Lines Matching +full:ch3 +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * Derived from cx25840-core.c
11 #include "cx18-driver.h"
12 #include "cx18-io.h"
13 #include "cx18-cards.h"
17 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write()
18 u32 mask = 0xff; in cx18_av_write()
24 return 0; in cx18_av_write()
29 u32 reg = 0xc40000 + (addr & ~3); in cx18_av_write_expect()
33 x = (x & ~((u32)0xff << shift)) | ((u32)value << shift); in cx18_av_write_expect()
36 return 0; in cx18_av_write_expect()
41 cx18_write_reg(cx, value, 0xc40000 + addr); in cx18_av_write4()
42 return 0; in cx18_av_write4()
48 cx18_write_reg_expect(cx, value, 0xc40000 + addr, eval, mask); in cx18_av_write4_expect()
49 return 0; in cx18_av_write4_expect()
54 cx18_write_reg_noretry(cx, value, 0xc40000 + addr); in cx18_av_write4_noretry()
55 return 0; in cx18_av_write4_noretry()
60 u32 x = cx18_read_reg(cx, 0xc40000 + (addr & ~3)); in cx18_av_read()
63 return (x >> shift) & 0xff; in cx18_av_read()
68 return cx18_read_reg(cx, 0xc40000 + addr); in cx18_av_read4()
96 * VDCLK Integer = 0x0f, Post Divider = 0x04 in cx18_av_init()
97 * AIMCLK Integer = 0x0e, Post Divider = 0x16 in cx18_av_init()
99 cx18_av_write4(cx, CXADEC_PLL_CTRL1, 0x160e040f); in cx18_av_init()
101 /* VDCLK Fraction = 0x2be2fe */ in cx18_av_init()
102 /* xtal * 0xf.15f17f0/4 = 108 MHz: 432 MHz before post divide */ in cx18_av_init()
103 cx18_av_write4(cx, CXADEC_VID_PLL_FRAC, 0x002be2fe); in cx18_av_init()
105 /* AIMCLK Fraction = 0x05227ad */ in cx18_av_init()
106 /* xtal * 0xe.2913d68/0x16 = 48000 * 384: 406 MHz pre post-div*/ in cx18_av_init()
107 cx18_av_write4(cx, CXADEC_AUX_PLL_FRAC, 0x005227ad); in cx18_av_init()
109 /* SA_MCLK_SEL=1, SA_MCLK_DIV=0x16 */ in cx18_av_init()
110 cx18_av_write(cx, CXADEC_I2S_MCLK, 0x56); in cx18_av_init()
122 cx18_av_write4_expect(cx, CXADEC_DL_CTL, 0x03000000, in cx18_av_initialize()
123 0x03000000, 0x13000000); in cx18_av_initialize()
127 /* enable sleep mode - register appears to be read only... */ in cx18_av_initialize()
128 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v | 1, v, 0xfffe); in cx18_av_initialize()
130 cx18_av_write4_expect(cx, CXADEC_HOST_REG1, v & 0xfffe, in cx18_av_initialize()
131 v & 0xfffe, 0xffff); in cx18_av_initialize()
134 v = cx18_av_read4(cx, CXADEC_DLL1_DIAG_CTRL) & 0xE1FFFEFF; in cx18_av_initialize()
138 cx18_av_write4(cx, CXADEC_DLL1_DIAG_CTRL, v | 0x10000100); in cx18_av_initialize()
140 v = cx18_av_read4(cx, CXADEC_DLL2_DIAG_CTRL) & 0xE1FFFEFF; in cx18_av_initialize()
144 cx18_av_write4(cx, CXADEC_DLL2_DIAG_CTRL, v | 0x06000100); in cx18_av_initialize()
147 cx18_av_write4(cx, CXADEC_AFE_DIAG_CTRL1, 0x000A1802); in cx18_av_initialize()
151 cx18_av_write4_expect(cx, CXADEC_AFE_DIAG_CTRL3, v, v, 0x03009F0F); in cx18_av_initialize()
154 v & 0xFFFFFFFE, v & 0xFFFFFFFE, 0x03009F0F); in cx18_av_initialize()
157 cx18_av_and_or4(cx, CXADEC_PIN_CTRL1, ~0, 0x040C00); in cx18_av_initialize()
160 cx18_av_and_or4(cx, CXADEC_PIN_CTRL2, ~0, 0x2); in cx18_av_initialize()
163 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0x8000); in cx18_av_initialize()
164 cx18_av_write4(cx, CXADEC_SOFT_RST_CTRL, 0); in cx18_av_initialize()
167 * Disable Video Auto-config of the Analog Front End and Video PLL. in cx18_av_initialize()
171 * 0x102 (CXADEC_CHIP_CTRL), 0x104-0x106 (CXADEC_AFE_CTRL), in cx18_av_initialize()
172 * 0x108-0x109 (CXADEC_PLL_CTRL1), and 0x10c-0x10f (CXADEC_VID_PLL_FRAC) in cx18_av_initialize()
173 * ourselves, than to run around cleaning up after the auto-config. in cx18_av_initialize()
179 * As a default, also turn off Dual mode for ADC2 and set ADC2 to CH3. in cx18_av_initialize()
181 cx18_av_and_or4(cx, CXADEC_CHIP_CTRL, 0xFFFBFFFF, 0x00120000); in cx18_av_initialize()
186 /* set video to auto-detect */ in cx18_av_initialize()
187 /* Clear bits 11-12 to enable slow locking mode. Set autodetect mode */ in cx18_av_initialize()
189 cx18_av_and_or4(cx, CXADEC_MODE_CTRL, 0xFFF7E7F0, 0x02040800); in cx18_av_initialize()
193 cx18_av_and_or4(cx, CXADEC_CRUSH_CTRL, ~0, 0x00500000); in cx18_av_initialize()
195 /* Set VGA_TRACK_RANGE to 0x20 */ in cx18_av_initialize()
196 cx18_av_and_or4(cx, CXADEC_DFE_CTRL2, 0xFFFF00FF, 0x00002000); in cx18_av_initialize()
200 * VIP-1.1, 10 bit mode, enable Raw, disable sliced, in cx18_av_initialize()
201 * don't clamp raw samples when codes are in use, 1 byte user D-words, in cx18_av_initialize()
205 cx18_av_write4(cx, CXADEC_OUT_CTRL1, 0x4013252e); in cx18_av_initialize()
209 /* EncSetSignalStd(dwDevNum, pEnc->dwSigStd); */ in cx18_av_initialize()
210 /* EncSetVideoInput(dwDevNum, pEnc->VidIndSelection); */ in cx18_av_initialize()
214 * Default to luma on ch1/ADC1, chroma on ch2/ADC2, SIF on ch3/ADC2 in cx18_av_initialize()
215 * bypass_ch[1-3] use filter in cx18_av_initialize()
216 * droop_comp_ch[1-3] disable in cx18_av_initialize()
217 * clamp_en_ch[1-3] disable in cx18_av_initialize()
221 * clamp_sel_ch[2-3] midcode in cx18_av_initialize()
224 * vga_sel_ch[1-2] video decoder in cx18_av_initialize()
225 * half_bw_ch[1-3] disable in cx18_av_initialize()
226 * +12db_ch[1-3] disable in cx18_av_initialize()
228 cx18_av_and_or4(cx, CXADEC_AFE_CTRL, 0xFF000000, 0x00005D00); in cx18_av_initialize()
231 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x7728021F); */ in cx18_av_initialize()
233 /* CxDevWrReg(CXADEC_SRC_COMB_CFG, 0x6628021F); */ in cx18_av_initialize()
235 cx18_av_write4(cx, CXADEC_SRC_COMB_CFG, 0x6628021F); in cx18_av_initialize()
236 default_volume = cx18_av_read(cx, 0x8d4); in cx18_av_initialize()
239 * -ERANGE errors when initializing the volume control in cx18_av_initialize()
242 /* Bottom out at -96 dB, v4l2 vol range 0x2e00-0x2fff */ in cx18_av_initialize()
244 cx18_av_write(cx, 0x8d4, 228); in cx18_av_initialize()
246 /* Top out at + 8 dB, v4l2 vol range 0xfe00-0xffff */ in cx18_av_initialize()
248 cx18_av_write(cx, 0x8d4, 20); in cx18_av_initialize()
250 default_volume = (((228 - default_volume) >> 1) + 23) << 9; in cx18_av_initialize()
251 state->volume->cur.val = state->volume->default_value = default_volume; in cx18_av_initialize()
252 v4l2_ctrl_handler_setup(&state->hdl); in cx18_av_initialize()
258 return 0; in cx18_av_reset()
265 if (!state->is_initialized) { in cx18_av_load_fw()
267 state->is_initialized = 1; in cx18_av_load_fw()
270 return 0; in cx18_av_load_fw()
275 struct cx18_av_state *state = &cx->av_state; in cx18_av_std_setup()
276 struct v4l2_subdev *sd = &state->sd; in cx18_av_std_setup()
277 v4l2_std_id std = state->std; in cx18_av_std_setup()
281 * 28.636360 MHz/13.5 Mpps * 256 = 0x21f.07b in cx18_av_std_setup()
283 const int src_decimation = 0x21f; in cx18_av_std_setup()
292 cx18_av_write(cx, 0x49f, 0x11); in cx18_av_std_setup()
294 cx18_av_write(cx, 0x49f, 0x14); in cx18_av_std_setup()
300 * 5 (625) or 6 (525) half-lines to blank for the vertical retrace in cx18_av_std_setup()
302 * 5 (625) or 6 (525) half-lines of equalization pulses in cx18_av_std_setup()
308 * 10 = vblank656 - vblank = vsync pulses + equalization pulses in cx18_av_std_setup()
310 * vblank656: half lines after line 625/mid-313 of blanked video in cx18_av_std_setup()
317 * vsync pulse (start of line 1 or mid-313) in cx18_av_std_setup()
322 * from lines 6-23 and lines 318-335 (but the slicer can only in cx18_av_std_setup()
334 * without them (at least when a PVR-350 is the PAL source). in cx18_av_std_setup()
336 vblank656 = 48; /* lines 1 - 24 & 313 - 336 */ in cx18_av_std_setup()
337 vblank = 38; /* lines 6 - 24 & 318 - 336 */ in cx18_av_std_setup()
338 vactive = 579; /* lines 24 - 313 & 337 - 626 */ in cx18_av_std_setup()
342 * 864 pixels = 720 active + 144 blanking. ITU-R BT.601 in cx18_av_std_setup()
361 comb = 0x20; in cx18_av_std_setup()
366 comb = 0x20; in cx18_av_std_setup()
370 uv_lpf = 0; in cx18_av_std_setup()
371 comb = 0; in cx18_av_std_setup()
380 * 12 = vblank656 - vblank = vsync pulses + equalization pulses in cx18_av_std_setup()
382 * prevsync: 6 half-lines before the vsync pulses in cx18_av_std_setup()
383 * vblank656: half lines, after line 3/mid-266, of blanked video in cx18_av_std_setup()
389 * vsync pulse (start of line 4 or mid-266) in cx18_av_std_setup()
394 * from lines 10-21 and lines 273-284. in cx18_av_std_setup()
396 vblank656 = 38; /* lines 4 - 22 & 266 - 284 */ in cx18_av_std_setup()
397 vblank = 26; /* lines 10 - 22 & 272 - 284 */ in cx18_av_std_setup()
398 vactive = 481; /* lines 23 - 263 & 285 - 525 */ in cx18_av_std_setup()
422 comb = 0x20; in cx18_av_std_setup()
426 /* The 97 needs to be verified against PAL-M timings */ in cx18_av_std_setup()
428 comb = 0x20; in cx18_av_std_setup()
433 comb = 0x66; in cx18_av_std_setup()
440 pll_int = cx18_av_read(cx, 0x108); in cx18_av_std_setup()
441 pll_frac = cx18_av_read4(cx, 0x10c) & 0x1ffffff; in cx18_av_std_setup()
442 pll_post = cx18_av_read(cx, 0x109); in cx18_av_std_setup()
465 "Chroma sub-carrier initial freq = %d.%06d MHz\n", in cx18_av_std_setup()
469 …ank %i, vactive %i, vblank656 %i, src_dec %i, burst 0x%02x, luma_lpf %i, uv_lpf %i, comb 0x%02x, s… in cx18_av_std_setup()
476 cx18_av_write(cx, 0x470, hblank); in cx18_av_std_setup()
477 cx18_av_write(cx, 0x471, in cx18_av_std_setup()
478 (((hblank >> 8) & 0x3) | (hactive << 4)) & 0xff); in cx18_av_std_setup()
479 cx18_av_write(cx, 0x472, hactive >> 4); in cx18_av_std_setup()
482 cx18_av_write(cx, 0x473, burst); in cx18_av_std_setup()
485 cx18_av_write(cx, 0x474, vblank); in cx18_av_std_setup()
486 cx18_av_write(cx, 0x475, in cx18_av_std_setup()
487 (((vblank >> 8) & 0x3) | (vactive << 4)) & 0xff); in cx18_av_std_setup()
488 cx18_av_write(cx, 0x476, vactive >> 4); in cx18_av_std_setup()
489 cx18_av_write(cx, 0x477, vblank656); in cx18_av_std_setup()
492 cx18_av_write(cx, 0x478, src_decimation & 0xff); in cx18_av_std_setup()
493 cx18_av_write(cx, 0x479, (src_decimation >> 8) & 0xff); in cx18_av_std_setup()
496 cx18_av_write(cx, 0x47a, luma_lpf << 6 | ((uv_lpf << 4) & 0x30)); in cx18_av_std_setup()
499 cx18_av_write(cx, 0x47b, comb); in cx18_av_std_setup()
502 cx18_av_write(cx, 0x47c, sc); in cx18_av_std_setup()
503 cx18_av_write(cx, 0x47d, (sc >> 8) & 0xff); in cx18_av_std_setup()
504 cx18_av_write(cx, 0x47e, (sc >> 16) & 0xff); in cx18_av_std_setup()
507 state->slicer_line_delay = 1; in cx18_av_std_setup()
508 state->slicer_line_offset = (6 + state->slicer_line_delay - 2); in cx18_av_std_setup()
510 state->slicer_line_delay = 0; in cx18_av_std_setup()
511 state->slicer_line_offset = (10 + state->slicer_line_delay - 2); in cx18_av_std_setup()
513 cx18_av_write(cx, 0x47f, state->slicer_line_delay); in cx18_av_std_setup()
518 struct cx18_av_state *state = &cx->av_state; in input_change()
519 v4l2_std_id std = state->std; in input_change()
523 cx18_av_write(cx, 0x49f, (std & V4L2_STD_NTSC) ? 0x14 : 0x11); in input_change()
524 cx18_av_and_or(cx, 0x401, ~0x60, 0); in input_change()
525 cx18_av_and_or(cx, 0x401, ~0x60, 0x60); in input_change()
530 cx18_av_write_expect(cx, 0x808, 0xf7, 0xf7, 0xff); in input_change()
531 cx18_av_write_expect(cx, 0x80b, 0x02, 0x02, 0x3f); in input_change()
534 cx18_av_write_expect(cx, 0x808, 0xf8, 0xf8, 0xff); in input_change()
535 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); in input_change()
538 cx18_av_write_expect(cx, 0x808, 0xf6, 0xf6, 0xff); in input_change()
539 cx18_av_write_expect(cx, 0x80b, 0x01, 0x01, 0x3f); in input_change()
543 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); in input_change()
544 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); in input_change()
547 cx18_av_write_expect(cx, 0x808, 0xff, 0xff, 0xff); in input_change()
548 cx18_av_write_expect(cx, 0x80b, 0x03, 0x03, 0x3f); in input_change()
551 v = cx18_av_read(cx, 0x803); in input_change()
552 if (v & 0x10) { in input_change()
554 v &= ~0x10; in input_change()
555 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); in input_change()
556 v |= 0x10; in input_change()
557 cx18_av_write_expect(cx, 0x803, v, v, 0x1f); in input_change()
566 return 0; in cx18_av_s_frequency()
572 struct cx18_av_state *state = &cx->av_state; in set_input()
573 struct v4l2_subdev *sd = &state->sd; in set_input()
590 afe_mux_cfg = 0xf0 + (vid_input - CX18_AV_COMPOSITE1); in set_input()
591 ch[0] = CVBS; in set_input()
592 input_mode = 0x0; in set_input()
594 int luma = vid_input & 0xf000; in set_input()
595 int r_chroma = vid_input & 0xf0000; in set_input()
596 int b_chroma = vid_input & 0xf00000; in set_input()
598 if ((vid_input & ~0xfff000) || in set_input()
605 CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n", in set_input()
607 return -EINVAL; in set_input()
609 afe_mux_cfg = (luma - CX18_AV_COMPONENT_LUMA1) >> 12; in set_input()
610 ch[0] = Y; in set_input()
611 afe_mux_cfg |= (r_chroma - CX18_AV_COMPONENT_R_CHROMA4) >> 12; in set_input()
613 afe_mux_cfg |= (b_chroma - CX18_AV_COMPONENT_B_CHROMA7) >> 14; in set_input()
615 input_mode = 0x6; in set_input()
617 int luma = vid_input & 0xf0; in set_input()
618 int chroma = vid_input & 0xf00; in set_input()
620 if ((vid_input & ~0xff0) || in set_input()
625 CX18_ERR_DEV(sd, "0x%06x is not a valid video input!\n", in set_input()
627 return -EINVAL; in set_input()
629 afe_mux_cfg = 0xf0 + ((luma - CX18_AV_SVIDEO_LUMA1) >> 4); in set_input()
630 ch[0] = Y; in set_input()
632 afe_mux_cfg &= 0x3f; in set_input()
633 afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA7) >> 2; in set_input()
636 afe_mux_cfg &= 0xcf; in set_input()
637 afe_mux_cfg |= (chroma - CX18_AV_SVIDEO_CHROMA4) >> 4; in set_input()
640 input_mode = 0x2; in set_input()
649 afe_mux_cfg &= ~0x30; in set_input()
653 afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x10; in set_input()
657 afe_mux_cfg = (afe_mux_cfg & ~0x30) | 0x20; in set_input()
661 afe_mux_cfg &= ~0xc0; in set_input()
665 afe_mux_cfg = (afe_mux_cfg & ~0xc0) | 0x40; in set_input()
670 CX18_ERR_DEV(sd, "0x%04x is not a valid audio input!\n", in set_input()
672 return -EINVAL; in set_input()
676 cx18_av_write_expect(cx, 0x103, afe_mux_cfg, afe_mux_cfg, 0xf7); in set_input()
677 /* Set INPUT_MODE to Composite, S-Video, or Component */ in set_input()
678 cx18_av_and_or(cx, 0x401, ~0x6, input_mode); in set_input()
680 /* Set CH_SEL_ADC2 to 1 if input comes from CH3 */ in set_input()
681 adc2_cfg = cx18_av_read(cx, 0x102); in set_input()
683 adc2_cfg &= ~0x2; /* No sig on CH3, set ADC2 to CH2 for input */ in set_input()
685 adc2_cfg |= 0x2; /* Signal on CH3, set ADC2 to CH3 for input */ in set_input()
687 /* Set DUAL_MODE_ADC2 to 1 if input comes from both CH2 and CH3 */ in set_input()
689 adc2_cfg |= 0x4; /* Set dual mode */ in set_input()
691 adc2_cfg &= ~0x4; /* Clear dual mode */ in set_input()
692 cx18_av_write_expect(cx, 0x102, adc2_cfg, adc2_cfg, 0x17); in set_input()
696 afe_cfg &= 0xff000000; in set_input()
697 afe_cfg |= 0x00005000; /* CHROMA_IN, AUD_IN: ADC2; LUMA_IN: ADC1 */ in set_input()
699 afe_cfg |= 0x00000030; /* half_bw_ch[2-3] since in dual mode */ in set_input()
701 for (i = 0; i < 3; i++) { in set_input()
706 afe_cfg |= (0x00000200 << i); in set_input()
710 if (i > 0) in set_input()
711 afe_cfg |= 0x00002000; /* LUMA_IN_SEL: ADC2 */ in set_input()
717 afe_cfg |= (0x00000200 << i); in set_input()
718 if (i == 0 && ch[i] == C) in set_input()
719 afe_cfg &= ~0x00001000; /* CHROMA_IN_SEL ADC1 */ in set_input()
726 afe_cfg |= (0x00000240 << i); in set_input()
727 if (i == 0) in set_input()
728 afe_cfg &= ~0x00004000; /* AUD_IN_SEL ADC1 */ in set_input()
735 state->vid_input = vid_input; in set_input()
736 state->aud_input = aud_input; in set_input()
739 return 0; in set_input()
747 return set_input(cx, input, state->aud_input); in cx18_av_s_video_routing()
755 return set_input(cx, state->vid_input, input); in cx18_av_s_audio_routing()
764 int val = 0; in cx18_av_g_tuner()
766 if (state->radio) in cx18_av_g_tuner()
767 return 0; in cx18_av_g_tuner()
769 vpres = cx18_av_read(cx, 0x40e) & 0x20; in cx18_av_g_tuner()
770 vt->signal = vpres ? 0xffff : 0x0; in cx18_av_g_tuner()
772 vt->capability |= in cx18_av_g_tuner()
776 mode = cx18_av_read(cx, 0x804); in cx18_av_g_tuner()
779 if ((mode & 0xf) == 1) in cx18_av_g_tuner()
787 if (mode & 0x10) in cx18_av_g_tuner()
790 vt->rxsubchans = val; in cx18_av_g_tuner()
791 vt->audmode = state->audmode; in cx18_av_g_tuner()
792 return 0; in cx18_av_g_tuner()
801 if (state->radio) in cx18_av_s_tuner()
802 return 0; in cx18_av_s_tuner()
804 v = cx18_av_read(cx, 0x809); in cx18_av_s_tuner()
805 v &= ~0xf; in cx18_av_s_tuner()
807 switch (vt->audmode) { in cx18_av_s_tuner()
809 /* mono -> mono in cx18_av_s_tuner()
810 stereo -> mono in cx18_av_s_tuner()
811 bilingual -> lang1 */ in cx18_av_s_tuner()
815 /* mono -> mono in cx18_av_s_tuner()
816 stereo -> stereo in cx18_av_s_tuner()
817 bilingual -> lang1 */ in cx18_av_s_tuner()
818 v |= 0x4; in cx18_av_s_tuner()
821 /* mono -> mono in cx18_av_s_tuner()
822 stereo -> stereo in cx18_av_s_tuner()
823 bilingual -> lang1/lang2 */ in cx18_av_s_tuner()
824 v |= 0x7; in cx18_av_s_tuner()
827 /* mono -> mono in cx18_av_s_tuner()
828 stereo -> stereo in cx18_av_s_tuner()
829 bilingual -> lang2 */ in cx18_av_s_tuner()
830 v |= 0x1; in cx18_av_s_tuner()
833 return -EINVAL; in cx18_av_s_tuner()
835 cx18_av_write_expect(cx, 0x809, v, v, 0xff); in cx18_av_s_tuner()
836 state->audmode = vt->audmode; in cx18_av_s_tuner()
837 return 0; in cx18_av_s_tuner()
845 u8 fmt = 0; /* zero is autodetect */ in cx18_av_s_std()
846 u8 pal_m = 0; in cx18_av_s_std()
848 if (state->radio == 0 && state->std == norm) in cx18_av_s_std()
849 return 0; in cx18_av_s_std()
851 state->radio = 0; in cx18_av_s_std()
852 state->std = norm; in cx18_av_s_std()
855 if (state->std == V4L2_STD_NTSC_M_JP) { in cx18_av_s_std()
856 fmt = 0x2; in cx18_av_s_std()
857 } else if (state->std == V4L2_STD_NTSC_443) { in cx18_av_s_std()
858 fmt = 0x3; in cx18_av_s_std()
859 } else if (state->std == V4L2_STD_PAL_M) { in cx18_av_s_std()
861 fmt = 0x5; in cx18_av_s_std()
862 } else if (state->std == V4L2_STD_PAL_N) { in cx18_av_s_std()
863 fmt = 0x6; in cx18_av_s_std()
864 } else if (state->std == V4L2_STD_PAL_Nc) { in cx18_av_s_std()
865 fmt = 0x7; in cx18_av_s_std()
866 } else if (state->std == V4L2_STD_PAL_60) { in cx18_av_s_std()
867 fmt = 0x8; in cx18_av_s_std()
870 if (state->std & V4L2_STD_NTSC) in cx18_av_s_std()
871 fmt = 0x1; in cx18_av_s_std()
872 else if (state->std & V4L2_STD_PAL) in cx18_av_s_std()
873 fmt = 0x4; in cx18_av_s_std()
874 else if (state->std & V4L2_STD_SECAM) in cx18_av_s_std()
875 fmt = 0xc; in cx18_av_s_std()
884 /* Set format to NTSC-M */ in cx18_av_s_std()
885 cx18_av_and_or(cx, 0x400, ~0xf, 1); in cx18_av_s_std()
887 cx18_av_and_or(cx, 0x47b, ~6, 0); in cx18_av_s_std()
889 cx18_av_and_or(cx, 0x400, ~0x2f, fmt | 0x20); in cx18_av_s_std()
890 cx18_av_and_or(cx, 0x403, ~0x3, pal_m); in cx18_av_s_std()
893 return 0; in cx18_av_s_std()
899 state->radio = 1; in cx18_av_s_radio()
900 return 0; in cx18_av_s_radio()
908 switch (ctrl->id) { in cx18_av_s_ctrl()
910 cx18_av_write(cx, 0x414, ctrl->val - 128); in cx18_av_s_ctrl()
914 cx18_av_write(cx, 0x415, ctrl->val << 1); in cx18_av_s_ctrl()
918 cx18_av_write(cx, 0x420, ctrl->val << 1); in cx18_av_s_ctrl()
919 cx18_av_write(cx, 0x421, ctrl->val << 1); in cx18_av_s_ctrl()
923 cx18_av_write(cx, 0x422, ctrl->val); in cx18_av_s_ctrl()
927 return -EINVAL; in cx18_av_s_ctrl()
929 return 0; in cx18_av_s_ctrl()
936 struct v4l2_mbus_framefmt *fmt = &format->format; in cx18_av_set_fmt()
940 int is_50Hz = !(state->std & V4L2_STD_525_60); in cx18_av_set_fmt()
942 if (format->pad || fmt->code != MEDIA_BUS_FMT_FIXED) in cx18_av_set_fmt()
943 return -EINVAL; in cx18_av_set_fmt()
945 fmt->field = V4L2_FIELD_INTERLACED; in cx18_av_set_fmt()
946 fmt->colorspace = V4L2_COLORSPACE_SMPTE170M; in cx18_av_set_fmt()
948 Vsrc = (cx18_av_read(cx, 0x476) & 0x3f) << 4; in cx18_av_set_fmt()
949 Vsrc |= (cx18_av_read(cx, 0x475) & 0xf0) >> 4; in cx18_av_set_fmt()
951 Hsrc = (cx18_av_read(cx, 0x472) & 0x3f) << 4; in cx18_av_set_fmt()
952 Hsrc |= (cx18_av_read(cx, 0x471) & 0xf0) >> 4; in cx18_av_set_fmt()
961 Vlines = fmt->height + (is_50Hz ? 3 : 1); in cx18_av_set_fmt()
970 if ((fmt->width * 16 < Hsrc) || (Hsrc < fmt->width) || in cx18_av_set_fmt()
973 fmt->width, fmt->height); in cx18_av_set_fmt()
974 return -ERANGE; in cx18_av_set_fmt()
977 if (format->which == V4L2_SUBDEV_FORMAT_TRY) in cx18_av_set_fmt()
978 return 0; in cx18_av_set_fmt()
980 HSC = (Hsrc * (1 << 20)) / fmt->width - (1 << 20); in cx18_av_set_fmt()
981 VSC = (1 << 16) - (Vsrc * (1 << 9) / Vlines - (1 << 9)); in cx18_av_set_fmt()
982 VSC &= 0x1fff; in cx18_av_set_fmt()
984 if (fmt->width >= 385) in cx18_av_set_fmt()
985 filter = 0; in cx18_av_set_fmt()
986 else if (fmt->width > 192) in cx18_av_set_fmt()
988 else if (fmt->width > 96) in cx18_av_set_fmt()
994 "decoder set size %dx%d -> scale %ux%u\n", in cx18_av_set_fmt()
995 fmt->width, fmt->height, HSC, VSC); in cx18_av_set_fmt()
998 cx18_av_write(cx, 0x418, HSC & 0xff); in cx18_av_set_fmt()
999 cx18_av_write(cx, 0x419, (HSC >> 8) & 0xff); in cx18_av_set_fmt()
1000 cx18_av_write(cx, 0x41a, HSC >> 16); in cx18_av_set_fmt()
1002 cx18_av_write(cx, 0x41c, VSC & 0xff); in cx18_av_set_fmt()
1003 cx18_av_write(cx, 0x41d, VSC >> 8); in cx18_av_set_fmt()
1005 cx18_av_write(cx, 0x41e, 0x8 | filter); in cx18_av_set_fmt()
1006 return 0; in cx18_av_set_fmt()
1015 cx18_av_write(cx, 0x115, 0x8c); in cx18_av_s_stream()
1016 cx18_av_write(cx, 0x116, 0x07); in cx18_av_s_stream()
1018 cx18_av_write(cx, 0x115, 0x00); in cx18_av_s_stream()
1019 cx18_av_write(cx, 0x116, 0x00); in cx18_av_s_stream()
1021 return 0; in cx18_av_s_stream()
1027 "0x0", in log_video_status()
1028 "NTSC-M", "NTSC-J", "NTSC-4.43", in log_video_status()
1029 "PAL-BDGHI", "PAL-M", "PAL-N", "PAL-Nc", "PAL-60", in log_video_status()
1030 "0x9", "0xA", "0xB", in log_video_status()
1032 "0xD", "0xE", "0xF" in log_video_status()
1035 struct cx18_av_state *state = &cx->av_state; in log_video_status()
1036 struct v4l2_subdev *sd = &state->sd; in log_video_status()
1037 u8 vidfmt_sel = cx18_av_read(cx, 0x400) & 0xf; in log_video_status()
1038 u8 gen_stat1 = cx18_av_read(cx, 0x40d); in log_video_status()
1039 u8 gen_stat2 = cx18_av_read(cx, 0x40e); in log_video_status()
1040 int vid_input = state->vid_input; in log_video_status()
1043 (gen_stat2 & 0x20) ? "" : "not "); in log_video_status()
1045 fmt_strs[gen_stat1 & 0xf]); in log_video_status()
1054 vid_input - CX18_AV_COMPOSITE1 + 1); in log_video_status()
1056 CX18_INFO_DEV(sd, "Specified video input: S-Video (Luma In%d, Chroma In%d)\n", in log_video_status()
1057 (vid_input & 0xf0) >> 4, in log_video_status()
1058 (vid_input & 0xf00) >> 8); in log_video_status()
1062 state->audclk_freq); in log_video_status()
1067 struct cx18_av_state *state = &cx->av_state; in log_audio_status()
1068 struct v4l2_subdev *sd = &state->sd; in log_audio_status()
1069 u8 download_ctl = cx18_av_read(cx, 0x803); in log_audio_status()
1070 u8 mod_det_stat0 = cx18_av_read(cx, 0x804); in log_audio_status()
1071 u8 mod_det_stat1 = cx18_av_read(cx, 0x805); in log_audio_status()
1072 u8 audio_config = cx18_av_read(cx, 0x808); in log_audio_status()
1073 u8 pref_mode = cx18_av_read(cx, 0x809); in log_audio_status()
1074 u8 afc0 = cx18_av_read(cx, 0x80b); in log_audio_status()
1075 u8 mute_ctl = cx18_av_read(cx, 0x8d3); in log_audio_status()
1076 int aud_input = state->aud_input; in log_audio_status()
1080 case 0x00: p = "mono"; break; in log_audio_status()
1081 case 0x01: p = "stereo"; break; in log_audio_status()
1082 case 0x02: p = "dual"; break; in log_audio_status()
1083 case 0x04: p = "tri"; break; in log_audio_status()
1084 case 0x10: p = "mono with SAP"; break; in log_audio_status()
1085 case 0x11: p = "stereo with SAP"; break; in log_audio_status()
1086 case 0x12: p = "dual with SAP"; break; in log_audio_status()
1087 case 0x14: p = "tri with SAP"; break; in log_audio_status()
1088 case 0xfe: p = "forced mode"; break; in log_audio_status()
1094 case 0x00: p = "not defined"; break; in log_audio_status()
1095 case 0x01: p = "EIAJ"; break; in log_audio_status()
1096 case 0x02: p = "A2-M"; break; in log_audio_status()
1097 case 0x03: p = "A2-BG"; break; in log_audio_status()
1098 case 0x04: p = "A2-DK1"; break; in log_audio_status()
1099 case 0x05: p = "A2-DK2"; break; in log_audio_status()
1100 case 0x06: p = "A2-DK3"; break; in log_audio_status()
1101 case 0x07: p = "A1 (6.0 MHz FM Mono)"; break; in log_audio_status()
1102 case 0x08: p = "AM-L"; break; in log_audio_status()
1103 case 0x09: p = "NICAM-BG"; break; in log_audio_status()
1104 case 0x0a: p = "NICAM-DK"; break; in log_audio_status()
1105 case 0x0b: p = "NICAM-I"; break; in log_audio_status()
1106 case 0x0c: p = "NICAM-L"; break; in log_audio_status()
1107 case 0x0d: p = "BTSC/EIAJ/A2-M Mono (4.5 MHz FMMono)"; break; in log_audio_status()
1108 case 0x0e: p = "IF FM Radio"; break; in log_audio_status()
1109 case 0x0f: p = "BTSC"; break; in log_audio_status()
1110 case 0x10: p = "detected chrominance"; break; in log_audio_status()
1111 case 0xfd: p = "unknown audio standard"; break; in log_audio_status()
1112 case 0xfe: p = "forced audio standard"; break; in log_audio_status()
1113 case 0xff: p = "no detected audio standard"; break; in log_audio_status()
1118 (mute_ctl & 0x2) ? "yes" : "no"); in log_audio_status()
1120 (download_ctl & 0x10) ? "running" : "stopped"); in log_audio_status()
1123 case 0x00: p = "undefined"; break; in log_audio_status()
1124 case 0x01: p = "BTSC"; break; in log_audio_status()
1125 case 0x02: p = "EIAJ"; break; in log_audio_status()
1126 case 0x03: p = "A2-M"; break; in log_audio_status()
1127 case 0x04: p = "A2-BG"; break; in log_audio_status()
1128 case 0x05: p = "A2-DK1"; break; in log_audio_status()
1129 case 0x06: p = "A2-DK2"; break; in log_audio_status()
1130 case 0x07: p = "A2-DK3"; break; in log_audio_status()
1131 case 0x08: p = "A1 (6.0 MHz FM Mono)"; break; in log_audio_status()
1132 case 0x09: p = "AM-L"; break; in log_audio_status()
1133 case 0x0a: p = "NICAM-BG"; break; in log_audio_status()
1134 case 0x0b: p = "NICAM-DK"; break; in log_audio_status()
1135 case 0x0c: p = "NICAM-I"; break; in log_audio_status()
1136 case 0x0d: p = "NICAM-L"; break; in log_audio_status()
1137 case 0x0e: p = "FM radio"; break; in log_audio_status()
1138 case 0x0f: p = "automatic detection"; break; in log_audio_status()
1143 if ((audio_config >> 4) < 0xF) { in log_audio_status()
1144 switch (audio_config & 0xF) { in log_audio_status()
1145 case 0x00: p = "MONO1 (LANGUAGE A/Mono L+R channel for BTSC, EIAJ, A2)"; break; in log_audio_status()
1146 case 0x01: p = "MONO2 (LANGUAGE B)"; break; in log_audio_status()
1147 case 0x02: p = "MONO3 (STEREO forced MONO)"; break; in log_audio_status()
1148 case 0x03: p = "MONO4 (NICAM ANALOG-Language C/Analog Fallback)"; break; in log_audio_status()
1149 case 0x04: p = "STEREO"; break; in log_audio_status()
1150 case 0x05: p = "DUAL1 (AC)"; break; in log_audio_status()
1151 case 0x06: p = "DUAL2 (BC)"; break; in log_audio_status()
1152 case 0x07: p = "DUAL3 (AB)"; break; in log_audio_status()
1157 switch (audio_config & 0xF) { in log_audio_status()
1158 case 0x00: p = "BG"; break; in log_audio_status()
1159 case 0x01: p = "DK1"; break; in log_audio_status()
1160 case 0x02: p = "DK2"; break; in log_audio_status()
1161 case 0x03: p = "DK3"; break; in log_audio_status()
1162 case 0x04: p = "I"; break; in log_audio_status()
1163 case 0x05: p = "L"; break; in log_audio_status()
1164 case 0x06: p = "BTSC"; break; in log_audio_status()
1165 case 0x07: p = "EIAJ"; break; in log_audio_status()
1166 case 0x08: p = "A2-M"; break; in log_audio_status()
1167 case 0x09: p = "FM Radio (4.5 MHz)"; break; in log_audio_status()
1168 case 0x0a: p = "FM Radio (5.5 MHz)"; break; in log_audio_status()
1169 case 0x0b: p = "S-Video"; break; in log_audio_status()
1170 case 0x0f: p = "automatic standard and mode detection"; break; in log_audio_status()
1182 switch (pref_mode & 0xf) { in log_audio_status()
1183 case 0: p = "mono/language A"; break; in log_audio_status()
1195 if ((audio_config & 0xf) == 0xf) { in log_audio_status()
1196 switch ((afc0 >> 3) & 0x1) { in log_audio_status()
1197 case 0: p = "system DK"; break; in log_audio_status()
1202 switch (afc0 & 0x7) { in log_audio_status()
1203 case 0: p = "Chroma"; break; in log_audio_status()
1206 case 3: p = "A2-M"; break; in log_audio_status()
1219 return 0; in cx18_av_log_status()
1228 if ((reg->reg & 0x3) != 0) in cx18_av_g_register()
1229 return -EINVAL; in cx18_av_g_register()
1230 reg->size = 4; in cx18_av_g_register()
1231 reg->val = cx18_av_read4(cx, reg->reg & 0x00000ffc); in cx18_av_g_register()
1232 return 0; in cx18_av_g_register()
1240 if ((reg->reg & 0x3) != 0) in cx18_av_s_register()
1241 return -EINVAL; in cx18_av_s_register()
1242 cx18_av_write4(cx, reg->reg & 0x00000ffc, reg->val); in cx18_av_s_register()
1243 return 0; in cx18_av_s_register()
1301 struct cx18_av_state *state = &cx->av_state; in cx18_av_probe()
1305 state->rev = cx18_av_read4(cx, CXADEC_CHIP_CTRL) & 0xffff; in cx18_av_probe()
1307 state->vid_input = CX18_AV_COMPOSITE7; in cx18_av_probe()
1308 state->aud_input = CX18_AV_AUDIO8; in cx18_av_probe()
1309 state->audclk_freq = 48000; in cx18_av_probe()
1310 state->audmode = V4L2_TUNER_MODE_LANG1; in cx18_av_probe()
1311 state->slicer_line_delay = 0; in cx18_av_probe()
1312 state->slicer_line_offset = (10 + state->slicer_line_delay - 2); in cx18_av_probe()
1314 sd = &state->sd; in cx18_av_probe()
1317 snprintf(sd->name, sizeof(sd->name), in cx18_av_probe()
1318 "%s %03x", cx->v4l2_dev.name, (state->rev >> 4)); in cx18_av_probe()
1319 sd->grp_id = CX18_HW_418_AV; in cx18_av_probe()
1320 v4l2_ctrl_handler_init(&state->hdl, 9); in cx18_av_probe()
1321 v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, in cx18_av_probe()
1322 V4L2_CID_BRIGHTNESS, 0, 255, 1, 128); in cx18_av_probe()
1323 v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, in cx18_av_probe()
1324 V4L2_CID_CONTRAST, 0, 127, 1, 64); in cx18_av_probe()
1325 v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, in cx18_av_probe()
1326 V4L2_CID_SATURATION, 0, 127, 1, 64); in cx18_av_probe()
1327 v4l2_ctrl_new_std(&state->hdl, &cx18_av_ctrl_ops, in cx18_av_probe()
1328 V4L2_CID_HUE, -128, 127, 1, 0); in cx18_av_probe()
1330 state->volume = v4l2_ctrl_new_std(&state->hdl, in cx18_av_probe()
1332 0, 65535, 65535 / 100, 0); in cx18_av_probe()
1333 v4l2_ctrl_new_std(&state->hdl, in cx18_av_probe()
1335 0, 1, 1, 0); in cx18_av_probe()
1336 v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, in cx18_av_probe()
1338 0, 65535, 65535 / 100, 32768); in cx18_av_probe()
1339 v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, in cx18_av_probe()
1341 0, 65535, 65535 / 100, 32768); in cx18_av_probe()
1342 v4l2_ctrl_new_std(&state->hdl, &cx18_av_audio_ctrl_ops, in cx18_av_probe()
1344 0, 65535, 65535 / 100, 32768); in cx18_av_probe()
1345 sd->ctrl_handler = &state->hdl; in cx18_av_probe()
1346 if (state->hdl.error) { in cx18_av_probe()
1347 int err = state->hdl.error; in cx18_av_probe()
1349 v4l2_ctrl_handler_free(&state->hdl); in cx18_av_probe()
1352 err = v4l2_device_register_subdev(&cx->v4l2_dev, sd); in cx18_av_probe()
1354 v4l2_ctrl_handler_free(&state->hdl); in cx18_av_probe()