Lines Matching +full:0 +full:xf005
38 #define THP7312_REG_FIRMWARE_VERSION_1 CCI_REG8(0xf000)
39 #define THP7312_REG_CAMERA_STATUS CCI_REG8(0xf001)
40 #define THP7312_REG_FIRMWARE_VERSION_2 CCI_REG8(0xf005)
41 #define THP7312_REG_SET_OUTPUT_ENABLE CCI_REG8(0xf008)
42 #define THP7312_OUTPUT_ENABLE 0x01
43 #define THP7312_OUTPUT_DISABLE 0x00
44 #define THP7312_REG_SET_OUTPUT_COLOR_COMPRESSION CCI_REG8(0xf009)
45 #define THP7312_REG_SET_OUTPUT_COLOR_UYVY 0x00
46 #define THP7312_REG_SET_OUTPUT_COLOR_YUY2 0x04
47 #define THP7312_REG_FLIP_MIRROR CCI_REG8(0xf00c)
48 #define THP7312_REG_FLIP_MIRROR_FLIP BIT(0)
50 #define THP7312_REG_VIDEO_IMAGE_SIZE CCI_REG8(0xf00d)
51 #define THP7312_VIDEO_IMAGE_SIZE_640x360 0x52
52 #define THP7312_VIDEO_IMAGE_SIZE_640x460 0x03
53 #define THP7312_VIDEO_IMAGE_SIZE_1280x720 0x0a
54 #define THP7312_VIDEO_IMAGE_SIZE_1920x1080 0x0b
55 #define THP7312_VIDEO_IMAGE_SIZE_3840x2160 0x0d
56 #define THP7312_VIDEO_IMAGE_SIZE_4160x3120 0x14
57 #define THP7312_VIDEO_IMAGE_SIZE_2016x1512 0x20
58 #define THP7312_VIDEO_IMAGE_SIZE_2048x1536 0x21
59 #define THP7312_REG_VIDEO_FRAME_RATE_MODE CCI_REG8(0xf00f)
60 #define THP7312_VIDEO_FRAME_RATE_MODE1 0x80
61 #define THP7312_VIDEO_FRAME_RATE_MODE2 0x81
62 #define THP7312_VIDEO_FRAME_RATE_MODE3 0x82
63 #define THP7312_REG_SET_DRIVING_MODE CCI_REG8(0xf010)
64 #define THP7312_REG_DRIVING_MODE_STATUS CCI_REG8(0xf011)
65 #define THP7312_REG_JPEG_COMPRESSION_FACTOR CCI_REG8(0xf01b)
66 #define THP7312_REG_AE_EXPOSURE_COMPENSATION CCI_REG8(0xf022)
67 #define THP7312_REG_AE_FLICKER_MODE CCI_REG8(0xf023)
68 #define THP7312_AE_FLICKER_MODE_50 0x00
69 #define THP7312_AE_FLICKER_MODE_60 0x01
70 #define THP7312_AE_FLICKER_MODE_DISABLE 0x80
71 #define THP7312_REG_AE_FIX_FRAME_RATE CCI_REG8(0xf02e)
72 #define THP7312_REG_MANUAL_WB_RED_GAIN CCI_REG8(0xf036)
73 #define THP7312_REG_MANUAL_WB_BLUE_GAIN CCI_REG8(0xf037)
74 #define THP7312_REG_WB_MODE CCI_REG8(0xf039)
75 #define THP7312_WB_MODE_AUTO 0x00
76 #define THP7312_WB_MODE_MANUAL 0x11
77 #define THP7312_REG_MANUAL_FOCUS_POSITION CCI_REG16(0xf03c)
78 #define THP7312_REG_AF_CONTROL CCI_REG8(0xf040)
79 #define THP7312_REG_AF_CONTROL_AF 0x01
80 #define THP7312_REG_AF_CONTROL_MANUAL 0x10
81 #define THP7312_REG_AF_CONTROL_LOCK 0x80
82 #define THP7312_REG_AF_SETTING CCI_REG8(0xf041)
83 #define THP7312_REG_AF_SETTING_ONESHOT_CONTRAST 0x00
84 #define THP7312_REG_AF_SETTING_ONESHOT_PDAF 0x40
85 #define THP7312_REG_AF_SETTING_ONESHOT_HYBRID 0x80
86 #define THP7312_REG_AF_SETTING_CONTINUOUS_CONTRAST 0x30
87 #define THP7312_REG_AF_SETTING_CONTINUOUS_PDAF 0x70
88 #define THP7312_REG_AF_SETTING_CONTINUOUS_HYBRID 0xf0
89 #define THP7312_REG_AF_SUPPORT CCI_REG8(0xf043)
91 #define THP7312_AF_SUPPORT_CONTRAST BIT(0)
92 #define THP7312_REG_SATURATION CCI_REG8(0xf052)
93 #define THP7312_REG_SHARPNESS CCI_REG8(0xf053)
94 #define THP7312_REG_BRIGHTNESS CCI_REG8(0xf056)
95 #define THP7312_REG_CONTRAST CCI_REG8(0xf057)
96 #define THP7312_REG_NOISE_REDUCTION CCI_REG8(0xf059)
99 #define TH7312_REG_CUSTOM_MIPI_SET CCI_REG8(0xf0f6)
100 #define TH7312_REG_CUSTOM_MIPI_STATUS CCI_REG8(0xf0f7)
101 #define TH7312_REG_CUSTOM_MIPI_RD CCI_REG8(0xf0f8)
102 #define TH7312_REG_CUSTOM_MIPI_TD CCI_REG8(0xf0f9)
109 #define THP7312_REG_FW_DRIVABILITY CCI_REG32(0xd65c)
110 #define THP7312_REG_FW_DEST_BANK_ADDR CCI_REG32(0xff08)
111 #define THP7312_REG_FW_VERIFY_RESULT CCI_REG8(0xff60)
112 #define THP7312_REG_FW_RESET_FLASH CCI_REG8(0xff61)
113 #define THP7312_REG_FW_MEMORY_IO_SETTING CCI_REG8(0xff62)
115 #define THP7312_FW_MEMORY_IO_GPIO1 0
116 #define THP7312_REG_FW_CRC_RESULT CCI_REG32(0xff64)
117 #define THP7312_REG_FW_STATUS CCI_REG8(0xfffc)
121 #define THP7312_FW_VERSION_MINOR(v) ((v) & 0xff)
169 THP7312_BOOT_MODE_2WIRE_SLAVE = 0,
197 "vddgpio-0",
207 { 30, 300000000, 0x81 },
208 { 60, 387500000, 0x82 },
209 { 0 }
216 { 30, 300000000, 0x81 },
217 { 0 }
224 { 30, 600000000, 0x81 },
225 { 0 }
232 { 20, 600000000, 0x81 },
233 { 0 }
366 u8 used_lanes = 0; in thp7312_map_data_lanes()
367 u8 val = 0; in thp7312_map_data_lanes()
375 for (i = 0; i < num_lanes; i++) { in thp7312_map_data_lanes()
386 * register is 0-indexed. in thp7312_map_data_lanes()
393 return 0; in thp7312_map_data_lanes()
399 int ret = 0; in thp7312_set_mipi_lanes()
403 thp7312->sensors[0].lane_remap, &ret); in thp7312_set_mipi_lanes()
412 val, val == 0x00, 100000, 2000000); in thp7312_set_mipi_lanes()
418 return 0; in thp7312_set_mipi_lanes()
426 u64 val = 0; in thp7312_change_mode()
430 val == 0x80, 20000, 200000); in thp7312_change_mode()
431 if (ret < 0) { in thp7312_change_mode()
440 cci_write(thp7312->regmap, THP7312_REG_JPEG_COMPRESSION_FACTOR, 0x5e, in thp7312_change_mode()
442 cci_write(thp7312->regmap, THP7312_REG_SET_DRIVING_MODE, 0x01, &ret); in thp7312_change_mode()
448 val, val == 0x01, 20000, 100000); in thp7312_change_mode()
449 if (ret < 0) { in thp7312_change_mode()
454 return 0; in thp7312_change_mode()
493 fmt = v4l2_subdev_state_get_format(sd_state, 0); in thp7312_init_mode()
494 interval = v4l2_subdev_state_get_interval(sd_state, 0); in thp7312_init_mode()
519 u64 status = 0; in thp7312_check_status_stream_mode()
522 while (status != 0x80) { in thp7312_check_status_stream_mode()
528 if (status == 0x80) { in thp7312_check_status_stream_mode()
530 return 0; in thp7312_check_status_stream_mode()
533 if (status != 0x00) { in thp7312_check_status_stream_mode()
542 return 0; in thp7312_check_status_stream_mode()
558 gpiod_set_value_cansleep(thp7312->reset_gpio, 0); in thp7312_reset()
591 if (ret < 0) in __thp7312_power_on()
595 if (ret < 0) { in __thp7312_power_on()
608 return 0; in __thp7312_power_on()
616 if (ret < 0) in thp7312_power_on()
620 if (ret < 0) in thp7312_power_on()
627 return 0; in thp7312_power_on()
643 return 0; in thp7312_pm_runtime_suspend()
667 for (i = 0; i < ARRAY_SIZE(thp7312_colour_fmts); ++i) { in thp7312_find_bus_code()
684 return 0; in thp7312_enum_mbus_code()
702 return 0; in thp7312_enum_frame_size()
725 return 0; in thp7312_enum_frame_interval()
743 mbus_fmt->code = thp7312_colour_fmts[0]; in thp7312_set_fmt()
747 fmt = v4l2_subdev_state_get_format(sd_state, 0); in thp7312_set_fmt()
759 interval = v4l2_subdev_state_get_interval(sd_state, 0); in thp7312_set_fmt()
761 interval->denominator = mode->rates[0].fps; in thp7312_set_fmt()
764 thp7312->link_freq = mode->rates[0].link_freq; in thp7312_set_fmt()
766 return 0; in thp7312_set_fmt()
780 /* Avoid divisions by 0, pick the highest frame if the interval is 0. */ in thp7312_set_frame_interval()
785 fmt = v4l2_subdev_state_get_format(sd_state, 0); in thp7312_set_frame_interval()
789 interval = v4l2_subdev_state_get_interval(sd_state, 0); in thp7312_set_frame_interval()
798 return 0; in thp7312_set_frame_interval()
817 return 0; in thp7312_s_stream()
854 const struct thp7312_mode_info *default_mode = &thp7312_mode_info_data[0]; in thp7312_init_state()
858 fmt = v4l2_subdev_state_get_format(sd_state, 0); in thp7312_init_state()
859 interval = v4l2_subdev_state_get_interval(sd_state, 0); in thp7312_init_state()
875 interval->denominator = default_mode->rates[0].fps; in thp7312_init_state()
877 return 0; in thp7312_init_state()
919 /* 0: 3000cm, 18: 8cm */
933 int ret = 0; in thp7312_set_focus()
988 return 0; in thp7312_set_focus()
1043 return 0; in thp7312_set_focus()
1049 int ret = 0; in thp7312_s_ctrl()
1056 return 0; in thp7312_s_ctrl()
1065 /* 0 = Auto adjust frame rate, 1 = Fix frame rate */ in thp7312_s_ctrl()
1067 ctrl->val ? 0 : 1, &ret); in thp7312_s_ctrl()
1079 value = (thp7312->hflip->val ? THP7312_REG_FLIP_MIRROR_MIRROR : 0) in thp7312_s_ctrl()
1080 | (thp7312->vflip->val ? THP7312_REG_FLIP_MIRROR_FLIP : 0); in thp7312_s_ctrl()
1087 value = thp7312->noise_reduction_auto->val ? 0 in thp7312_s_ctrl()
1194 .min = 0,
1203 .min = 0,
1212 .min = 0,
1213 .def = 0,
1220 -2000, -1667, -1333, -1000, -667, -333, 0, 333, 667, 1000, 1333, 1667, 2000
1255 + (af_support ? 4 : 0); in thp7312_init_controls()
1271 0, 1, 1, 1); in thp7312_init_controls()
1275 0, ARRAY_SIZE(thp7312_focus_values), in thp7312_init_controls()
1276 1, 0); in thp7312_init_controls()
1288 0, 1, 1, 1); in thp7312_init_controls()
1297 -10, 10, 1, 0); in thp7312_init_controls()
1299 0, 31, 1, 10); in thp7312_init_controls()
1301 0, 20, 1, 10); in thp7312_init_controls()
1303 0, 31, 1, 8); in thp7312_init_controls()
1306 V4L2_CID_HFLIP, 0, 1, 1, 0); in thp7312_init_controls()
1308 V4L2_CID_VFLIP, 0, 1, 1, 0); in thp7312_init_controls()
1319 V4L2_CID_POWER_LINE_FREQUENCY_60HZ, 0, in thp7312_init_controls()
1322 thp7312->link_freq = thp7312_mode_info_data[0].rates[0].link_freq; in thp7312_init_controls()
1325 V4L2_CID_LINK_FREQ, 0, 0, in thp7312_init_controls()
1341 for (i = 0; i < ARRAY_SIZE(thp7312_v4l2_ctrls_custom); i++) { in thp7312_init_controls()
1397 0xd5, 0x18, 0x00, 0x00, 0x00, 0x80
1401 0xd5, 0x0c, 0x80, 0x00, 0x00, 0x00
1405 0xd5, 0x04
1414 * Source address always starts from 0
1416 static const u8 thp7312_cmd_write_ram_to_flash[] = { 0xff, 0x70, 0x0f };
1425 static const u8 thp7312_cmd_calc_crc[] = { 0xff, 0x70, 0x09 };
1427 static const u8 thp7312_jedec_rdid[] = { SPINOR_OP_RDID, 0x00, 0x00, 0x00 };
1428 static const u8 thp7312_jedec_rdsr[] = { SPINOR_OP_RDSR, 0x00, 0x00, 0x00 };
1433 u64 val = 0; in thp7312_read_firmware_version()
1434 int ret = 0; in thp7312_read_firmware_version()
1455 return ret >= 0 ? 0 : ret; in thp7312_write_buf()
1473 if (ret < 0) { in __thp7312_flash_reg_write()
1479 temp_write_buf[0] = 0xd5; in __thp7312_flash_reg_write()
1480 temp_write_buf[1] = 0x00; in __thp7312_flash_reg_write()
1483 if (ret < 0) in __thp7312_flash_reg_write()
1489 return 0; in __thp7312_flash_reg_write()
1504 msgs[0].addr = client->addr; in __thp7312_flash_reg_read()
1505 msgs[0].flags = 0; in __thp7312_flash_reg_read()
1506 msgs[0].len = sizeof(thp7312_cmd_read_reg); in __thp7312_flash_reg_read()
1507 msgs[0].buf = (u8 *)thp7312_cmd_read_reg; in __thp7312_flash_reg_read()
1515 return ret >= 0 ? 0 : ret; in __thp7312_flash_reg_read()
1538 ret = cci_write(thp7312->regmap, THP7312_REG_FW_DRIVABILITY, 0x00777777, in thp7312_fw_prepare_config()
1551 u8 read_buf[3] = { 0 }; in thp7312_fw_prepare_check()
1561 dev_dbg(dev, "Flash Memory: JEDEC ID = 0x%x 0x%x 0x%x\n", in thp7312_fw_prepare_check()
1562 read_buf[0], read_buf[1], read_buf[2]); in thp7312_fw_prepare_check()
1572 ret = cci_write(thp7312->regmap, THP7312_REG_FW_RESET_FLASH, 0x81, NULL); in thp7312_fw_prepare_reset()
1585 u8 read_buf[1] = { 0 }; in thp7312_flash_erase()
1590 for (block = 0; block < 3; block++) { in thp7312_flash_erase()
1591 const u8 jedec_se[] = { SPINOR_OP_SE, block, 0x00, 0x00 }; in thp7312_flash_erase()
1594 if (ret < 0) { in thp7312_flash_erase()
1600 if (ret < 0) { in thp7312_flash_erase()
1605 for (i = 0; i < THP7312_FLASH_MEMORY_ERASE_TIMEOUT; i++) { in thp7312_flash_erase()
1610 /* Check Busy bit. Busy == 0x0 means erase complete. */ in thp7312_flash_erase()
1611 if (!(read_buf[0] & SR_WIP)) in thp7312_flash_erase()
1622 if (read_buf[0] & SR_WEL) in thp7312_flash_erase()
1637 dev_dbg(dev, "%s: addr = 0x%04x, data = 0x%p, size = %u\n", in thp7312_write_download_data_by_unit()
1640 write_buf[0] = (addr >> 8) & 0xff; in thp7312_write_download_data_by_unit()
1641 write_buf[1] = (addr >> 0) & 0xff; in thp7312_write_download_data_by_unit()
1646 * Command ID (address to download): 0x0000 - 0x7fff in thp7312_write_download_data_by_unit()
1650 if (ret < 0) in thp7312_write_download_data_by_unit()
1653 return ret >= 0 ? FW_UPLOAD_ERR_NONE : FW_UPLOAD_ERR_RW_ERROR; in thp7312_write_download_data_by_unit()
1669 for (i = 0; i < num_banks; i++) { in thp7312_fw_load_to_ram()
1670 const u32 bank_addr = 0x10000000 | (i * THP7312_RAM_BANK_SIZE); in thp7312_fw_load_to_ram()
1685 for (j = 0 ; j < num_chunks; j++) { in thp7312_fw_load_to_ram()
1718 command[cmd_size] = (dest & 0xff0000) >> 16; in thp7312_fw_write_to_flash()
1719 command[cmd_size + 1] = (dest & 0x00ff00) >> 8; in thp7312_fw_write_to_flash()
1720 command[cmd_size + 2] = (dest & 0x0000ff); in thp7312_fw_write_to_flash()
1721 command[cmd_size + 3] = ((write_size - 1) & 0xff0000) >> 16; in thp7312_fw_write_to_flash()
1722 command[cmd_size + 4] = ((write_size - 1) & 0x00ff00) >> 8; in thp7312_fw_write_to_flash()
1723 command[cmd_size + 5] = ((write_size - 1) & 0x0000ff); in thp7312_fw_write_to_flash()
1726 if (ret < 0) in thp7312_fw_write_to_flash()
1733 if (ret < 0) in thp7312_fw_write_to_flash()
1753 command[cmd_size] = 0; in thp7312_fw_check_crc()
1754 command[cmd_size + 1] = (header_size >> 8) & 0xff; in thp7312_fw_check_crc()
1755 command[cmd_size + 2] = header_size & 0xff; in thp7312_fw_check_crc()
1757 command[cmd_size + 3] = (size >> 16) & 0xff; in thp7312_fw_check_crc()
1758 command[cmd_size + 4] = (size >> 8) & 0xff; in thp7312_fw_check_crc()
1759 command[cmd_size + 5] = size & 0xff; in thp7312_fw_check_crc()
1762 if (ret < 0) in thp7312_fw_check_crc()
1770 if (ret < 0) in thp7312_fw_check_crc()
1774 dev_err(dev, "CRC mismatch: firmware 0x%08x, flash 0x%08llx\n", in thp7312_fw_check_crc()
1843 ret = thp7312_fw_write_to_flash(thp7312, 0, 0x1ffff); in thp7312_fw_write()
1851 ret = thp7312_fw_write_to_flash(thp7312, 0x20000, header_size - 1); in thp7312_fw_write()
1909 if (ret < 0) in thp7312_register_flash_mode()
1927 return 0; in thp7312_register_flash_mode()
1942 for (i = 0; i < ARRAY_SIZE(thp7312->supplies); i++) in thp7312_get_regulators()
1964 if (ret < 0) { in thp7312_sensor_parse_dt()
1981 if (ret < 0) { in thp7312_sensor_parse_dt()
1986 for (i = 0; i < ARRAY_SIZE(thp7312_sensor_info); i++) { in thp7312_sensor_parse_dt()
2003 if (ret < 0) { in thp7312_sensor_parse_dt()
2008 for (i = 0; i < ARRAY_SIZE(data_lanes); ++i) in thp7312_sensor_parse_dt()
2018 return 0; in thp7312_sensor_parse_dt()
2029 unsigned int num_sensors = 0; in thp7312_parse_dt()
2087 return 0; in thp7312_parse_dt()
2108 if (ret < 0) in thp7312_probe()
2148 if (ret < 0) { in thp7312_probe()
2163 if (ret < 0) { in thp7312_probe()
2180 if (ret < 0) { in thp7312_probe()
2196 return 0; in thp7312_probe()