media/i2c/tda1997x_regs.h

1 /* SPDX-License-Identifier: GPL-2.0 */
6 /* Page 0x00 - General Control */
128 #define DETECT_UTIL		BIT(7)	/* utility of HDMI level */
129 #define DETECT_HPD		BIT(6)	/* HPD of HDMI level */
130 #define DETECT_5V_SEL		BIT(2)	/* 5V present on selected input */
131 #define DETECT_5V_B		BIT(1)	/* 5V present on input B */
132 #define DETECT_5V_A		BIT(0)	/* 5V present on input A */
135 #define INPUT_SEL_RST_FMT	BIT(7)	/* 1=reset format measurement */
136 #define INPUT_SEL_RST_VDP	BIT(2)	/* 1=reset video data path */
137 #define INPUT_SEL_OUT_MODE	BIT(1)	/* 0=loop 1=bypass */
138 #define INPUT_SEL_B		BIT(0)	/* 0=inputA 1=inputB */
144 #define SVC_MODE_CLK2_XTLDIV2	1L
149 #define SVC_MODE_CLK1_XTLDIV2	1L
151 #define SVC_MODE_RAMP		BIT(3)	/* 0=colorbar 1=ramp */
152 #define SVC_MODE_PAL		BIT(2)	/* 0=NTSC(480i/p) 1=PAL(576i/p) */
153 #define SVC_MODE_INT_PROG	BIT(1)	/* 0=interlaced 1=progressive */
154 #define SVC_MODE_SM_ON		BIT(0)	/* Enable color bars and tone gen */
157 #define HPD_MAN_CTRL_HPD_PULSE	BIT(7)	/* HPD Pulse low 110ms */
158 #define HPD_MAN_CTRL_5VEN	BIT(2)	/* Output 5V */
159 #define HPD_MAN_CTRL_HPD_B	BIT(1)	/* Assert HPD High for Input A */
160 #define HPD_MAN_CTRL_HPD_A	BIT(0)	/* Assert HPD High for Input A */
163 #define RT_MAN_CTRL_RT_AUTO	BIT(7)
164 #define RT_MAN_CTRL_RT		BIT(6)
165 #define RT_MAN_CTRL_RT_B	BIT(1)	/* enable TMDS pull-up on Input B */
166 #define RT_MAN_CTRL_RT_A	BIT(0)	/* enable TMDS pull-up on Input A */
169 #define VDP_CTRL_COMPDEL_BP	BIT(5)	/* bypass compdel */
170 #define VDP_CTRL_FORMATTER_BP	BIT(4)	/* bypass formatter */
171 #define VDP_CTRL_PREFILTER_BP	BIT(1)	/* bypass prefilter */
172 #define VDP_CTRL_MATRIX_BP	BIT(0)	/* bypass matrix conversion */
175 #define VHREF_INT_DET		BIT(7)	/* interlace detect: 1=alt 0=frame */
179 #define VHREF_VSYNC_FDW		1L
185 #define VHREF_STD_DET_NTSC	1L
188 #define VHREF_VREF_SRC_STD	BIT(2)	/* 1=from standard 0=manual */
189 #define VHREF_HREF_SRC_STD	BIT(1)	/* 1=from standard 0=manual */
190 #define VHREF_HSYNC_SEL_HS	BIT(0)	/* 1=HS 0=VS */
193 #define AUDIO_OUT_ENABLE_ACLK	BIT(5)
194 #define AUDIO_OUT_ENABLE_WS	BIT(4)
195 #define AUDIO_OUT_ENABLE_AP3	BIT(3)
196 #define AUDIO_OUT_ENABLE_AP2	BIT(2)
197 #define AUDIO_OUT_ENABLE_AP1	BIT(1)
198 #define AUDIO_OUT_ENABLE_AP0	BIT(0)
206 #define FILTERS_CTRL_2TAP	1L	/* 2 Taps */
212 #define PCLK_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
217 #define PCLK_SEL_X2		1L
225 #define PIX_REPEAT_CHROMA	1
227 /* Page 0x01 - HDMI info and packets */
238 #define HDMI_FLAGS_AUDIO	BIT(7)	/* Audio packet in last videoframe */
239 #define HDMI_FLAGS_HDMI		BIT(6)	/* HDMI detected */
240 #define HDMI_FLAGS_EESS		BIT(5)	/* EESS detected */
241 #define HDMI_FLAGS_HDCP		BIT(4)	/* HDCP detected */
242 #define HDMI_FLAGS_AVMUTE	BIT(3)	/* AVMUTE */
243 #define HDMI_FLAGS_AUD_LAYOUT	BIT(2)	/* Layout status Audio sample packet */
244 #define HDMI_FLAGS_AUD_FIFO_OF	BIT(1)	/* FIFO read/write pointers crossed */
245 #define HDMI_FLAGS_AUD_FIFO_LOW	BIT(0)	/* FIFO read ptr within 2 of write */
247 /* Page 0x12 - HDMI Extra control and debug */
269 #define PON_EN			1
273 #define CLK_CFG_INV_OUT_CLK	BIT(7)
274 #define CLK_CFG_INV_BUS_CLK	BIT(6)
275 #define CLK_CFG_SEL_ACLK_EN	BIT(1)
276 #define CLK_CFG_SEL_ACLK	BIT(0)
279 /* Page 0x13 - HDMI Extra control and debug */
302 #define HDCP_DE_REGEN_EN	BIT(5)	/* enable regen mode */
311 #define HDCP_DE_COMP_CH1	1L
326 #define HDMI_CTRL_MUTE_OFF	1L
331 #define HDMI_CTRL_HDCP_OESS	1L
337 #define CGU_DBG_XO_FRO_SEL	BIT(2)
338 #define CGU_DBG_VDP_CLK_SEL	BIT(1)
339 #define CGU_DBG_PIX_CLK_SEL	BIT(0)
342 #define MAN_DIS_OUT_BUF		BIT(7)
343 #define MAN_DIS_ANA_PATH	BIT(6)
344 #define MAN_DIS_HDCP		BIT(5)
345 #define MAN_DIS_TMDS_ENC	BIT(4)
346 #define MAN_DIS_TMDS_FLOW	BIT(3)
347 #define MAN_RST_HDCP		BIT(2)
348 #define MAN_RST_TMDS_ENC	BIT(1)
349 #define MAN_RST_TMDS_FLOW	BIT(0)
351 /* Page 0x14 - Audio Extra control and debug */
359 #define AUDIO_CLOCK_PLL_PD	BIT(7)	/* powerdown PLL */
362 #define AUDIO_CLOCK_SEL_32FS	1L	/* 32*fs */
378 #define EDID_ENABLE_NACK_OFF	BIT(7)
379 #define EDID_ENABLE_EDID_ONLY	BIT(6)
380 #define EDID_ENABLE_B_EN	BIT(1)
381 #define EDID_ENABLE_A_EN	BIT(0)
387 #define HPD_POWER_BP_HIGH	1L
388 #define HPD_POWER_EDID_ONLY	BIT(1)
391 #define HPD_AUTO_READ_EDID	BIT(7)
392 #define HPD_AUTO_HPD_F3TECH	BIT(5)
393 #define HPD_AUTO_HP_OTHER	BIT(4)
394 #define HPD_AUTO_HPD_UNSEL	BIT(3)
395 #define HPD_AUTO_HPD_ALL_CH	BIT(2)
396 #define HPD_AUTO_HPD_PRV_CH	BIT(1)
397 #define HPD_AUTO_HPD_NEW_CH	BIT(0)
399 /* Page 0x21 - EDID content */
409 /* Page 0x30 - NV Configuration */
429 /* Page 0x80 - CEC */
436 #define INTERRUPT_AFE		BIT(7) /* AFE module */
437 #define INTERRUPT_HDCP		BIT(6) /* HDCP module */
438 #define INTERRUPT_AUDIO		BIT(5) /* Audio module */
439 #define INTERRUPT_INFO		BIT(4) /* Infoframe module */
440 #define INTERRUPT_MODE		BIT(3) /* HDMI mode module */
441 #define INTERRUPT_RATE		BIT(2) /* rate module */
442 #define INTERRUPT_DDC		BIT(1) /* DDC module */
443 #define INTERRUPT_SUS		BIT(0) /* SUS module */
446 #define MASK_HDCP_MTP		BIT(7) /* HDCP MTP busy */
447 #define MASK_HDCP_DLMTP		BIT(4) /* HDCP end download MTP to SRAM */
448 #define MASK_HDCP_DLRAM		BIT(3) /* HDCP end download keys from SRAM */
449 #define MASK_HDCP_ENC		BIT(2) /* HDCP ENC */
450 #define MASK_STATE_C5		BIT(1) /* HDCP State C5 reached */
451 #define MASK_AKSV		BIT(0) /* AKSV received (start of auth) */
454 #define MASK_RATE_B_DRIFT	BIT(7) /* Rate measurement drifted */
455 #define MASK_RATE_B_ST		BIT(6) /* Rate measurement stability change */
456 #define MASK_RATE_B_ACT		BIT(5) /* Rate measurement activity change */
457 #define MASK_RATE_B_PST		BIT(4) /* Rate measreument presence change */
458 #define MASK_RATE_A_DRIFT	BIT(3) /* Rate measurement drifted */
459 #define MASK_RATE_A_ST		BIT(2) /* Rate measurement stability change */
460 #define MASK_RATE_A_ACT		BIT(1) /* Rate measurement presence change */
461 #define MASK_RATE_A_PST		BIT(0) /* Rate measreument presence change */
464 #define MASK_MPT		BIT(7) /* Config MTP end of process */
465 #define MASK_FMT		BIT(5) /* Video format changed */
466 #define MASK_RT_PULSE		BIT(4) /* End of termination resistance pulse */
467 #define MASK_SUS_END		BIT(3) /* SUS last state reached */
468 #define MASK_SUS_ACT		BIT(2) /* Activity of selected input changed */
469 #define MASK_SUS_CH		BIT(1) /* Selected input changed */
470 #define MASK_SUS_ST		BIT(0) /* SUS state changed */
473 #define MASK_EDID_MTP		BIT(7) /* EDID MTP end of process */
474 #define MASK_DDC_ERR		BIT(6) /* master DDC error */
475 #define MASK_DDC_CMD_DONE	BIT(5) /* master DDC cmd send correct */
476 #define MASK_READ_DONE		BIT(4) /* End of down EDID read */
477 #define MASK_RX_DDC_SW		BIT(3) /* Output DDC switching finished */
478 #define MASK_HDCP_DDC_SW	BIT(2) /* HDCP DDC switching finished */
479 #define MASK_HDP_PULSE_END	BIT(1) /* End of Hot Plug Detect pulse */
480 #define MASK_DET_5V		BIT(0) /* Detection of +5V */
483 #define MASK_HDMI_FLG		BIT(7) /* HDMI mode/avmute/encrypt/FIFO fail */
484 #define MASK_GAMUT		BIT(6) /* Gamut packet */
485 #define MASK_ISRC2		BIT(5) /* ISRC2 packet */
486 #define MASK_ISRC1		BIT(4) /* ISRC1 packet */
487 #define MASK_ACP		BIT(3) /* Audio Content Protection packet */
488 #define MASK_DC_NO_GCP		BIT(2) /* GCP not received in 5 frames */
489 #define MASK_DC_PHASE		BIT(1) /* deepcolor pixel phase needs update */
490 #define MASK_DC_MODE		BIT(0) /* deepcolor color depth changed */
493 #define MASK_MPS_IF		BIT(6) /* MPEG Source Product */
494 #define MASK_AUD_IF		BIT(5) /* Audio */
495 #define MASK_SPD_IF		BIT(4) /* Source Product Descriptor */
496 #define MASK_AVI_IF		BIT(3) /* Auxiliary Video IF */
497 #define MASK_VS_IF_OTHER_BK2	BIT(2) /* Vendor Specific (bank2) */
498 #define MASK_VS_IF_OTHER_BK1	BIT(1) /* Vendor Specific (bank1) */
499 #define MASK_VS_IF_HDMI		BIT(0) /* Vendor Specific (w/ HDMI LLC code) */
502 #define MASK_AUDIO_FREQ_FLG	BIT(5) /* Audio freq change */
503 #define MASK_AUDIO_FLG		BIT(4) /* DST, OBA, HBR, ASP change */
504 #define MASK_MUTE_FLG		BIT(3) /* Audio Mute */
505 #define MASK_CH_STATE		BIT(2) /* Channel status */
506 #define MASK_UNMUTE_FIFO	BIT(1) /* Audio Unmute */
507 #define MASK_ERROR_FIFO_PT	BIT(0) /* Audio FIFO pointer error */
510 #define MASK_AFE_WDL_UNLOCKED	BIT(7) /* Wordlocker was unlocked */
511 #define MASK_AFE_GAIN_DONE	BIT(6) /* Gain calibration done */
512 #define MASK_AFE_OFFSET_DONE	BIT(5) /* Offset calibration done */
513 #define MASK_AFE_ACTIVITY_DET	BIT(4) /* Activity detected on data */
514 #define MASK_AFE_PLL_LOCK	BIT(3) /* TMDS PLL is locked */
515 #define MASK_AFE_TRMCAL_DONE	BIT(2) /* Termination calibration done */
516 #define MASK_AFE_ASU_STATE	BIT(1) /* ASU state is reached */
517 #define MASK_AFE_ASU_READY	BIT(0) /* AFE calibration done: TMDS ready */
520 #define AUDCFG_CLK_INVERT	BIT(7)	/* invert A_CLK polarity */
521 #define AUDCFG_TEST_TONE	BIT(6)	/* enable test tone generator */
524 #define AUDCFG_BUS_SPDIF	1L
527 #define AUDCFG_I2SW_32		1L
528 #define AUDCFG_AUTO_MUTE_EN	BIT(3)	/* Enable Automatic audio mute */
531 #define AUDCFG_HBR_DEMUX	1L	/* demuxed via AP0:AP3 */
535 #define AUDCFG_TYPE_OBA		2L	/* One Bit Audio (OBA) */
536 #define AUDCFG_TYPE_HBR		1L	/* High Bit Rate (HBR) */
540 #define OF_VP_ENABLE		BIT(7)	/* VP[35:0]/HS/VS/DE/CLK */
541 #define OF_BLK			BIT(4)	/* blanking codes */
542 #define OF_TRC			BIT(3)	/* timing codes (SAV/EAV) */
545 #define OF_FMT_422_SMPT		1L	/* YUV422 semi-planar */
550 #define HS_HREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
552 #define HS_HREF_INV_SHIFT	2	/* polarity (1=invert) */
556 #define HS_HREF_SEL_HREF_VHREF	1L	/* HREF from VHREF */
562 #define VS_VREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
563 #define VS_VREF_INV_SHIFT	2	/* polarity (1=invert) */
567 #define VS_VREF_SEL_VREF_VHREF	1L	/* VREF from VHREF */
573 #define DE_FREF_DELAY_SHIFT	4	/* Pixel delay (-8..+7) */
575 #define DE_FREF_INV_SHIFT	2	/* polarity (1=invert) */
579 #define DE_FREF_SEL_FREF_VHREF	1L	/* FREF from VHREF */
584 #define RESET_DC		BIT(7)	/* Reset deep color module */
585 #define RESET_HDCP		BIT(6)	/* Reset HDCP module */
586 #define RESET_KSV		BIT(5)	/* Reset KSV-FIFO */
587 #define RESET_SCFG		BIT(4)	/* Reset HDCP and repeater function */
588 #define RESET_HCFG		BIT(3)	/* Reset HDCP DDC part */
589 #define RESET_PA		BIT(2)	/* Reset polarity adjust */
590 #define RESET_EP		BIT(1)	/* Reset Error protection */
591 #define RESET_TMDS		BIT(0)	/* Reset TMDS (calib, encoding, flow) */
594 #define NACK_HDCP		BIT(7)	/* No ACK on HDCP request */
595 #define RESET_FIFO		BIT(4)	/* Reset Audio FIFO control */
596 #define RESET_GAMUT		BIT(3)	/* Clear Gamut packet */
597 #define RESET_AI		BIT(2)	/* Clear ACP and ISRC packets */
598 #define RESET_IF		BIT(1)	/* Clear all Audio infoframe packets */
599 #define RESET_AUDIO		BIT(0)	/* Reset Audio FIFO control */
602 #define HDCP_HDMI		BIT(7)	/* HDCP supports HDMI (vs DVI only) */
603 #define HDCP_REPEATER		BIT(6)	/* HDCP supports repeater function */
604 #define HDCP_READY		BIT(5)	/* set by repeater function */
605 #define HDCP_FAST		BIT(4)	/* Up to 400kHz */
606 #define HDCP_11			BIT(1)	/* HDCP 1.1 supported */
607 #define HDCP_FAST_REAUTH	BIT(0)	/* fast reauthentication supported */
610 #define AUDIO_LAYOUT_SP_FLAG	BIT(2)	/* sp flag used by FIFO */
611 #define AUDIO_LAYOUT_MANUAL	BIT(1)	/* manual layout (vs per pkt) */
612 #define AUDIO_LAYOUT_LAYOUT1	BIT(0)  /* Layout1: AP0-3 vs Layout0:AP0 */