Lines Matching +full:0 +full:x4301
36 #define OV8858_REG_ADDR_MASK 0xffff
41 #define OV8858_REG_SC_CTRL0100 OV8858_REG_8BIT(0x0100)
42 #define OV8858_MODE_SW_STANDBY 0x0
43 #define OV8858_MODE_STREAMING 0x1
45 #define OV8858_REG_CHIP_ID OV8858_REG_24BIT(0x300a)
46 #define OV8858_CHIP_ID 0x008858
48 #define OV8858_REG_SUB_ID OV8858_REG_8BIT(0x302a)
49 #define OV8858_R1A 0xb0
50 #define OV8858_R2A 0xb2
52 #define OV8858_REG_LONG_EXPO OV8858_REG_24BIT(0x3500)
57 #define OV8858_REG_LONG_GAIN OV8858_REG_16BIT(0x3508)
58 #define OV8858_LONG_GAIN_MIN 0x0
59 #define OV8858_LONG_GAIN_MAX 0x7ff
61 #define OV8858_LONG_GAIN_DEFAULT 0x80
63 #define OV8858_REG_LONG_DIGIGAIN OV8858_REG_16BIT(0x350a)
64 #define OV8858_LONG_DIGIGAIN_H_MASK 0x3fc0
65 #define OV8858_LONG_DIGIGAIN_L_MASK 0x3f
67 #define OV8858_LONG_DIGIGAIN_MIN 0x0
68 #define OV8858_LONG_DIGIGAIN_MAX 0x3fff
70 #define OV8858_LONG_DIGIGAIN_DEFAULT 0x200
72 #define OV8858_REG_VTS OV8858_REG_16BIT(0x380e)
73 #define OV8858_VTS_MAX 0x7fff
75 #define OV8858_REG_TEST_PATTERN OV8858_REG_8BIT(0x5e00)
76 #define OV8858_TEST_PATTERN_ENABLE 0x80
77 #define OV8858_TEST_PATTERN_DISABLE 0x0
79 #define REG_NULL 0xffff
131 {0x0100, 0x00},
132 {0x0100, 0x00},
133 {0x0100, 0x00},
134 {0x0100, 0x00},
135 {0x0302, 0x1e},
136 {0x0303, 0x00},
137 {0x0304, 0x03},
138 {0x030e, 0x00},
139 {0x030f, 0x09},
140 {0x0312, 0x01},
141 {0x031e, 0x0c},
142 {0x3600, 0x00},
143 {0x3601, 0x00},
144 {0x3602, 0x00},
145 {0x3603, 0x00},
146 {0x3604, 0x22},
147 {0x3605, 0x30},
148 {0x3606, 0x00},
149 {0x3607, 0x20},
150 {0x3608, 0x11},
151 {0x3609, 0x28},
152 {0x360a, 0x00},
153 {0x360b, 0x06},
154 {0x360c, 0xdc},
155 {0x360d, 0x40},
156 {0x360e, 0x0c},
157 {0x360f, 0x20},
158 {0x3610, 0x07},
159 {0x3611, 0x20},
160 {0x3612, 0x88},
161 {0x3613, 0x80},
162 {0x3614, 0x58},
163 {0x3615, 0x00},
164 {0x3616, 0x4a},
165 {0x3617, 0xb0},
166 {0x3618, 0x56},
167 {0x3619, 0x70},
168 {0x361a, 0x99},
169 {0x361b, 0x00},
170 {0x361c, 0x07},
171 {0x361d, 0x00},
172 {0x361e, 0x00},
173 {0x361f, 0x00},
174 {0x3638, 0xff},
175 {0x3633, 0x0c},
176 {0x3634, 0x0c},
177 {0x3635, 0x0c},
178 {0x3636, 0x0c},
179 {0x3645, 0x13},
180 {0x3646, 0x83},
181 {0x364a, 0x07},
182 {0x3015, 0x01},
183 {0x3018, 0x32},
184 {0x3020, 0x93},
185 {0x3022, 0x01},
186 {0x3031, 0x0a},
187 {0x3034, 0x00},
188 {0x3106, 0x01},
189 {0x3305, 0xf1},
190 {0x3308, 0x00},
191 {0x3309, 0x28},
192 {0x330a, 0x00},
193 {0x330b, 0x20},
194 {0x330c, 0x00},
195 {0x330d, 0x00},
196 {0x330e, 0x00},
197 {0x330f, 0x40},
198 {0x3307, 0x04},
199 {0x3500, 0x00},
200 {0x3501, 0x4d},
201 {0x3502, 0x40},
202 {0x3503, 0x00},
203 {0x3505, 0x80},
204 {0x3508, 0x04},
205 {0x3509, 0x00},
206 {0x350c, 0x00},
207 {0x350d, 0x80},
208 {0x3510, 0x00},
209 {0x3511, 0x02},
210 {0x3512, 0x00},
211 {0x3700, 0x18},
212 {0x3701, 0x0c},
213 {0x3702, 0x28},
214 {0x3703, 0x19},
215 {0x3704, 0x14},
216 {0x3705, 0x00},
217 {0x3706, 0x35},
218 {0x3707, 0x04},
219 {0x3708, 0x24},
220 {0x3709, 0x33},
221 {0x370a, 0x00},
222 {0x370b, 0xb5},
223 {0x370c, 0x04},
224 {0x3718, 0x12},
225 {0x3719, 0x31},
226 {0x3712, 0x42},
227 {0x3714, 0x24},
228 {0x371e, 0x19},
229 {0x371f, 0x40},
230 {0x3720, 0x05},
231 {0x3721, 0x05},
232 {0x3724, 0x06},
233 {0x3725, 0x01},
234 {0x3726, 0x06},
235 {0x3728, 0x05},
236 {0x3729, 0x02},
237 {0x372a, 0x03},
238 {0x372b, 0x53},
239 {0x372c, 0xa3},
240 {0x372d, 0x53},
241 {0x372e, 0x06},
242 {0x372f, 0x10},
243 {0x3730, 0x01},
244 {0x3731, 0x06},
245 {0x3732, 0x14},
246 {0x3733, 0x10},
247 {0x3734, 0x40},
248 {0x3736, 0x20},
249 {0x373a, 0x05},
250 {0x373b, 0x06},
251 {0x373c, 0x0a},
252 {0x373e, 0x03},
253 {0x3755, 0x10},
254 {0x3758, 0x00},
255 {0x3759, 0x4c},
256 {0x375a, 0x06},
257 {0x375b, 0x13},
258 {0x375c, 0x20},
259 {0x375d, 0x02},
260 {0x375e, 0x00},
261 {0x375f, 0x14},
262 {0x3768, 0x22},
263 {0x3769, 0x44},
264 {0x376a, 0x44},
265 {0x3761, 0x00},
266 {0x3762, 0x00},
267 {0x3763, 0x00},
268 {0x3766, 0xff},
269 {0x376b, 0x00},
270 {0x3772, 0x23},
271 {0x3773, 0x02},
272 {0x3774, 0x16},
273 {0x3775, 0x12},
274 {0x3776, 0x04},
275 {0x3777, 0x00},
276 {0x3778, 0x1b},
277 {0x37a0, 0x44},
278 {0x37a1, 0x3d},
279 {0x37a2, 0x3d},
280 {0x37a3, 0x00},
281 {0x37a4, 0x00},
282 {0x37a5, 0x00},
283 {0x37a6, 0x00},
284 {0x37a7, 0x44},
285 {0x37a8, 0x4c},
286 {0x37a9, 0x4c},
287 {0x3760, 0x00},
288 {0x376f, 0x01},
289 {0x37aa, 0x44},
290 {0x37ab, 0x2e},
291 {0x37ac, 0x2e},
292 {0x37ad, 0x33},
293 {0x37ae, 0x0d},
294 {0x37af, 0x0d},
295 {0x37b0, 0x00},
296 {0x37b1, 0x00},
297 {0x37b2, 0x00},
298 {0x37b3, 0x42},
299 {0x37b4, 0x42},
300 {0x37b5, 0x33},
301 {0x37b6, 0x00},
302 {0x37b7, 0x00},
303 {0x37b8, 0x00},
304 {0x37b9, 0xff},
305 {0x3800, 0x00},
306 {0x3801, 0x0c},
307 {0x3802, 0x00},
308 {0x3803, 0x0c},
309 {0x3804, 0x0c},
310 {0x3805, 0xd3},
311 {0x3806, 0x09},
312 {0x3807, 0xa3},
313 {0x3808, 0x06},
314 {0x3809, 0x60},
315 {0x380a, 0x04},
316 {0x380b, 0xc8},
317 {0x380c, 0x07},
318 {0x380d, 0x88},
319 {0x380e, 0x04},
320 {0x380f, 0xdc},
321 {0x3810, 0x00},
322 {0x3811, 0x04},
323 {0x3813, 0x02},
324 {0x3814, 0x03},
325 {0x3815, 0x01},
326 {0x3820, 0x00},
327 {0x3821, 0x67},
328 {0x382a, 0x03},
329 {0x382b, 0x01},
330 {0x3830, 0x08},
331 {0x3836, 0x02},
332 {0x3837, 0x18},
333 {0x3841, 0xff},
334 {0x3846, 0x48},
335 {0x3d85, 0x14},
336 {0x3f08, 0x08},
337 {0x3f0a, 0x80},
338 {0x4000, 0xf1},
339 {0x4001, 0x10},
340 {0x4005, 0x10},
341 {0x4002, 0x27},
342 {0x4009, 0x81},
343 {0x400b, 0x0c},
344 {0x401b, 0x00},
345 {0x401d, 0x00},
346 {0x4020, 0x00},
347 {0x4021, 0x04},
348 {0x4022, 0x04},
349 {0x4023, 0xb9},
350 {0x4024, 0x05},
351 {0x4025, 0x2a},
352 {0x4026, 0x05},
353 {0x4027, 0x2b},
354 {0x4028, 0x00},
355 {0x4029, 0x02},
356 {0x402a, 0x04},
357 {0x402b, 0x04},
358 {0x402c, 0x02},
359 {0x402d, 0x02},
360 {0x402e, 0x08},
361 {0x402f, 0x02},
362 {0x401f, 0x00},
363 {0x4034, 0x3f},
364 {0x403d, 0x04},
365 {0x4300, 0xff},
366 {0x4301, 0x00},
367 {0x4302, 0x0f},
368 {0x4316, 0x00},
369 {0x4500, 0x38},
370 {0x4503, 0x18},
371 {0x4600, 0x00},
372 {0x4601, 0xcb},
373 {0x481f, 0x32},
374 {0x4837, 0x16},
375 {0x4850, 0x10},
376 {0x4851, 0x32},
377 {0x4b00, 0x2a},
378 {0x4b0d, 0x00},
379 {0x4d00, 0x04},
380 {0x4d01, 0x18},
381 {0x4d02, 0xc3},
382 {0x4d03, 0xff},
383 {0x4d04, 0xff},
384 {0x4d05, 0xff},
385 {0x5000, 0x7e},
386 {0x5001, 0x01},
387 {0x5002, 0x08},
388 {0x5003, 0x20},
389 {0x5046, 0x12},
390 {0x5901, 0x00},
391 {0x5e00, 0x00},
392 {0x5e01, 0x41},
393 {0x382d, 0x7f},
394 {0x4825, 0x3a},
395 {0x4826, 0x40},
396 {0x4808, 0x25},
397 {REG_NULL, 0x00},
404 * AM19 : 3617 <- 0xC0
405 * AM20 : change FWC_6K_EN to be default 0x3618=0x5a
407 {0x0103, 0x01}, /* software reset */
408 {0x0100, 0x00}, /* software standby */
409 {0x0302, 0x1e}, /* pll1_multi */
410 {0x0303, 0x00}, /* pll1_divm */
411 {0x0304, 0x03}, /* pll1_div_mipi */
412 {0x030e, 0x02}, /* pll2_rdiv */
413 {0x030f, 0x04}, /* pll2_divsp */
414 {0x0312, 0x03}, /* pll2_pre_div0, pll2_r_divdac */
415 {0x031e, 0x0c}, /* pll1_no_lat */
416 {0x3600, 0x00},
417 {0x3601, 0x00},
418 {0x3602, 0x00},
419 {0x3603, 0x00},
420 {0x3604, 0x22},
421 {0x3605, 0x20},
422 {0x3606, 0x00},
423 {0x3607, 0x20},
424 {0x3608, 0x11},
425 {0x3609, 0x28},
426 {0x360a, 0x00},
427 {0x360b, 0x05},
428 {0x360c, 0xd4},
429 {0x360d, 0x40},
430 {0x360e, 0x0c},
431 {0x360f, 0x20},
432 {0x3610, 0x07},
433 {0x3611, 0x20},
434 {0x3612, 0x88},
435 {0x3613, 0x80},
436 {0x3614, 0x58},
437 {0x3615, 0x00},
438 {0x3616, 0x4a},
439 {0x3617, 0x90},
440 {0x3618, 0x5a},
441 {0x3619, 0x70},
442 {0x361a, 0x99},
443 {0x361b, 0x0a},
444 {0x361c, 0x07},
445 {0x361d, 0x00},
446 {0x361e, 0x00},
447 {0x361f, 0x00},
448 {0x3638, 0xff},
449 {0x3633, 0x0f},
450 {0x3634, 0x0f},
451 {0x3635, 0x0f},
452 {0x3636, 0x12},
453 {0x3645, 0x13},
454 {0x3646, 0x83},
455 {0x364a, 0x07},
456 {0x3015, 0x00},
457 {0x3018, 0x32}, /* MIPI 2 lane */
458 {0x3020, 0x93}, /* Clock switch output normal, pclk_div =/1 */
459 {0x3022, 0x01}, /* pd_mipi enable when rst_sync */
460 {0x3031, 0x0a}, /* MIPI 10-bit mode */
461 {0x3034, 0x00},
462 {0x3106, 0x01}, /* sclk_div, sclk_pre_div */
463 {0x3305, 0xf1},
464 {0x3308, 0x00},
465 {0x3309, 0x28},
466 {0x330a, 0x00},
467 {0x330b, 0x20},
468 {0x330c, 0x00},
469 {0x330d, 0x00},
470 {0x330e, 0x00},
471 {0x330f, 0x40},
472 {0x3307, 0x04},
473 {0x3500, 0x00}, /* exposure H */
474 {0x3501, 0x4d}, /* exposure M */
475 {0x3502, 0x40}, /* exposure L */
476 {0x3503, 0x80}, /* gain delay ?, exposure delay 1 frame, real gain */
477 {0x3505, 0x80}, /* gain option */
478 {0x3508, 0x02}, /* gain H */
479 {0x3509, 0x00}, /* gain L */
480 {0x350c, 0x00}, /* short gain H */
481 {0x350d, 0x80}, /* short gain L */
482 {0x3510, 0x00}, /* short exposure H */
483 {0x3511, 0x02}, /* short exposure M */
484 {0x3512, 0x00}, /* short exposure L */
485 {0x3700, 0x18},
486 {0x3701, 0x0c},
487 {0x3702, 0x28},
488 {0x3703, 0x19},
489 {0x3704, 0x14},
490 {0x3705, 0x00},
491 {0x3706, 0x82},
492 {0x3707, 0x04},
493 {0x3708, 0x24},
494 {0x3709, 0x33},
495 {0x370a, 0x01},
496 {0x370b, 0x82},
497 {0x370c, 0x04},
498 {0x3718, 0x12},
499 {0x3719, 0x31},
500 {0x3712, 0x42},
501 {0x3714, 0x24},
502 {0x371e, 0x19},
503 {0x371f, 0x40},
504 {0x3720, 0x05},
505 {0x3721, 0x05},
506 {0x3724, 0x06},
507 {0x3725, 0x01},
508 {0x3726, 0x06},
509 {0x3728, 0x05},
510 {0x3729, 0x02},
511 {0x372a, 0x03},
512 {0x372b, 0x53},
513 {0x372c, 0xa3},
514 {0x372d, 0x53},
515 {0x372e, 0x06},
516 {0x372f, 0x10},
517 {0x3730, 0x01},
518 {0x3731, 0x06},
519 {0x3732, 0x14},
520 {0x3733, 0x10},
521 {0x3734, 0x40},
522 {0x3736, 0x20},
523 {0x373a, 0x05},
524 {0x373b, 0x06},
525 {0x373c, 0x0a},
526 {0x373e, 0x03},
527 {0x3750, 0x0a},
528 {0x3751, 0x0e},
529 {0x3755, 0x10},
530 {0x3758, 0x00},
531 {0x3759, 0x4c},
532 {0x375a, 0x06},
533 {0x375b, 0x13},
534 {0x375c, 0x20},
535 {0x375d, 0x02},
536 {0x375e, 0x00},
537 {0x375f, 0x14},
538 {0x3768, 0x22},
539 {0x3769, 0x44},
540 {0x376a, 0x44},
541 {0x3761, 0x00},
542 {0x3762, 0x00},
543 {0x3763, 0x00},
544 {0x3766, 0xff},
545 {0x376b, 0x00},
546 {0x3772, 0x23},
547 {0x3773, 0x02},
548 {0x3774, 0x16},
549 {0x3775, 0x12},
550 {0x3776, 0x04},
551 {0x3777, 0x00},
552 {0x3778, 0x17},
553 {0x37a0, 0x44},
554 {0x37a1, 0x3d},
555 {0x37a2, 0x3d},
556 {0x37a3, 0x00},
557 {0x37a4, 0x00},
558 {0x37a5, 0x00},
559 {0x37a6, 0x00},
560 {0x37a7, 0x44},
561 {0x37a8, 0x4c},
562 {0x37a9, 0x4c},
563 {0x3760, 0x00},
564 {0x376f, 0x01},
565 {0x37aa, 0x44},
566 {0x37ab, 0x2e},
567 {0x37ac, 0x2e},
568 {0x37ad, 0x33},
569 {0x37ae, 0x0d},
570 {0x37af, 0x0d},
571 {0x37b0, 0x00},
572 {0x37b1, 0x00},
573 {0x37b2, 0x00},
574 {0x37b3, 0x42},
575 {0x37b4, 0x42},
576 {0x37b5, 0x31},
577 {0x37b6, 0x00},
578 {0x37b7, 0x00},
579 {0x37b8, 0x00},
580 {0x37b9, 0xff},
581 {0x3800, 0x00}, /* x start H */
582 {0x3801, 0x0c}, /* x start L */
583 {0x3802, 0x00}, /* y start H */
584 {0x3803, 0x0c}, /* y start L */
585 {0x3804, 0x0c}, /* x end H */
586 {0x3805, 0xd3}, /* x end L */
587 {0x3806, 0x09}, /* y end H */
588 {0x3807, 0xa3}, /* y end L */
589 {0x3808, 0x06}, /* x output size H */
590 {0x3809, 0x60}, /* x output size L */
591 {0x380a, 0x04}, /* y output size H */
592 {0x380b, 0xc8}, /* y output size L */
593 {0x380c, 0x07}, /* HTS H */
594 {0x380d, 0x88}, /* HTS L */
595 {0x380e, 0x04}, /* VTS H */
596 {0x380f, 0xdc}, /* VTS L */
597 {0x3810, 0x00}, /* ISP x win H */
598 {0x3811, 0x04}, /* ISP x win L */
599 {0x3813, 0x02}, /* ISP y win L */
600 {0x3814, 0x03}, /* x odd inc */
601 {0x3815, 0x01}, /* x even inc */
602 {0x3820, 0x00}, /* vflip off */
603 {0x3821, 0x67}, /* mirror on, bin on */
604 {0x382a, 0x03}, /* y odd inc */
605 {0x382b, 0x01}, /* y even inc */
606 {0x3830, 0x08},
607 {0x3836, 0x02},
608 {0x3837, 0x18},
609 {0x3841, 0xff}, /* window auto size enable */
610 {0x3846, 0x48},
611 {0x3d85, 0x16}, /* OTP power up load data enable with BIST */
612 {0x3d8c, 0x73}, /* OTP setting start High */
613 {0x3d8d, 0xde}, /* OTP setting start Low */
614 {0x3f08, 0x08},
615 {0x3f0a, 0x00},
616 {0x4000, 0xf1}, /* out_range_trig, format_chg_trig */
617 {0x4001, 0x10}, /* total 128 black column */
618 {0x4005, 0x10}, /* BLC target L */
619 {0x4002, 0x27}, /* value used to limit BLC offset */
620 {0x4009, 0x81}, /* final BLC offset limitation enable */
621 {0x400b, 0x0c}, /* DCBLC on, DCBLC manual mode on */
622 {0x401b, 0x00}, /* zero line R coefficient */
623 {0x401d, 0x00}, /* zoro line T coefficient */
624 {0x4020, 0x00}, /* Anchor left start H */
625 {0x4021, 0x04}, /* Anchor left start L */
626 {0x4022, 0x06}, /* Anchor left end H */
627 {0x4023, 0x00}, /* Anchor left end L */
628 {0x4024, 0x0f}, /* Anchor right start H */
629 {0x4025, 0x2a}, /* Anchor right start L */
630 {0x4026, 0x0f}, /* Anchor right end H */
631 {0x4027, 0x2b}, /* Anchor right end L */
632 {0x4028, 0x00}, /* top zero line start */
633 {0x4029, 0x02}, /* top zero line number */
634 {0x402a, 0x04}, /* top black line start */
635 {0x402b, 0x04}, /* top black line number */
636 {0x402c, 0x00}, /* bottom zero line start */
637 {0x402d, 0x02}, /* bottom zoro line number */
638 {0x402e, 0x04}, /* bottom black line start */
639 {0x402f, 0x04}, /* bottom black line number */
640 {0x401f, 0x00}, /* interpolation x/y disable, Anchor one disable */
641 {0x4034, 0x3f},
642 {0x403d, 0x04}, /* md_precision_en */
643 {0x4300, 0xff}, /* clip max H */
644 {0x4301, 0x00}, /* clip min H */
645 {0x4302, 0x0f}, /* clip min L, clip max L */
646 {0x4316, 0x00},
647 {0x4500, 0x58},
648 {0x4503, 0x18},
649 {0x4600, 0x00},
650 {0x4601, 0xcb},
651 {0x481f, 0x32}, /* clk prepare min */
652 {0x4837, 0x16}, /* global timing */
653 {0x4850, 0x10}, /* lane 1 = 1, lane 0 = 0 */
654 {0x4851, 0x32}, /* lane 3 = 3, lane 2 = 2 */
655 {0x4b00, 0x2a},
656 {0x4b0d, 0x00},
657 {0x4d00, 0x04}, /* temperature sensor */
658 {0x4d01, 0x18},
659 {0x4d02, 0xc3},
660 {0x4d03, 0xff},
661 {0x4d04, 0xff},
662 {0x4d05, 0xff}, /* temperature sensor */
663 {0x5000, 0xfe}, /* lenc on, slave/master AWB gain/statistics enable */
664 {0x5001, 0x01}, /* BLC on */
665 {0x5002, 0x08}, /* H scale off, WBMATCH off, OTP_DPC */
666 {0x5003, 0x20}, /* DPC_DBC buffer control enable, WB */
667 {0x501e, 0x93}, /* enable digital gain */
668 {0x5046, 0x12},
669 {0x5780, 0x3e}, /* DPC */
670 {0x5781, 0x0f},
671 {0x5782, 0x44},
672 {0x5783, 0x02},
673 {0x5784, 0x01},
674 {0x5785, 0x00},
675 {0x5786, 0x00},
676 {0x5787, 0x04},
677 {0x5788, 0x02},
678 {0x5789, 0x0f},
679 {0x578a, 0xfd},
680 {0x578b, 0xf5},
681 {0x578c, 0xf5},
682 {0x578d, 0x03},
683 {0x578e, 0x08},
684 {0x578f, 0x0c},
685 {0x5790, 0x08},
686 {0x5791, 0x04},
687 {0x5792, 0x00},
688 {0x5793, 0x52},
689 {0x5794, 0xa3}, /* DPC */
690 {0x5871, 0x0d}, /* Lenc */
691 {0x5870, 0x18},
692 {0x586e, 0x10},
693 {0x586f, 0x08},
694 {0x58f7, 0x01},
695 {0x58f8, 0x3d}, /* Lenc */
696 {0x5901, 0x00}, /* H skip off, V skip off */
697 {0x5b00, 0x02}, /* OTP DPC start address */
698 {0x5b01, 0x10}, /* OTP DPC start address */
699 {0x5b02, 0x03}, /* OTP DPC end address */
700 {0x5b03, 0xcf}, /* OTP DPC end address */
701 {0x5b05, 0x6c}, /* recover method = 2b11, */
702 {0x5e00, 0x00}, /* use 0x3ff to test pattern off */
703 {0x5e01, 0x41}, /* window cut enable */
704 {0x382d, 0x7f},
705 {0x4825, 0x3a}, /* lpx_p_min */
706 {0x4826, 0x40}, /* hs_prepare_min */
707 {0x4808, 0x25}, /* wake up delay in 1/1024 s */
708 {0x3763, 0x18},
709 {0x3768, 0xcc},
710 {0x470b, 0x28},
711 {0x4202, 0x00},
712 {0x400d, 0x10}, /* BLC offset trigger L */
713 {0x4040, 0x04}, /* BLC gain th2 */
714 {0x403e, 0x04}, /* BLC gain th1 */
715 {0x4041, 0xc6}, /* BLC */
716 {0x3007, 0x80},
717 {0x400a, 0x01},
718 {REG_NULL, 0x00},
730 * AM19 : 3617 <- 0xC0
731 * AM20 : change FWC_6K_EN to be default 0x3618=0x5a
733 {0x0100, 0x00},
734 {0x3501, 0x4d}, /* exposure M */
735 {0x3502, 0x40}, /* exposure L */
736 {0x3778, 0x17},
737 {0x3808, 0x06}, /* x output size H */
738 {0x3809, 0x60}, /* x output size L */
739 {0x380a, 0x04}, /* y output size H */
740 {0x380b, 0xc8}, /* y output size L */
741 {0x380c, 0x07}, /* HTS H */
742 {0x380d, 0x88}, /* HTS L */
743 {0x380e, 0x04}, /* VTS H */
744 {0x380f, 0xdc}, /* VTS L */
745 {0x3814, 0x03}, /* x odd inc */
746 {0x3821, 0x67}, /* mirror on, bin on */
747 {0x382a, 0x03}, /* y odd inc */
748 {0x3830, 0x08},
749 {0x3836, 0x02},
750 {0x3f0a, 0x00},
751 {0x4001, 0x10}, /* total 128 black column */
752 {0x4022, 0x06}, /* Anchor left end H */
753 {0x4023, 0x00}, /* Anchor left end L */
754 {0x4025, 0x2a}, /* Anchor right start L */
755 {0x4027, 0x2b}, /* Anchor right end L */
756 {0x402b, 0x04}, /* top black line number */
757 {0x402f, 0x04}, /* bottom black line number */
758 {0x4500, 0x58},
759 {0x4600, 0x00},
760 {0x4601, 0xcb},
761 {0x382d, 0x7f},
762 {0x0100, 0x01},
763 {REG_NULL, 0x00},
772 {0x0100, 0x00},
773 {0x3501, 0x9a}, /* exposure M */
774 {0x3502, 0x20}, /* exposure L */
775 {0x3778, 0x1a},
776 {0x3808, 0x0c}, /* x output size H */
777 {0x3809, 0xc0}, /* x output size L */
778 {0x380a, 0x09}, /* y output size H */
779 {0x380b, 0x90}, /* y output size L */
780 {0x380c, 0x07}, /* HTS H */
781 {0x380d, 0x94}, /* HTS L */
782 {0x380e, 0x09}, /* VTS H */
783 {0x380f, 0xaa}, /* VTS L */
784 {0x3814, 0x01}, /* x odd inc */
785 {0x3821, 0x46}, /* mirror on, bin off */
786 {0x382a, 0x01}, /* y odd inc */
787 {0x3830, 0x06},
788 {0x3836, 0x01},
789 {0x3f0a, 0x00},
790 {0x4001, 0x00}, /* total 256 black column */
791 {0x4022, 0x0c}, /* Anchor left end H */
792 {0x4023, 0x60}, /* Anchor left end L */
793 {0x4025, 0x36}, /* Anchor right start L */
794 {0x4027, 0x37}, /* Anchor right end L */
795 {0x402b, 0x08}, /* top black line number */
796 {0x402f, 0x08}, /* bottom black line number */
797 {0x4500, 0x58},
798 {0x4600, 0x01},
799 {0x4601, 0x97},
800 {0x382d, 0xff},
801 {REG_NULL, 0x00},
808 * AM19 : 3617 <- 0xC0
809 * AM20 : change FWC_6K_EN to be default 0x3618=0x5a
811 {0x0103, 0x01}, /* software reset for OVTATool only */
812 {0x0103, 0x01}, /* software reset */
813 {0x0100, 0x00}, /* software standby */
814 {0x0302, 0x1e}, /* pll1_multi */
815 {0x0303, 0x00}, /* pll1_divm */
816 {0x0304, 0x03}, /* pll1_div_mipi */
817 {0x030e, 0x00}, /* pll2_rdiv */
818 {0x030f, 0x04}, /* pll2_divsp */
819 {0x0312, 0x01}, /* pll2_pre_div0, pll2_r_divdac */
820 {0x031e, 0x0c}, /* pll1_no_lat */
821 {0x3600, 0x00},
822 {0x3601, 0x00},
823 {0x3602, 0x00},
824 {0x3603, 0x00},
825 {0x3604, 0x22},
826 {0x3605, 0x20},
827 {0x3606, 0x00},
828 {0x3607, 0x20},
829 {0x3608, 0x11},
830 {0x3609, 0x28},
831 {0x360a, 0x00},
832 {0x360b, 0x05},
833 {0x360c, 0xd4},
834 {0x360d, 0x40},
835 {0x360e, 0x0c},
836 {0x360f, 0x20},
837 {0x3610, 0x07},
838 {0x3611, 0x20},
839 {0x3612, 0x88},
840 {0x3613, 0x80},
841 {0x3614, 0x58},
842 {0x3615, 0x00},
843 {0x3616, 0x4a},
844 {0x3617, 0x90},
845 {0x3618, 0x5a},
846 {0x3619, 0x70},
847 {0x361a, 0x99},
848 {0x361b, 0x0a},
849 {0x361c, 0x07},
850 {0x361d, 0x00},
851 {0x361e, 0x00},
852 {0x361f, 0x00},
853 {0x3638, 0xff},
854 {0x3633, 0x0f},
855 {0x3634, 0x0f},
856 {0x3635, 0x0f},
857 {0x3636, 0x12},
858 {0x3645, 0x13},
859 {0x3646, 0x83},
860 {0x364a, 0x07},
861 {0x3015, 0x01},
862 {0x3018, 0x72}, /* MIPI 4 lane */
863 {0x3020, 0x93}, /* Clock switch output normal, pclk_div =/1 */
864 {0x3022, 0x01}, /* pd_mipi enable when rst_sync */
865 {0x3031, 0x0a}, /* MIPI 10-bit mode */
866 {0x3034, 0x00},
867 {0x3106, 0x01}, /* sclk_div, sclk_pre_div */
868 {0x3305, 0xf1},
869 {0x3308, 0x00},
870 {0x3309, 0x28},
871 {0x330a, 0x00},
872 {0x330b, 0x20},
873 {0x330c, 0x00},
874 {0x330d, 0x00},
875 {0x330e, 0x00},
876 {0x330f, 0x40},
877 {0x3307, 0x04},
878 {0x3500, 0x00}, /* exposure H */
879 {0x3501, 0x4d}, /* exposure M */
880 {0x3502, 0x40}, /* exposure L */
881 {0x3503, 0x80}, /* gain delay ?, exposure delay 1 frame, real gain */
882 {0x3505, 0x80}, /* gain option */
883 {0x3508, 0x02}, /* gain H */
884 {0x3509, 0x00}, /* gain L */
885 {0x350c, 0x00}, /* short gain H */
886 {0x350d, 0x80}, /* short gain L */
887 {0x3510, 0x00}, /* short exposure H */
888 {0x3511, 0x02}, /* short exposure M */
889 {0x3512, 0x00}, /* short exposure L */
890 {0x3700, 0x30},
891 {0x3701, 0x18},
892 {0x3702, 0x50},
893 {0x3703, 0x32},
894 {0x3704, 0x28},
895 {0x3705, 0x00},
896 {0x3706, 0x82},
897 {0x3707, 0x08},
898 {0x3708, 0x48},
899 {0x3709, 0x66},
900 {0x370a, 0x01},
901 {0x370b, 0x82},
902 {0x370c, 0x07},
903 {0x3718, 0x14},
904 {0x3719, 0x31},
905 {0x3712, 0x44},
906 {0x3714, 0x24},
907 {0x371e, 0x31},
908 {0x371f, 0x7f},
909 {0x3720, 0x0a},
910 {0x3721, 0x0a},
911 {0x3724, 0x0c},
912 {0x3725, 0x02},
913 {0x3726, 0x0c},
914 {0x3728, 0x0a},
915 {0x3729, 0x03},
916 {0x372a, 0x06},
917 {0x372b, 0xa6},
918 {0x372c, 0xa6},
919 {0x372d, 0xa6},
920 {0x372e, 0x0c},
921 {0x372f, 0x20},
922 {0x3730, 0x02},
923 {0x3731, 0x0c},
924 {0x3732, 0x28},
925 {0x3733, 0x10},
926 {0x3734, 0x40},
927 {0x3736, 0x30},
928 {0x373a, 0x0a},
929 {0x373b, 0x0b},
930 {0x373c, 0x14},
931 {0x373e, 0x06},
932 {0x3750, 0x0a},
933 {0x3751, 0x0e},
934 {0x3755, 0x10},
935 {0x3758, 0x00},
936 {0x3759, 0x4c},
937 {0x375a, 0x0c},
938 {0x375b, 0x26},
939 {0x375c, 0x20},
940 {0x375d, 0x04},
941 {0x375e, 0x00},
942 {0x375f, 0x28},
943 {0x3768, 0x22},
944 {0x3769, 0x44},
945 {0x376a, 0x44},
946 {0x3761, 0x00},
947 {0x3762, 0x00},
948 {0x3763, 0x00},
949 {0x3766, 0xff},
950 {0x376b, 0x00},
951 {0x3772, 0x46},
952 {0x3773, 0x04},
953 {0x3774, 0x2c},
954 {0x3775, 0x13},
955 {0x3776, 0x08},
956 {0x3777, 0x00},
957 {0x3778, 0x17},
958 {0x37a0, 0x88},
959 {0x37a1, 0x7a},
960 {0x37a2, 0x7a},
961 {0x37a3, 0x00},
962 {0x37a4, 0x00},
963 {0x37a5, 0x00},
964 {0x37a6, 0x00},
965 {0x37a7, 0x88},
966 {0x37a8, 0x98},
967 {0x37a9, 0x98},
968 {0x3760, 0x00},
969 {0x376f, 0x01},
970 {0x37aa, 0x88},
971 {0x37ab, 0x5c},
972 {0x37ac, 0x5c},
973 {0x37ad, 0x55},
974 {0x37ae, 0x19},
975 {0x37af, 0x19},
976 {0x37b0, 0x00},
977 {0x37b1, 0x00},
978 {0x37b2, 0x00},
979 {0x37b3, 0x84},
980 {0x37b4, 0x84},
981 {0x37b5, 0x60},
982 {0x37b6, 0x00},
983 {0x37b7, 0x00},
984 {0x37b8, 0x00},
985 {0x37b9, 0xff},
986 {0x3800, 0x00}, /* x start H */
987 {0x3801, 0x0c}, /* x start L */
988 {0x3802, 0x00}, /* y start H */
989 {0x3803, 0x0c}, /* y start L */
990 {0x3804, 0x0c}, /* x end H */
991 {0x3805, 0xd3}, /* x end L */
992 {0x3806, 0x09}, /* y end H */
993 {0x3807, 0xa3}, /* y end L */
994 {0x3808, 0x06}, /* x output size H */
995 {0x3809, 0x60}, /* x output size L */
996 {0x380a, 0x04}, /* y output size H */
997 {0x380b, 0xc8}, /* y output size L */
998 {0x380c, 0x07}, /* HTS H */
999 {0x380d, 0x88}, /* HTS L */
1000 {0x380e, 0x04}, /* VTS H */
1001 {0x380f, 0xdc}, /* VTS L */
1002 {0x3810, 0x00}, /* ISP x win H */
1003 {0x3811, 0x04}, /* ISP x win L */
1004 {0x3813, 0x02}, /* ISP y win L */
1005 {0x3814, 0x03}, /* x odd inc */
1006 {0x3815, 0x01}, /* x even inc */
1007 {0x3820, 0x00}, /* vflip off */
1008 {0x3821, 0x67}, /* mirror on, bin o */
1009 {0x382a, 0x03}, /* y odd inc */
1010 {0x382b, 0x01}, /* y even inc */
1011 {0x3830, 0x08},
1012 {0x3836, 0x02},
1013 {0x3837, 0x18},
1014 {0x3841, 0xff}, /* window auto size enable */
1015 {0x3846, 0x48},
1016 {0x3d85, 0x16}, /* OTP power up load data/setting enable */
1017 {0x3d8c, 0x73}, /* OTP setting start High */
1018 {0x3d8d, 0xde}, /* OTP setting start Low */
1019 {0x3f08, 0x10},
1020 {0x3f0a, 0x00},
1021 {0x4000, 0xf1}, /* out_range/format_chg/gain/exp_chg trig enable */
1022 {0x4001, 0x10}, /* total 128 black column */
1023 {0x4005, 0x10}, /* BLC target L */
1024 {0x4002, 0x27}, /* value used to limit BLC offset */
1025 {0x4009, 0x81}, /* final BLC offset limitation enable */
1026 {0x400b, 0x0c}, /* DCBLC on, DCBLC manual mode on */
1027 {0x401b, 0x00}, /* zero line R coefficient */
1028 {0x401d, 0x00}, /* zoro line T coefficient */
1029 {0x4020, 0x00}, /* Anchor left start H */
1030 {0x4021, 0x04}, /* Anchor left start L */
1031 {0x4022, 0x06}, /* Anchor left end H */
1032 {0x4023, 0x00}, /* Anchor left end L */
1033 {0x4024, 0x0f}, /* Anchor right start H */
1034 {0x4025, 0x2a}, /* Anchor right start L */
1035 {0x4026, 0x0f}, /* Anchor right end H */
1036 {0x4027, 0x2b}, /* Anchor right end L */
1037 {0x4028, 0x00}, /* top zero line start */
1038 {0x4029, 0x02}, /* top zero line number */
1039 {0x402a, 0x04}, /* top black line start */
1040 {0x402b, 0x04}, /* top black line number */
1041 {0x402c, 0x00}, /* bottom zero line start */
1042 {0x402d, 0x02}, /* bottom zoro line number */
1043 {0x402e, 0x04}, /* bottom black line start */
1044 {0x402f, 0x04}, /* bottom black line number */
1045 {0x401f, 0x00}, /* interpolation x/y disable, Anchor one disable */
1046 {0x4034, 0x3f},
1047 {0x403d, 0x04}, /* md_precision_en */
1048 {0x4300, 0xff}, /* clip max H */
1049 {0x4301, 0x00}, /* clip min H */
1050 {0x4302, 0x0f}, /* clip min L, clip max L */
1051 {0x4316, 0x00},
1052 {0x4500, 0x58},
1053 {0x4503, 0x18},
1054 {0x4600, 0x00},
1055 {0x4601, 0xcb},
1056 {0x481f, 0x32}, /* clk prepare min */
1057 {0x4837, 0x16}, /* global timing */
1058 {0x4850, 0x10}, /* lane 1 = 1, lane 0 = 0 */
1059 {0x4851, 0x32}, /* lane 3 = 3, lane 2 = 2 */
1060 {0x4b00, 0x2a},
1061 {0x4b0d, 0x00},
1062 {0x4d00, 0x04}, /* temperature sensor */
1063 {0x4d01, 0x18},
1064 {0x4d02, 0xc3},
1065 {0x4d03, 0xff},
1066 {0x4d04, 0xff},
1067 {0x4d05, 0xff}, /* temperature sensor */
1068 {0x5000, 0xfe}, /* lenc on, slave/master AWB gain/statistics enable */
1069 {0x5001, 0x01}, /* BLC on */
1070 {0x5002, 0x08}, /* WBMATCH sensor's gain, H scale/WBMATCH/OTP_DPC off */
1071 {0x5003, 0x20}, /* DPC_DBC buffer control enable, WB */
1072 {0x501e, 0x93}, /* enable digital gain */
1073 {0x5046, 0x12},
1074 {0x5780, 0x3e}, /* DPC */
1075 {0x5781, 0x0f},
1076 {0x5782, 0x44},
1077 {0x5783, 0x02},
1078 {0x5784, 0x01},
1079 {0x5785, 0x00},
1080 {0x5786, 0x00},
1081 {0x5787, 0x04},
1082 {0x5788, 0x02},
1083 {0x5789, 0x0f},
1084 {0x578a, 0xfd},
1085 {0x578b, 0xf5},
1086 {0x578c, 0xf5},
1087 {0x578d, 0x03},
1088 {0x578e, 0x08},
1089 {0x578f, 0x0c},
1090 {0x5790, 0x08},
1091 {0x5791, 0x04},
1092 {0x5792, 0x00},
1093 {0x5793, 0x52},
1094 {0x5794, 0xa3}, /* DPC */
1095 {0x5871, 0x0d}, /* Lenc */
1096 {0x5870, 0x18},
1097 {0x586e, 0x10},
1098 {0x586f, 0x08},
1099 {0x58f7, 0x01},
1100 {0x58f8, 0x3d}, /* Lenc */
1101 {0x5901, 0x00}, /* H skip off, V skip off */
1102 {0x5b00, 0x02}, /* OTP DPC start address */
1103 {0x5b01, 0x10}, /* OTP DPC start address */
1104 {0x5b02, 0x03}, /* OTP DPC end address */
1105 {0x5b03, 0xcf}, /* OTP DPC end address */
1106 {0x5b05, 0x6c}, /* recover method = 2b11 */
1107 {0x5e00, 0x00}, /* use 0x3ff to test pattern off */
1108 {0x5e01, 0x41}, /* window cut enable */
1109 {0x382d, 0x7f},
1110 {0x4825, 0x3a}, /* lpx_p_min */
1111 {0x4826, 0x40}, /* hs_prepare_min */
1112 {0x4808, 0x25}, /* wake up delay in 1/1024 s */
1113 {0x3763, 0x18},
1114 {0x3768, 0xcc},
1115 {0x470b, 0x28},
1116 {0x4202, 0x00},
1117 {0x400d, 0x10}, /* BLC offset trigger L */
1118 {0x4040, 0x04}, /* BLC gain th2 */
1119 {0x403e, 0x04}, /* BLC gain th1 */
1120 {0x4041, 0xc6}, /* BLC */
1121 {0x3007, 0x80},
1122 {0x400a, 0x01},
1123 {REG_NULL, 0x00},
1132 {0x0100, 0x00},
1133 {0x3501, 0x4d}, /* exposure M */
1134 {0x3502, 0x40}, /* exposure L */
1135 {0x3808, 0x06}, /* x output size H */
1136 {0x3809, 0x60}, /* x output size L */
1137 {0x380a, 0x04}, /* y output size H */
1138 {0x380b, 0xc8}, /* y output size L */
1139 {0x380c, 0x07}, /* HTS H */
1140 {0x380d, 0x88}, /* HTS L */
1141 {0x380e, 0x04}, /* VTS H */
1142 {0x380f, 0xdc}, /* VTS L */
1143 {0x3814, 0x03}, /* x odd inc */
1144 {0x3821, 0x67}, /* mirror on, bin on */
1145 {0x382a, 0x03}, /* y odd inc */
1146 {0x3830, 0x08},
1147 {0x3836, 0x02},
1148 {0x3f0a, 0x00},
1149 {0x4001, 0x10}, /* total 128 black column */
1150 {0x4022, 0x06}, /* Anchor left end H */
1151 {0x4023, 0x00}, /* Anchor left end L */
1152 {0x4025, 0x2a}, /* Anchor right start L */
1153 {0x4027, 0x2b}, /* Anchor right end L */
1154 {0x402b, 0x04}, /* top black line number */
1155 {0x402f, 0x04}, /* bottom black line number */
1156 {0x4500, 0x58},
1157 {0x4600, 0x00},
1158 {0x4601, 0xcb},
1159 {0x382d, 0x7f},
1160 {0x0100, 0x01},
1161 {REG_NULL, 0x00},
1170 {0x0100, 0x00},
1171 {0x3501, 0x9a}, /* exposure M */
1172 {0x3502, 0x20}, /* exposure L */
1173 {0x3808, 0x0c}, /* x output size H */
1174 {0x3809, 0xc0}, /* x output size L */
1175 {0x380a, 0x09}, /* y output size H */
1176 {0x380b, 0x90}, /* y output size L */
1177 {0x380c, 0x07}, /* HTS H */
1178 {0x380d, 0x94}, /* HTS L */
1179 {0x380e, 0x09}, /* VTS H */
1180 {0x380f, 0xaa}, /* VTS L */
1181 {0x3814, 0x01}, /* x odd inc */
1182 {0x3821, 0x46}, /* mirror on, bin off */
1183 {0x382a, 0x01}, /* y odd inc */
1184 {0x3830, 0x06},
1185 {0x3836, 0x01},
1186 {0x3f0a, 0x00},
1187 {0x4001, 0x00}, /* total 256 black column */
1188 {0x4022, 0x0c}, /* Anchor left end H */
1189 {0x4023, 0x60}, /* Anchor left end L */
1190 {0x4025, 0x36}, /* Anchor right start L */
1191 {0x4027, 0x37}, /* Anchor right end L */
1192 {0x402b, 0x08}, /* top black line number */
1193 {0x402f, 0x08}, /* interpolation x/y disable, Anchor one disable */
1194 {0x4500, 0x58},
1195 {0x4600, 0x01},
1196 {0x4601, 0x97},
1197 {0x382d, 0xff},
1198 {REG_NULL, 0x00},
1258 ret = ret < 0 ? ret : -EIO; in ov8858_write()
1267 return 0; in ov8858_write()
1273 int ret = 0; in ov8858_write_array()
1275 for (i = 0; ret == 0 && regs[i].addr != REG_NULL; ++i) { in ov8858_write_array()
1289 __be32 data_be = 0; in ov8858_read()
1296 msgs[0].addr = client->addr; in ov8858_read()
1297 msgs[0].flags = 0; in ov8858_read()
1298 msgs[0].len = 2; in ov8858_read()
1299 msgs[0].buf = (u8 *)®_addr_be; in ov8858_read()
1309 ret = ret < 0 ? ret : -EIO; in ov8858_read()
1317 return 0; in ov8858_read()
1336 format = v4l2_subdev_state_get_format(state, 0); in ov8858_start_stream()
1364 return 0; in ov8858_start_stream()
1378 int ret = 0; in ov8858_s_stream()
1384 if (ret < 0) in ov8858_s_stream()
1431 *v4l2_subdev_state_get_format(state, 0) = fmt->format; in ov8858_set_fmt()
1434 return 0; in ov8858_set_fmt()
1446 return 0; in ov8858_set_fmt()
1464 return 0; in ov8858_enum_frame_sizes()
1471 if (code->index != 0) in ov8858_enum_mbus_code()
1476 return 0; in ov8858_enum_mbus_code()
1482 const struct ov8858_mode *def_mode = &ov8858_modes[0]; in ov8858_init_state()
1493 return 0; in ov8858_init_state()
1553 format = v4l2_subdev_state_get_format(state, 0); in ov8858_set_ctrl()
1568 return 0; in ov8858_set_ctrl()
1583 * 0x350a[7:0] = dgain[13:6] in ov8858_set_ctrl()
1584 * 0x350b[5:0] = dgain[5:0] in ov8858_set_ctrl()
1602 dev_warn(&client->dev, "%s Unhandled id: 0x%x\n", in ov8858_set_ctrl()
1631 if (ret < 0) { in ov8858_power_on()
1638 if (ret < 0) { in ov8858_power_on()
1650 gpiod_set_value_cansleep(ov8858->reset_gpio, 0); in ov8858_power_on()
1652 gpiod_set_value_cansleep(ov8858->pwdn_gpio, 0); in ov8858_power_on()
1655 return 0; in ov8858_power_on()
1690 return 0; in ov8858_runtime_suspend()
1706 const struct ov8858_mode *mode = &ov8858_modes[0]; in ov8858_init_ctrls()
1719 0, 0, link_freq_menu_items); in ov8858_init_ctrls()
1726 0, pixel_rate, 1, pixel_rate); in ov8858_init_ctrls()
1759 0, 0, ov8858_test_pattern_menu); in ov8858_init_ctrls()
1777 return 0; in ov8858_init_ctrls()
1789 u32 id = 0; in ov8858_check_sensor_id()
1797 dev_err(&client->dev, "Unexpected sensor id 0x%x\n", id); in ov8858_check_sensor_id()
1805 dev_info(&client->dev, "Detected OV8858 sensor, revision 0x%x\n", id); in ov8858_check_sensor_id()
1825 return 0; in ov8858_check_sensor_id()
1833 for (i = 0; i < ARRAY_SIZE(ov8858_supply_names); i++) in ov8858_configure_regulators()
1873 return 0; in ov8858_parse_of()
1924 if (ret < 0) in ov8858_probe()
1929 if (ret < 0) { in ov8858_probe()
1958 return 0; in ov8858_probe()