Lines Matching refs:ov64a40
2832 struct ov64a40 { struct
2859 static inline struct ov64a40 *sd_to_ov64a40(struct v4l2_subdev *sd) in sd_to_ov64a40() argument
2861 return container_of_const(sd, struct ov64a40, sd); in sd_to_ov64a40()
2865 ov64a40_get_timings(struct ov64a40 *ov64a40, unsigned int link_freq_index) in ov64a40_get_timings() argument
2867 s64 link_freq = ov64a40->link_frequencies[link_freq_index]; in ov64a40_get_timings()
2872 return &ov64a40->mode->timings_default[timings_index]; in ov64a40_get_timings()
2875 static int ov64a40_program_geometry(struct ov64a40 *ov64a40) in ov64a40_program_geometry() argument
2877 struct ov64a40_mode *mode = ov64a40->mode; in ov64a40_program_geometry()
2884 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL0, in ov64a40_program_geometry()
2886 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL2, in ov64a40_program_geometry()
2888 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL4, in ov64a40_program_geometry()
2890 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL6, in ov64a40_program_geometry()
2894 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL10, in ov64a40_program_geometry()
2896 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL12, in ov64a40_program_geometry()
2898 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL8, in ov64a40_program_geometry()
2900 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLA, in ov64a40_program_geometry()
2904 timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val); in ov64a40_program_geometry()
2905 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLC, timings->ppl, &ret); in ov64a40_program_geometry()
2906 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRLE, timings->vts, &ret); in ov64a40_program_geometry()
2911 static int ov64a40_program_subsampling(struct ov64a40 *ov64a40) in ov64a40_program_subsampling() argument
2913 struct ov64a40_subsampling *subsampling = &ov64a40->mode->subsampling; in ov64a40_program_subsampling()
2917 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL14, in ov64a40_program_subsampling()
2920 cci_write(ov64a40->cci, OV64A40_REG_TIMING_CTRL15, in ov64a40_program_subsampling()
2925 cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20, in ov64a40_program_subsampling()
2929 cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21, in ov64a40_program_subsampling()
2937 static int ov64a40_start_streaming(struct ov64a40 *ov64a40, in ov64a40_start_streaming() argument
2940 const struct ov64a40_reglist *reglist = &ov64a40->mode->reglist; in ov64a40_start_streaming()
2945 ret = pm_runtime_resume_and_get(ov64a40->dev); in ov64a40_start_streaming()
2949 ret = cci_multi_reg_write(ov64a40->cci, ov64a40_init, in ov64a40_start_streaming()
2954 ret = cci_multi_reg_write(ov64a40->cci, reglist->regvals, in ov64a40_start_streaming()
2959 ret = ov64a40_program_geometry(ov64a40); in ov64a40_start_streaming()
2963 ret = ov64a40_program_subsampling(ov64a40); in ov64a40_start_streaming()
2967 ret = __v4l2_ctrl_handler_setup(&ov64a40->ctrl_handler); in ov64a40_start_streaming()
2971 ret = cci_write(ov64a40->cci, OV64A40_REG_SMIA, in ov64a40_start_streaming()
2977 __v4l2_ctrl_grab(ov64a40->link_freq, true); in ov64a40_start_streaming()
2978 __v4l2_ctrl_grab(ov64a40->vflip, true); in ov64a40_start_streaming()
2979 __v4l2_ctrl_grab(ov64a40->hflip, true); in ov64a40_start_streaming()
2982 timings = ov64a40_get_timings(ov64a40, ov64a40->link_freq->cur.val); in ov64a40_start_streaming()
2987 delay += DIV_ROUND_UP(timings->ppl * 4 * ov64a40->exposure->cur.val, in ov64a40_start_streaming()
2994 pm_runtime_mark_last_busy(ov64a40->dev); in ov64a40_start_streaming()
2995 pm_runtime_put_autosuspend(ov64a40->dev); in ov64a40_start_streaming()
3000 static int ov64a40_stop_streaming(struct ov64a40 *ov64a40, in ov64a40_stop_streaming() argument
3003 cci_update_bits(ov64a40->cci, OV64A40_REG_SMIA, BIT(0), 0, NULL); in ov64a40_stop_streaming()
3004 pm_runtime_mark_last_busy(ov64a40->dev); in ov64a40_stop_streaming()
3005 pm_runtime_put_autosuspend(ov64a40->dev); in ov64a40_stop_streaming()
3007 __v4l2_ctrl_grab(ov64a40->link_freq, false); in ov64a40_stop_streaming()
3008 __v4l2_ctrl_grab(ov64a40->vflip, false); in ov64a40_stop_streaming()
3009 __v4l2_ctrl_grab(ov64a40->hflip, false); in ov64a40_stop_streaming()
3016 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); in ov64a40_set_stream() local
3022 ret = ov64a40_start_streaming(ov64a40, state); in ov64a40_set_stream()
3024 ret = ov64a40_stop_streaming(ov64a40, state); in ov64a40_set_stream()
3034 static u32 ov64a40_mbus_code(struct ov64a40 *ov64a40) in ov64a40_mbus_code() argument
3036 unsigned int index = ov64a40->hflip->val << 1 | ov64a40->vflip->val; in ov64a40_mbus_code()
3041 static void ov64a40_update_pad_fmt(struct ov64a40 *ov64a40, in ov64a40_update_pad_fmt() argument
3045 fmt->code = ov64a40_mbus_code(ov64a40); in ov64a40_update_pad_fmt()
3058 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); in ov64a40_init_state() local
3063 ov64a40_update_pad_fmt(ov64a40, &ov64a40_modes[0], format); in ov64a40_init_state()
3078 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); in ov64a40_enum_mbus_code() local
3083 code->code = ov64a40_mbus_code(ov64a40); in ov64a40_enum_mbus_code()
3092 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); in ov64a40_enum_frame_size() local
3099 code = ov64a40_mbus_code(ov64a40); in ov64a40_enum_frame_size()
3147 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); in ov64a40_set_format() local
3156 ov64a40_update_pad_fmt(ov64a40, mode, &fmt->format); in ov64a40_set_format()
3159 if (ov64a40->mode == mode && format->code == fmt->format.code) in ov64a40_set_format()
3168 ov64a40->mode = mode; in ov64a40_set_format()
3172 timings = ov64a40_get_timings(ov64a40, in ov64a40_set_format()
3173 ov64a40->link_freq->cur.val); in ov64a40_set_format()
3176 __v4l2_ctrl_modify_range(ov64a40->vblank, OV64A40_VBLANK_MIN, in ov64a40_set_format()
3178 __v4l2_ctrl_s_ctrl(ov64a40->vblank, vblank_def); in ov64a40_set_format()
3181 __v4l2_ctrl_modify_range(ov64a40->exposure, in ov64a40_set_format()
3186 __v4l2_ctrl_modify_range(ov64a40->hblank, in ov64a40_set_format()
3221 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); in ov64a40_power_on() local
3224 ret = clk_prepare_enable(ov64a40->xclk); in ov64a40_power_on()
3229 ov64a40->supplies); in ov64a40_power_on()
3231 clk_disable_unprepare(ov64a40->xclk); in ov64a40_power_on()
3236 gpiod_set_value_cansleep(ov64a40->reset_gpio, 0); in ov64a40_power_on()
3246 struct ov64a40 *ov64a40 = sd_to_ov64a40(sd); in ov64a40_power_off() local
3248 gpiod_set_value_cansleep(ov64a40->reset_gpio, 1); in ov64a40_power_off()
3250 ov64a40->supplies); in ov64a40_power_off()
3251 clk_disable_unprepare(ov64a40->xclk); in ov64a40_power_off()
3256 static int ov64a40_link_freq_config(struct ov64a40 *ov64a40, int link_freq_id) in ov64a40_link_freq_config() argument
3262 cci_multi_reg_write(ov64a40->cci, ov64a40_pll_config, in ov64a40_link_freq_config()
3266 link_frequency = ov64a40->link_frequencies[link_freq_id]; in ov64a40_link_freq_config()
3268 cci_write(ov64a40->cci, OV64A40_PLL1_MULTIPLIER, 0x0078, &ret); in ov64a40_link_freq_config()
3275 struct ov64a40 *ov64a40 = container_of(ctrl->handler, struct ov64a40, in ov64a40_set_ctrl() local
3281 int exp_max = ov64a40->mode->height + ctrl->val in ov64a40_set_ctrl()
3283 int exp_val = min(ov64a40->exposure->cur.val, exp_max); in ov64a40_set_ctrl()
3285 __v4l2_ctrl_modify_range(ov64a40->exposure, in ov64a40_set_ctrl()
3286 ov64a40->exposure->minimum, in ov64a40_set_ctrl()
3290 pm_status = pm_runtime_get_if_active(ov64a40->dev); in ov64a40_set_ctrl()
3296 ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_EXPO, in ov64a40_set_ctrl()
3300 ret = cci_write(ov64a40->cci, OV64A40_REG_MEC_LONG_GAIN, in ov64a40_set_ctrl()
3304 int vts = ctrl->val + ov64a40->mode->height; in ov64a40_set_ctrl()
3306 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_LOW, vts, &ret); in ov64a40_set_ctrl()
3307 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_MID, in ov64a40_set_ctrl()
3309 cci_write(ov64a40->cci, OV64A40_REG_TIMINGS_VTS_HIGH, in ov64a40_set_ctrl()
3314 ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_20, in ov64a40_set_ctrl()
3320 ret = cci_update_bits(ov64a40->cci, OV64A40_REG_TIMING_CTRL_21, in ov64a40_set_ctrl()
3327 ret = cci_write(ov64a40->cci, OV64A40_REG_TEST_PATTERN, in ov64a40_set_ctrl()
3331 ret = ov64a40_link_freq_config(ov64a40, ctrl->val); in ov64a40_set_ctrl()
3334 dev_err(ov64a40->dev, "Unhandled control: %#x\n", ctrl->id); in ov64a40_set_ctrl()
3340 pm_runtime_mark_last_busy(ov64a40->dev); in ov64a40_set_ctrl()
3341 pm_runtime_put_autosuspend(ov64a40->dev); in ov64a40_set_ctrl()
3351 static int ov64a40_init_controls(struct ov64a40 *ov64a40) in ov64a40_init_controls() argument
3354 struct v4l2_ctrl_handler *hdlr = &ov64a40->ctrl_handler; in ov64a40_init_controls()
3367 ov64a40->link_freq = in ov64a40_init_controls()
3370 ov64a40->num_link_frequencies - 1, in ov64a40_init_controls()
3371 0, ov64a40->link_frequencies); in ov64a40_init_controls()
3378 timings = ov64a40_get_timings(ov64a40, 0); in ov64a40_init_controls()
3380 ov64a40->exposure = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, in ov64a40_init_controls()
3385 hblank_val = timings->ppl * 4 - ov64a40->mode->width; in ov64a40_init_controls()
3386 ov64a40->hblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, in ov64a40_init_controls()
3389 if (ov64a40->hblank) in ov64a40_init_controls()
3390 ov64a40->hblank->flags |= V4L2_CTRL_FLAG_READ_ONLY; in ov64a40_init_controls()
3392 vblank_def = timings->vts - ov64a40->mode->height; in ov64a40_init_controls()
3393 vblank_max = OV64A40_VTS_MAX - ov64a40->mode->height; in ov64a40_init_controls()
3394 ov64a40->vblank = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, in ov64a40_init_controls()
3402 ov64a40->hflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, in ov64a40_init_controls()
3404 if (ov64a40->hflip) in ov64a40_init_controls()
3405 ov64a40->hflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; in ov64a40_init_controls()
3407 ov64a40->vflip = v4l2_ctrl_new_std(hdlr, &ov64a40_ctrl_ops, in ov64a40_init_controls()
3409 if (ov64a40->vflip) in ov64a40_init_controls()
3410 ov64a40->vflip->flags |= V4L2_CTRL_FLAG_MODIFY_LAYOUT; in ov64a40_init_controls()
3414 dev_err(ov64a40->dev, "control init failed: %d\n", ret); in ov64a40_init_controls()
3418 ret = v4l2_fwnode_device_parse(ov64a40->dev, &props); in ov64a40_init_controls()
3427 ov64a40->sd.ctrl_handler = hdlr; in ov64a40_init_controls()
3436 static int ov64a40_identify(struct ov64a40 *ov64a40) in ov64a40_identify() argument
3441 ret = cci_read(ov64a40->cci, OV64A40_REG_CHIP_ID, &id, NULL); in ov64a40_identify()
3443 dev_err(ov64a40->dev, "Failed to read chip id: %d\n", ret); in ov64a40_identify()
3448 dev_err(ov64a40->dev, "chip id mismatch: %#llx\n", id); in ov64a40_identify()
3452 dev_dbg(ov64a40->dev, "OV64A40 chip identified: %#llx\n", id); in ov64a40_identify()
3457 static int ov64a40_parse_dt(struct ov64a40 *ov64a40) in ov64a40_parse_dt() argument
3466 endpoint = fwnode_graph_get_next_endpoint(dev_fwnode(ov64a40->dev), in ov64a40_parse_dt()
3469 dev_err(ov64a40->dev, "Failed to find endpoint\n"); in ov64a40_parse_dt()
3476 dev_err(ov64a40->dev, "Failed to parse endpoint\n"); in ov64a40_parse_dt()
3481 dev_err(ov64a40->dev, "Unsupported number of data lanes: %u\n", in ov64a40_parse_dt()
3488 dev_warn(ov64a40->dev, "no link frequencies defined\n"); in ov64a40_parse_dt()
3494 dev_warn(ov64a40->dev, in ov64a40_parse_dt()
3500 ov64a40->link_frequencies = in ov64a40_parse_dt()
3501 devm_kcalloc(ov64a40->dev, v4l2_fwnode.nr_of_link_frequencies, in ov64a40_parse_dt()
3504 if (!ov64a40->link_frequencies) { in ov64a40_parse_dt()
3508 ov64a40->num_link_frequencies = v4l2_fwnode.nr_of_link_frequencies; in ov64a40_parse_dt()
3513 dev_err(ov64a40->dev, in ov64a40_parse_dt()
3520 ov64a40->link_frequencies[i] = v4l2_fwnode.link_frequencies[i]; in ov64a40_parse_dt()
3528 static int ov64a40_get_regulators(struct ov64a40 *ov64a40) in ov64a40_get_regulators() argument
3530 struct i2c_client *client = v4l2_get_subdevdata(&ov64a40->sd); in ov64a40_get_regulators()
3534 ov64a40->supplies[i].supply = ov64a40_supply_names[i]; in ov64a40_get_regulators()
3538 ov64a40->supplies); in ov64a40_get_regulators()
3543 struct ov64a40 *ov64a40; in ov64a40_probe() local
3547 ov64a40 = devm_kzalloc(&client->dev, sizeof(*ov64a40), GFP_KERNEL); in ov64a40_probe()
3548 if (!ov64a40) in ov64a40_probe()
3551 ov64a40->dev = &client->dev; in ov64a40_probe()
3552 v4l2_i2c_subdev_init(&ov64a40->sd, client, &ov64a40_subdev_ops); in ov64a40_probe()
3554 ov64a40->cci = devm_cci_regmap_init_i2c(client, 16); in ov64a40_probe()
3555 if (IS_ERR(ov64a40->cci)) { in ov64a40_probe()
3557 return PTR_ERR(ov64a40->cci); in ov64a40_probe()
3560 ov64a40->xclk = devm_clk_get(&client->dev, NULL); in ov64a40_probe()
3561 if (IS_ERR(ov64a40->xclk)) in ov64a40_probe()
3562 return dev_err_probe(&client->dev, PTR_ERR(ov64a40->xclk), in ov64a40_probe()
3565 xclk_freq = clk_get_rate(ov64a40->xclk); in ov64a40_probe()
3572 ret = ov64a40_get_regulators(ov64a40); in ov64a40_probe()
3576 ov64a40->reset_gpio = devm_gpiod_get_optional(&client->dev, "reset", in ov64a40_probe()
3578 if (IS_ERR(ov64a40->reset_gpio)) in ov64a40_probe()
3579 return dev_err_probe(&client->dev, PTR_ERR(ov64a40->reset_gpio), in ov64a40_probe()
3582 ret = ov64a40_parse_dt(ov64a40); in ov64a40_probe()
3590 ret = ov64a40_identify(ov64a40); in ov64a40_probe()
3594 ov64a40->mode = &ov64a40_modes[0]; in ov64a40_probe()
3602 ret = ov64a40_init_controls(ov64a40); in ov64a40_probe()
3607 ov64a40->sd.internal_ops = &ov64a40_internal_ops; in ov64a40_probe()
3608 ov64a40->sd.flags = V4L2_SUBDEV_FL_HAS_DEVNODE in ov64a40_probe()
3610 ov64a40->sd.entity.function = MEDIA_ENT_F_CAM_SENSOR; in ov64a40_probe()
3612 ov64a40->pad.flags = MEDIA_PAD_FL_SOURCE; in ov64a40_probe()
3613 ret = media_entity_pads_init(&ov64a40->sd.entity, 1, &ov64a40->pad); in ov64a40_probe()
3619 ov64a40->sd.state_lock = ov64a40->ctrl_handler.lock; in ov64a40_probe()
3620 ret = v4l2_subdev_init_finalize(&ov64a40->sd); in ov64a40_probe()
3626 ret = v4l2_async_register_subdev_sensor(&ov64a40->sd); in ov64a40_probe()
3639 v4l2_subdev_cleanup(&ov64a40->sd); in ov64a40_probe()
3641 media_entity_cleanup(&ov64a40->sd.entity); in ov64a40_probe()
3643 v4l2_ctrl_handler_free(ov64a40->sd.ctrl_handler); in ov64a40_probe()