588 static int ov2740_write_reg(struct ov2740 *ov2740, u16 reg, u16 len, u32 val)  in ov2740_write_reg()  function
615 		ret = ov2740_write_reg(ov2740, r_list->regs[i].address, 1,  in ov2740_write_reg_list()
656 	ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,  in ov2740_update_digital_gain()
661 	ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_R_GAIN, 2, d_gain);  in ov2740_update_digital_gain()
665 	ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_G_GAIN, 2, d_gain);  in ov2740_update_digital_gain()
669 	ret = ov2740_write_reg(ov2740, OV2740_REG_MWB_B_GAIN, 2, d_gain);  in ov2740_update_digital_gain()
673 	ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,  in ov2740_update_digital_gain()
678 	ret = ov2740_write_reg(ov2740, OV2740_REG_GROUP_ACCESS, 1,  in ov2740_update_digital_gain()
689 	return ov2740_write_reg(ov2740, OV2740_REG_TEST_PATTERN, 1, pattern);  in ov2740_test_pattern()
717 		ret = ov2740_write_reg(ov2740, OV2740_REG_ANALOG_GAIN, 2,  in ov2740_set_ctrl()
727 		ret = ov2740_write_reg(ov2740, OV2740_REG_EXPOSURE, 3,  in ov2740_set_ctrl()
732 		ret = ov2740_write_reg(ov2740, OV2740_REG_VTS, 2,  in ov2740_set_ctrl()
861 	ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1,  in ov2740_load_otp_data()
869 	ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1,  in ov2740_load_otp_data()
876 	ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,  in ov2740_load_otp_data()
896 	ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,  in ov2740_load_otp_data()
903 	ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL01, 1, isp_ctrl01);  in ov2740_load_otp_data()
909 	ret = ov2740_write_reg(ov2740, OV2740_REG_ISP_CTRL00, 1, isp_ctrl00);  in ov2740_load_otp_data()
938 	ret = ov2740_write_reg(ov2740, 0x0103, 1, 0x01);  in ov2740_start_streaming()
965 	ret = ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,  in ov2740_start_streaming()
977 	if (ov2740_write_reg(ov2740, OV2740_REG_MODE_SELECT, 1,  in ov2740_stop_streaming()