90 	struct clk		*xvclk;  member
109 /* PLL settings bases on 24M xvclk */
457 	ret = clk_prepare_enable(ov2685->xvclk);  in __ov2685_power_on()
459 		dev_err(dev, "Failed to enable xvclk\n");  in __ov2685_power_on()
473 	/* 8192 xvclk cycles prior to the first SCCB transaction */  in __ov2685_power_on()
491 	clk_disable_unprepare(ov2685->xvclk);  in __ov2685_power_on()
498 	/* 512 xvclk cycles after the last SCCB transaction or MIPI frame end */  in __ov2685_power_off()
502 	clk_disable_unprepare(ov2685->xvclk);  in __ov2685_power_off()
786 	ov2685->xvclk = devm_clk_get(dev, "xvclk");  in ov2685_probe()
787 	if (IS_ERR(ov2685->xvclk)) {  in ov2685_probe()
788 		dev_err(dev, "Failed to get xvclk\n");  in ov2685_probe()
791 	ret = clk_set_rate(ov2685->xvclk, OV2685_XVCLK_FREQ);  in ov2685_probe()
793 		dev_err(dev, "Failed to set xvclk rate (24MHz)\n");  in ov2685_probe()
796 	if (clk_get_rate(ov2685->xvclk) != OV2685_XVCLK_FREQ)  in ov2685_probe()
797 		dev_warn(dev, "xvclk mismatched, modes are based on 24MHz\n");  in ov2685_probe()