15 #define HI847_REG_VALUE_16BIT		2  macro
2253 				      HI847_REG_VALUE_16BIT,  in hi847_write_reg_list()
2271 			      HI847_REG_VALUE_16BIT, d_gain);  in hi847_update_digital_gain()
2276 			      HI847_REG_VALUE_16BIT, d_gain);  in hi847_update_digital_gain()
2281 			      HI847_REG_VALUE_16BIT, d_gain);  in hi847_update_digital_gain()
2286 			       HI847_REG_VALUE_16BIT, d_gain);  in hi847_update_digital_gain()
2296 				     HI847_REG_VALUE_16BIT, &val);  in hi847_test_pattern()
2301 				      HI847_REG_VALUE_16BIT,  in hi847_test_pattern()
2308 			     HI847_REG_VALUE_16BIT, &val);  in hi847_test_pattern()
2313 			       HI847_REG_VALUE_16BIT, val | pattern << 8);  in hi847_test_pattern()
2348 				      HI847_REG_VALUE_16BIT,  in hi847_grbg_shift()
2354 				       HI847_REG_VALUE_16BIT,  in hi847_grbg_shift()
2358 				      HI847_REG_VALUE_16BIT,  in hi847_grbg_shift()
2364 				       HI847_REG_VALUE_16BIT,  in hi847_grbg_shift()
2375 			     HI847_REG_VALUE_16BIT, &val);  in hi847_set_ctrl_hflip()
2384 			       HI847_REG_VALUE_16BIT,  in hi847_set_ctrl_hflip()
2394 			     HI847_REG_VALUE_16BIT, &val);  in hi847_set_ctrl_vflip()
2403 			       HI847_REG_VALUE_16BIT,  in hi847_set_ctrl_vflip()
2433 				      HI847_REG_VALUE_16BIT, ctrl->val);  in hi847_set_ctrl()
2442 				      HI847_REG_VALUE_16BIT, ctrl->val);  in hi847_set_ctrl()
2448 				      HI847_REG_VALUE_16BIT,  in hi847_set_ctrl()
2584 			      HI847_REG_VALUE_16BIT, HI847_REG_MODE_TG_ENABLE);  in hi847_start_streaming()
2587 			      HI847_REG_VALUE_16BIT, HI847_MODE_STREAMING);  in hi847_start_streaming()
2602 			    HI847_REG_VALUE_16BIT, HI847_REG_MODE_TG_DISABLE))  in hi847_stop_streaming()
2607 			    HI847_REG_VALUE_16BIT, HI847_MODE_STANDBY))  in hi847_stop_streaming()
2776 			     HI847_REG_VALUE_16BIT, &val);  in hi847_identify_module()