457 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in afe_write()  function
466 	return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);  in afe_write_and_or()
929 		afe_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
1292 		afe_write(sd, 0xc8, ctrl->val);  in adv7842_s_ctrl()
1804 		afe_write(sd, 0x00, 0x00); /* power up ADC */  in select_input()
1805 		afe_write(sd, 0xc8, 0x00); /* phase control */  in select_input()
1813 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/  in select_input()
1814 			afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/  in select_input()
1816 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/  in select_input()
1817 			afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/  in select_input()
1819 		afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */  in select_input()
1820 		afe_write(sd, 0x12, 0x63); /* ADI recommend write */  in select_input()
1852 		afe_write(sd, 0x00, 0x00); /* power up ADC */  in select_input()
1853 		afe_write(sd, 0xc8, 0x00); /* phase control */  in select_input()
1865 		afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */  in select_input()
1866 		afe_write(sd, 0x12, 0x63); /* ADC Range improvement */  in select_input()
1917 		afe_write(sd, 0x00, 0xff); /* power down ADC */  in select_input()
1918 		afe_write(sd, 0xc8, 0x40); /* phase control */  in select_input()
1929 		afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */  in select_input()
1930 		afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */  in select_input()
3045 	afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */  in adv7842_core_init()
3047 	afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */  in adv7842_core_init()
3123 	afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */  in adv7842_ddr_ram_test()
3124 	afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3125 	afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3126 	afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3127 	afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3128 	afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()