1 // SPDX-License-Identifier: GPL-2.0-only
3  * adv7842 - Analog Devices ADV7842 video decoder driver
10  * REF_01 - Analog devices, ADV7842,
12  * REF_02 - Analog devices, Software User Guide, UG-206,
14  * REF_03 - Analog devices, Hardware User Guide, UG-214,
15  *		ADV7842 Fast Switching 2:1 HDMI 1.4 Receiver with 3D-Comb
27 #include <linux/v4l2-dv-timings.h>
30 #include <media/v4l2-device.h>
31 #include <media/v4l2-event.h>
32 #include <media/v4l2-ctrls.h>
33 #include <media/v4l2-dv-timings.h>
38 MODULE_PARM_DESC(debug, "debug level (0-2)");
48 #define ADV7842_RGB_OUT					(1 << 1)
51 #define ADV7842_OP_FORMAT_SEL_10BIT			(1 << 0)
55 #define ADV7842_OP_MODE_SEL_DDR_422			(1 << 5)
62 #define ADV7842_OP_CH_SEL_GRB				(1 << 5)
68 #define ADV7842_OP_SWAP_CB_CR				(1 << 0)
90 	struct v4l2_subdev sd;  member
91 	struct media_pad pads[ADV7842_PAD_SOURCE + 1];
247 /* ----------------------------------------------------------------------- */
249 static inline struct adv7842_state *to_state(struct v4l2_subdev *sd)  in to_state()  argument
251 	return container_of(sd, struct adv7842_state, sd);  in to_state()
256 	return &container_of(ctrl->handler, struct adv7842_state, hdl)->sd;  in to_sd()
270 /* ----------------------------------------------------------------------- */
277 	if (!i2c_smbus_xfer(client->adapter, client->addr, client->flags,  in adv_smbus_read_byte_data_check()
283 			client->addr, command);  in adv_smbus_read_byte_data_check()
284 	return -EIO;  in adv_smbus_read_byte_data_check()
301 	return -EIO;  in adv_smbus_read_byte_data()
313 		err = i2c_smbus_xfer(client->adapter, client->addr,  in adv_smbus_write_byte_data()
314 				     client->flags,  in adv_smbus_write_byte_data()
322 			client->addr, command, value);  in adv_smbus_write_byte_data()
332 	i2c_smbus_xfer(client->adapter, client->addr,  in adv_smbus_write_byte_no_check()
333 		       client->flags,  in adv_smbus_write_byte_no_check()
338 /* ----------------------------------------------------------------------- */
340 static inline int io_read(struct v4l2_subdev *sd, u8 reg)  in io_read()  argument
342 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in io_read()
347 static inline int io_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in io_write()  argument
349 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in io_write()
354 static inline int io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in io_write_and_or()  argument
356 	return io_write(sd, reg, (io_read(sd, reg) & mask) | val);  in io_write_and_or()
359 static inline int io_write_clr_set(struct v4l2_subdev *sd,  in io_write_clr_set()  argument
362 	return io_write(sd, reg, (io_read(sd, reg) & ~mask) | val);  in io_write_clr_set()
365 static inline int avlink_read(struct v4l2_subdev *sd, u8 reg)  in avlink_read()  argument
367 	struct adv7842_state *state = to_state(sd);  in avlink_read()
369 	return adv_smbus_read_byte_data(state->i2c_avlink, reg);  in avlink_read()
372 static inline int avlink_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in avlink_write()  argument
374 	struct adv7842_state *state = to_state(sd);  in avlink_write()
376 	return adv_smbus_write_byte_data(state->i2c_avlink, reg, val);  in avlink_write()
379 static inline int cec_read(struct v4l2_subdev *sd, u8 reg)  in cec_read()  argument
381 	struct adv7842_state *state = to_state(sd);  in cec_read()
383 	return adv_smbus_read_byte_data(state->i2c_cec, reg);  in cec_read()
386 static inline int cec_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in cec_write()  argument
388 	struct adv7842_state *state = to_state(sd);  in cec_write()
390 	return adv_smbus_write_byte_data(state->i2c_cec, reg, val);  in cec_write()
393 static inline int cec_write_clr_set(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in cec_write_clr_set()  argument
395 	return cec_write(sd, reg, (cec_read(sd, reg) & ~mask) | val);  in cec_write_clr_set()
398 static inline int infoframe_read(struct v4l2_subdev *sd, u8 reg)  in infoframe_read()  argument
400 	struct adv7842_state *state = to_state(sd);  in infoframe_read()
402 	return adv_smbus_read_byte_data(state->i2c_infoframe, reg);  in infoframe_read()
405 static inline int infoframe_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in infoframe_write()  argument
407 	struct adv7842_state *state = to_state(sd);  in infoframe_write()
409 	return adv_smbus_write_byte_data(state->i2c_infoframe, reg, val);  in infoframe_write()
412 static inline int sdp_io_read(struct v4l2_subdev *sd, u8 reg)  in sdp_io_read()  argument
414 	struct adv7842_state *state = to_state(sd);  in sdp_io_read()
416 	return adv_smbus_read_byte_data(state->i2c_sdp_io, reg);  in sdp_io_read()
419 static inline int sdp_io_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in sdp_io_write()  argument
421 	struct adv7842_state *state = to_state(sd);  in sdp_io_write()
423 	return adv_smbus_write_byte_data(state->i2c_sdp_io, reg, val);  in sdp_io_write()
426 static inline int sdp_io_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in sdp_io_write_and_or()  argument
428 	return sdp_io_write(sd, reg, (sdp_io_read(sd, reg) & mask) | val);  in sdp_io_write_and_or()
431 static inline int sdp_read(struct v4l2_subdev *sd, u8 reg)  in sdp_read()  argument
433 	struct adv7842_state *state = to_state(sd);  in sdp_read()
435 	return adv_smbus_read_byte_data(state->i2c_sdp, reg);  in sdp_read()
438 static inline int sdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in sdp_write()  argument
440 	struct adv7842_state *state = to_state(sd);  in sdp_write()
442 	return adv_smbus_write_byte_data(state->i2c_sdp, reg, val);  in sdp_write()
445 static inline int sdp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in sdp_write_and_or()  argument
447 	return sdp_write(sd, reg, (sdp_read(sd, reg) & mask) | val);  in sdp_write_and_or()
450 static inline int afe_read(struct v4l2_subdev *sd, u8 reg)  in afe_read()  argument
452 	struct adv7842_state *state = to_state(sd);  in afe_read()
454 	return adv_smbus_read_byte_data(state->i2c_afe, reg);  in afe_read()
457 static inline int afe_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in afe_write()  argument
459 	struct adv7842_state *state = to_state(sd);  in afe_write()
461 	return adv_smbus_write_byte_data(state->i2c_afe, reg, val);  in afe_write()
464 static inline int afe_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in afe_write_and_or()  argument
466 	return afe_write(sd, reg, (afe_read(sd, reg) & mask) | val);  in afe_write_and_or()
469 static inline int rep_read(struct v4l2_subdev *sd, u8 reg)  in rep_read()  argument
471 	struct adv7842_state *state = to_state(sd);  in rep_read()
473 	return adv_smbus_read_byte_data(state->i2c_repeater, reg);  in rep_read()
476 static inline int rep_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in rep_write()  argument
478 	struct adv7842_state *state = to_state(sd);  in rep_write()
480 	return adv_smbus_write_byte_data(state->i2c_repeater, reg, val);  in rep_write()
483 static inline int rep_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in rep_write_and_or()  argument
485 	return rep_write(sd, reg, (rep_read(sd, reg) & mask) | val);  in rep_write_and_or()
488 static inline int edid_read(struct v4l2_subdev *sd, u8 reg)  in edid_read()  argument
490 	struct adv7842_state *state = to_state(sd);  in edid_read()
492 	return adv_smbus_read_byte_data(state->i2c_edid, reg);  in edid_read()
495 static inline int edid_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in edid_write()  argument
497 	struct adv7842_state *state = to_state(sd);  in edid_write()
499 	return adv_smbus_write_byte_data(state->i2c_edid, reg, val);  in edid_write()
502 static inline int hdmi_read(struct v4l2_subdev *sd, u8 reg)  in hdmi_read()  argument
504 	struct adv7842_state *state = to_state(sd);  in hdmi_read()
506 	return adv_smbus_read_byte_data(state->i2c_hdmi, reg);  in hdmi_read()
509 static inline int hdmi_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in hdmi_write()  argument
511 	struct adv7842_state *state = to_state(sd);  in hdmi_write()
513 	return adv_smbus_write_byte_data(state->i2c_hdmi, reg, val);  in hdmi_write()
516 static inline int hdmi_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in hdmi_write_and_or()  argument
518 	return hdmi_write(sd, reg, (hdmi_read(sd, reg) & mask) | val);  in hdmi_write_and_or()
521 static inline int cp_read(struct v4l2_subdev *sd, u8 reg)  in cp_read()  argument
523 	struct adv7842_state *state = to_state(sd);  in cp_read()
525 	return adv_smbus_read_byte_data(state->i2c_cp, reg);  in cp_read()
528 static inline int cp_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in cp_write()  argument
530 	struct adv7842_state *state = to_state(sd);  in cp_write()
532 	return adv_smbus_write_byte_data(state->i2c_cp, reg, val);  in cp_write()
535 static inline int cp_write_and_or(struct v4l2_subdev *sd, u8 reg, u8 mask, u8 val)  in cp_write_and_or()  argument
537 	return cp_write(sd, reg, (cp_read(sd, reg) & mask) | val);  in cp_write_and_or()
540 static inline int vdp_read(struct v4l2_subdev *sd, u8 reg)  in vdp_read()  argument
542 	struct adv7842_state *state = to_state(sd);  in vdp_read()
544 	return adv_smbus_read_byte_data(state->i2c_vdp, reg);  in vdp_read()
547 static inline int vdp_write(struct v4l2_subdev *sd, u8 reg, u8 val)  in vdp_write()  argument
549 	struct adv7842_state *state = to_state(sd);  in vdp_write()
551 	return adv_smbus_write_byte_data(state->i2c_vdp, reg, val);  in vdp_write()
554 static void main_reset(struct v4l2_subdev *sd)  in main_reset()  argument
556 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in main_reset()
558 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);  in main_reset()
565 /* -----------------------------------------------------------------------------
623 /* ----------------------------------------------------------------------- */
625 static inline bool is_analog_input(struct v4l2_subdev *sd)  in is_analog_input()  argument
627 	struct adv7842_state *state = to_state(sd);  in is_analog_input()
629 	return ((state->mode == ADV7842_MODE_RGB) ||  in is_analog_input()
630 		(state->mode == ADV7842_MODE_COMP));  in is_analog_input()
633 static inline bool is_digital_input(struct v4l2_subdev *sd)  in is_digital_input()  argument
635 	struct adv7842_state *state = to_state(sd);  in is_digital_input()
637 	return state->mode == ADV7842_MODE_HDMI;  in is_digital_input()
663 adv7842_get_dv_timings_cap(struct v4l2_subdev *sd)  in adv7842_get_dv_timings_cap()  argument
665 	return is_digital_input(sd) ? &adv7842_timings_cap_digital :  in adv7842_get_dv_timings_cap()
669 /* ----------------------------------------------------------------------- */
671 static u16 adv7842_read_cable_det(struct v4l2_subdev *sd)  in adv7842_read_cable_det()  argument
673 	u8 reg = io_read(sd, 0x6f);  in adv7842_read_cable_det()
677 		val |= 1; /* port A */  in adv7842_read_cable_det()
688 	struct v4l2_subdev *sd = &state->sd;  in adv7842_delayed_work_enable_hotplug()  local
689 	int present = state->hdmi_edid.present;  in adv7842_delayed_work_enable_hotplug()
692 	v4l2_dbg(2, debug, sd, "%s: enable hotplug on ports: 0x%x\n",  in adv7842_delayed_work_enable_hotplug()
699 	io_write_and_or(sd, 0x20, 0xcf, mask);  in adv7842_delayed_work_enable_hotplug()
702 static int edid_write_vga_segment(struct v4l2_subdev *sd)  in edid_write_vga_segment()  argument
704 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in edid_write_vga_segment()
705 	struct adv7842_state *state = to_state(sd);  in edid_write_vga_segment()
706 	const u8 *edid = state->vga_edid.edid;  in edid_write_vga_segment()
707 	u32 blocks = state->vga_edid.blocks;  in edid_write_vga_segment()
711 	v4l2_dbg(2, debug, sd, "%s: write EDID on VGA port\n", __func__);  in edid_write_vga_segment()
713 	if (!state->vga_edid.present)  in edid_write_vga_segment()
717 	io_write_and_or(sd, 0x20, 0xcf, 0x00);  in edid_write_vga_segment()
720 	rep_write_and_or(sd, 0x7f, 0x7f, 0x00);  in edid_write_vga_segment()
722 	/* edid segment pointer '1' for VGA port */  in edid_write_vga_segment()
723 	rep_write_and_or(sd, 0x77, 0xef, 0x10);  in edid_write_vga_segment()
726 		err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i,  in edid_write_vga_segment()
735 	rep_write_and_or(sd, 0x7f, 0x7f, 0x80);  in edid_write_vga_segment()
738 		if (rep_read(sd, 0x79) & 0x20)  in edid_write_vga_segment()
740 		mdelay(1);  in edid_write_vga_segment()
744 		return -EIO;  in edid_write_vga_segment()
748 	schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);  in edid_write_vga_segment()
753 static int edid_write_hdmi_segment(struct v4l2_subdev *sd, u8 port)  in edid_write_hdmi_segment()  argument
755 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in edid_write_hdmi_segment()
756 	struct adv7842_state *state = to_state(sd);  in edid_write_hdmi_segment()
757 	const u8 *edid = state->hdmi_edid.edid;  in edid_write_hdmi_segment()
758 	u32 blocks = state->hdmi_edid.blocks;  in edid_write_hdmi_segment()
764 	v4l2_dbg(2, debug, sd, "%s: write EDID on port %c\n",  in edid_write_hdmi_segment()
768 	io_write_and_or(sd, 0x20, 0xcf, 0x00);  in edid_write_hdmi_segment()
771 	rep_write_and_or(sd, 0x77, 0xf3, 0x00);  in edid_write_hdmi_segment()
773 	if (!state->hdmi_edid.present) {  in edid_write_hdmi_segment()
774 		cec_phys_addr_invalidate(state->cec_adap);  in edid_write_hdmi_segment()
789 		pa = (edid[spa_loc] << 8) | edid[spa_loc + 1];  in edid_write_hdmi_segment()
796 			rep_write_and_or(sd, 0x77, 0xef, i >= 256 ? 0x10 : 0x00);  in edid_write_hdmi_segment()
797 		err = i2c_smbus_write_i2c_block_data(state->i2c_edid, i,  in edid_write_hdmi_segment()
804 		rep_write(sd, 0x72, pa >> 8);  in edid_write_hdmi_segment()
805 		rep_write(sd, 0x73, pa & 0xff);  in edid_write_hdmi_segment()
807 		rep_write(sd, 0x74, pa >> 8);  in edid_write_hdmi_segment()
808 		rep_write(sd, 0x75, pa & 0xff);  in edid_write_hdmi_segment()
810 	rep_write(sd, 0x76, spa_loc & 0xff);  in edid_write_hdmi_segment()
811 	rep_write_and_or(sd, 0x77, 0xbf, (spa_loc >> 2) & 0x40);  in edid_write_hdmi_segment()
816 	rep_write_and_or(sd, 0x77, 0xf3, state->hdmi_edid.present);  in edid_write_hdmi_segment()
819 		if (rep_read(sd, 0x7d) & state->hdmi_edid.present)  in edid_write_hdmi_segment()
821 		mdelay(1);  in edid_write_hdmi_segment()
826 		return -EIO;  in edid_write_hdmi_segment()
828 	cec_s_phys_addr(state->cec_adap, parent_pa, false);  in edid_write_hdmi_segment()
831 	schedule_delayed_work(&state->delayed_work_enable_hotplug, HZ / 5);  in edid_write_hdmi_segment()
836 /* ----------------------------------------------------------------------- */
839 static void adv7842_inv_register(struct v4l2_subdev *sd)  in adv7842_inv_register()  argument
841 	v4l2_info(sd, "0x000-0x0ff: IO Map\n");  in adv7842_inv_register()
842 	v4l2_info(sd, "0x100-0x1ff: AVLink Map\n");  in adv7842_inv_register()
843 	v4l2_info(sd, "0x200-0x2ff: CEC Map\n");  in adv7842_inv_register()
844 	v4l2_info(sd, "0x300-0x3ff: InfoFrame Map\n");  in adv7842_inv_register()
845 	v4l2_info(sd, "0x400-0x4ff: SDP_IO Map\n");  in adv7842_inv_register()
846 	v4l2_info(sd, "0x500-0x5ff: SDP Map\n");  in adv7842_inv_register()
847 	v4l2_info(sd, "0x600-0x6ff: AFE Map\n");  in adv7842_inv_register()
848 	v4l2_info(sd, "0x700-0x7ff: Repeater Map\n");  in adv7842_inv_register()
849 	v4l2_info(sd, "0x800-0x8ff: EDID Map\n");  in adv7842_inv_register()
850 	v4l2_info(sd, "0x900-0x9ff: HDMI Map\n");  in adv7842_inv_register()
851 	v4l2_info(sd, "0xa00-0xaff: CP Map\n");  in adv7842_inv_register()
852 	v4l2_info(sd, "0xb00-0xbff: VDP Map\n");  in adv7842_inv_register()
855 static int adv7842_g_register(struct v4l2_subdev *sd,  in adv7842_g_register()  argument
858 	reg->size = 1;  in adv7842_g_register()
859 	switch (reg->reg >> 8) {  in adv7842_g_register()
861 		reg->val = io_read(sd, reg->reg & 0xff);  in adv7842_g_register()
863 	case 1:  in adv7842_g_register()
864 		reg->val = avlink_read(sd, reg->reg & 0xff);  in adv7842_g_register()
867 		reg->val = cec_read(sd, reg->reg & 0xff);  in adv7842_g_register()
870 		reg->val = infoframe_read(sd, reg->reg & 0xff);  in adv7842_g_register()
873 		reg->val = sdp_io_read(sd, reg->reg & 0xff);  in adv7842_g_register()
876 		reg->val = sdp_read(sd, reg->reg & 0xff);  in adv7842_g_register()
879 		reg->val = afe_read(sd, reg->reg & 0xff);  in adv7842_g_register()
882 		reg->val = rep_read(sd, reg->reg & 0xff);  in adv7842_g_register()
885 		reg->val = edid_read(sd, reg->reg & 0xff);  in adv7842_g_register()
888 		reg->val = hdmi_read(sd, reg->reg & 0xff);  in adv7842_g_register()
891 		reg->val = cp_read(sd, reg->reg & 0xff);  in adv7842_g_register()
894 		reg->val = vdp_read(sd, reg->reg & 0xff);  in adv7842_g_register()
897 		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);  in adv7842_g_register()
898 		adv7842_inv_register(sd);  in adv7842_g_register()
904 static int adv7842_s_register(struct v4l2_subdev *sd,  in adv7842_s_register()  argument
907 	u8 val = reg->val & 0xff;  in adv7842_s_register()
909 	switch (reg->reg >> 8) {  in adv7842_s_register()
911 		io_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
913 	case 1:  in adv7842_s_register()
914 		avlink_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
917 		cec_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
920 		infoframe_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
923 		sdp_io_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
926 		sdp_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
929 		afe_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
932 		rep_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
935 		edid_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
938 		hdmi_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
941 		cp_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
944 		vdp_write(sd, reg->reg & 0xff, val);  in adv7842_s_register()
947 		v4l2_info(sd, "Register %03llx not supported\n", reg->reg);  in adv7842_s_register()
948 		adv7842_inv_register(sd);  in adv7842_s_register()
955 static int adv7842_s_detect_tx_5v_ctrl(struct v4l2_subdev *sd)  in adv7842_s_detect_tx_5v_ctrl()  argument
957 	struct adv7842_state *state = to_state(sd);  in adv7842_s_detect_tx_5v_ctrl()
958 	u16 cable_det = adv7842_read_cable_det(sd);  in adv7842_s_detect_tx_5v_ctrl()
960 	v4l2_dbg(1, debug, sd, "%s: 0x%x\n", __func__, cable_det);  in adv7842_s_detect_tx_5v_ctrl()
962 	return v4l2_ctrl_s_ctrl(state->detect_tx_5v_ctrl, cable_det);  in adv7842_s_detect_tx_5v_ctrl()
965 static int find_and_set_predefined_video_timings(struct v4l2_subdev *sd,  in find_and_set_predefined_video_timings()  argument
974 				  is_digital_input(sd) ? 250000 : 1000000, false))  in find_and_set_predefined_video_timings()
977 		io_write(sd, 0x00, predef_vid_timings[i].vid_std);  in find_and_set_predefined_video_timings()
979 		io_write(sd, 0x01, (predef_vid_timings[i].v_freq << 4) + prim_mode);  in find_and_set_predefined_video_timings()
983 	return -1;  in find_and_set_predefined_video_timings()
986 static int configure_predefined_video_timings(struct v4l2_subdev *sd,  in configure_predefined_video_timings()  argument
989 	struct adv7842_state *state = to_state(sd);  in configure_predefined_video_timings()
992 	v4l2_dbg(1, debug, sd, "%s\n", __func__);  in configure_predefined_video_timings()
995 	io_write(sd, 0x16, 0x43);  in configure_predefined_video_timings()
996 	io_write(sd, 0x17, 0x5a);  in configure_predefined_video_timings()
998 	cp_write_and_or(sd, 0x81, 0xef, 0x00);  in configure_predefined_video_timings()
999 	cp_write(sd, 0x26, 0x00);  in configure_predefined_video_timings()
1000 	cp_write(sd, 0x27, 0x00);  in configure_predefined_video_timings()
1001 	cp_write(sd, 0x28, 0x00);  in configure_predefined_video_timings()
1002 	cp_write(sd, 0x29, 0x00);  in configure_predefined_video_timings()
1003 	cp_write(sd, 0x8f, 0x40);  in configure_predefined_video_timings()
1004 	cp_write(sd, 0x90, 0x00);  in configure_predefined_video_timings()
1005 	cp_write(sd, 0xa5, 0x00);  in configure_predefined_video_timings()
1006 	cp_write(sd, 0xa6, 0x00);  in configure_predefined_video_timings()
1007 	cp_write(sd, 0xa7, 0x00);  in configure_predefined_video_timings()
1008 	cp_write(sd, 0xab, 0x00);  in configure_predefined_video_timings()
1009 	cp_write(sd, 0xac, 0x00);  in configure_predefined_video_timings()
1011 	switch (state->mode) {  in configure_predefined_video_timings()
1014 		err = find_and_set_predefined_video_timings(sd,  in configure_predefined_video_timings()
1017 			err = find_and_set_predefined_video_timings(sd,  in configure_predefined_video_timings()
1021 		err = find_and_set_predefined_video_timings(sd,  in configure_predefined_video_timings()
1024 			err = find_and_set_predefined_video_timings(sd,  in configure_predefined_video_timings()
1028 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",  in configure_predefined_video_timings()
1029 				__func__, state->mode);  in configure_predefined_video_timings()
1030 		err = -1;  in configure_predefined_video_timings()
1038 static void configure_custom_video_timings(struct v4l2_subdev *sd,  in configure_custom_video_timings()  argument
1041 	struct adv7842_state *state = to_state(sd);  in configure_custom_video_timings()
1042 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in configure_custom_video_timings()
1045 	u16 cp_start_sav = bt->hsync + bt->hbackporch - 4;  in configure_custom_video_timings()
1046 	u16 cp_start_eav = width - bt->hfrontporch;  in configure_custom_video_timings()
1047 	u16 cp_start_vbi = height - bt->vfrontporch + 1;  in configure_custom_video_timings()
1048 	u16 cp_end_vbi = bt->vsync + bt->vbackporch + 1;  in configure_custom_video_timings()
1049 	u16 ch1_fr_ll = (((u32)bt->pixelclock / 100) > 0) ?  in configure_custom_video_timings()
1050 		((width * (ADV7842_fsc / 100)) / ((u32)bt->pixelclock / 100)) : 0;  in configure_custom_video_timings()
1056 	v4l2_dbg(2, debug, sd, "%s\n", __func__);  in configure_custom_video_timings()
1058 	switch (state->mode) {  in configure_custom_video_timings()
1062 		io_write(sd, 0x00, 0x07); /* video std */  in configure_custom_video_timings()
1063 		io_write(sd, 0x01, 0x02); /* prim mode */  in configure_custom_video_timings()
1065 		cp_write_and_or(sd, 0x81, 0xef, 0x10);  in configure_custom_video_timings()
1067 		/* Should only be set in auto-graphics mode [REF_02, p. 91-92] */  in configure_custom_video_timings()
1069 		/* IO-map reg. 0x16 and 0x17 should be written in sequence */  in configure_custom_video_timings()
1071 			v4l2_err(sd, "writing to reg 0x16 and 0x17 failed\n");  in configure_custom_video_timings()
1075 		/* active video - horizontal timing */  in configure_custom_video_timings()
1076 		cp_write(sd, 0x26, (cp_start_sav >> 8) & 0xf);  in configure_custom_video_timings()
1077 		cp_write(sd, 0x27, (cp_start_sav & 0xff));  in configure_custom_video_timings()
1078 		cp_write(sd, 0x28, (cp_start_eav >> 8) & 0xf);  in configure_custom_video_timings()
1079 		cp_write(sd, 0x29, (cp_start_eav & 0xff));  in configure_custom_video_timings()
1081 		/* active video - vertical timing */  in configure_custom_video_timings()
1082 		cp_write(sd, 0xa5, (cp_start_vbi >> 4) & 0xff);  in configure_custom_video_timings()
1083 		cp_write(sd, 0xa6, ((cp_start_vbi & 0xf) << 4) |  in configure_custom_video_timings()
1085 		cp_write(sd, 0xa7, cp_end_vbi & 0xff);  in configure_custom_video_timings()
1090 		io_write(sd, 0x00, 0x02); /* video std */  in configure_custom_video_timings()
1091 		io_write(sd, 0x01, 0x06); /* prim mode */  in configure_custom_video_timings()
1094 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",  in configure_custom_video_timings()
1095 				__func__, state->mode);  in configure_custom_video_timings()
1099 	cp_write(sd, 0x8f, (ch1_fr_ll >> 8) & 0x7);  in configure_custom_video_timings()
1100 	cp_write(sd, 0x90, ch1_fr_ll & 0xff);  in configure_custom_video_timings()
1101 	cp_write(sd, 0xab, (height >> 4) & 0xff);  in configure_custom_video_timings()
1102 	cp_write(sd, 0xac, (height & 0x0f) << 4);  in configure_custom_video_timings()
1105 static void adv7842_set_offset(struct v4l2_subdev *sd, bool auto_offset, u16 offset_a, u16 offset_b…  in adv7842_set_offset()  argument
1107 	struct adv7842_state *state = to_state(sd);  in adv7842_set_offset()
1116 	v4l2_dbg(2, debug, sd, "%s: %s offset: a = 0x%x, b = 0x%x, c = 0x%x\n",  in adv7842_set_offset()
1120 	offset_buf[0]= (cp_read(sd, 0x77) & 0xc0) | ((offset_a & 0x3f0) >> 4);  in adv7842_set_offset()
1121 	offset_buf[1] = ((offset_a & 0x00f) << 4) | ((offset_b & 0x3c0) >> 6);  in adv7842_set_offset()
1126 	if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x77, 4, offset_buf))  in adv7842_set_offset()
1127 		v4l2_err(sd, "%s: i2c error writing to CP reg 0x77, 0x78, 0x79, 0x7a\n", __func__);  in adv7842_set_offset()
1130 static void adv7842_set_gain(struct v4l2_subdev *sd, bool auto_gain, u16 gain_a, u16 gain_b, u16 ga…  in adv7842_set_gain()  argument
1132 	struct adv7842_state *state = to_state(sd);  in adv7842_set_gain()
1134 	u8 gain_man = 1;  in adv7842_set_gain()
1135 	u8 agc_mode_man = 1;  in adv7842_set_gain()
1145 	v4l2_dbg(2, debug, sd, "%s: %s gain: a = 0x%x, b = 0x%x, c = 0x%x\n",  in adv7842_set_gain()
1150 	gain_buf[1] = (((gain_a & 0x00f) << 4) | ((gain_b & 0x3c0) >> 6));  in adv7842_set_gain()
1155 	if (i2c_smbus_write_i2c_block_data(state->i2c_cp, 0x73, 4, gain_buf))  in adv7842_set_gain()
1156 		v4l2_err(sd, "%s: i2c error writing to CP reg 0x73, 0x74, 0x75, 0x76\n", __func__);  in adv7842_set_gain()
1159 static void set_rgb_quantization_range(struct v4l2_subdev *sd)  in set_rgb_quantization_range()  argument
1161 	struct adv7842_state *state = to_state(sd);  in set_rgb_quantization_range()
1162 	bool rgb_output = io_read(sd, 0x02) & 0x02;  in set_rgb_quantization_range()
1163 	bool hdmi_signal = hdmi_read(sd, 0x05) & 0x80;  in set_rgb_quantization_range()
1166 	if (hdmi_signal && (io_read(sd, 0x60) & 1))  in set_rgb_quantization_range()
1167 		y = infoframe_read(sd, 0x01) >> 5;  in set_rgb_quantization_range()
1169 	v4l2_dbg(2, debug, sd, "%s: RGB quantization range: %d, RGB out: %d, HDMI: %d\n",  in set_rgb_quantization_range()
1170 			__func__, state->rgb_quantization_range,  in set_rgb_quantization_range()
1173 	adv7842_set_gain(sd, true, 0x0, 0x0, 0x0);  in set_rgb_quantization_range()
1174 	adv7842_set_offset(sd, true, 0x0, 0x0, 0x0);  in set_rgb_quantization_range()
1175 	io_write_clr_set(sd, 0x02, 0x04, rgb_output ? 0 : 4);  in set_rgb_quantization_range()
1177 	switch (state->rgb_quantization_range) {  in set_rgb_quantization_range()
1179 		if (state->mode == ADV7842_MODE_RGB) {  in set_rgb_quantization_range()
1181 			 * Set RGB full range (0-255) */  in set_rgb_quantization_range()
1182 			io_write_and_or(sd, 0x02, 0x0f, 0x10);  in set_rgb_quantization_range()
1186 		if (state->mode == ADV7842_MODE_COMP) {  in set_rgb_quantization_range()
1189 			io_write_and_or(sd, 0x02, 0x0f, 0xf0);  in set_rgb_quantization_range()
1196 			io_write_and_or(sd, 0x02, 0x0f, 0xf0);  in set_rgb_quantization_range()
1200 		/* Receiving DVI-D signal  in set_rgb_quantization_range()
1203 		if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO) {  in set_rgb_quantization_range()
1204 			/* RGB limited range (16-235) */  in set_rgb_quantization_range()
1205 			io_write_and_or(sd, 0x02, 0x0f, 0x00);  in set_rgb_quantization_range()
1207 			/* RGB full range (0-255) */  in set_rgb_quantization_range()
1208 			io_write_and_or(sd, 0x02, 0x0f, 0x10);  in set_rgb_quantization_range()
1210 			if (is_digital_input(sd) && rgb_output) {  in set_rgb_quantization_range()
1211 				adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);  in set_rgb_quantization_range()
1213 				adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);  in set_rgb_quantization_range()
1214 				adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);  in set_rgb_quantization_range()
1219 		if (state->mode == ADV7842_MODE_COMP) {  in set_rgb_quantization_range()
1220 			/* YCrCb limited range (16-235) */  in set_rgb_quantization_range()
1221 			io_write_and_or(sd, 0x02, 0x0f, 0x20);  in set_rgb_quantization_range()
1228 		/* RGB limited range (16-235) */  in set_rgb_quantization_range()
1229 		io_write_and_or(sd, 0x02, 0x0f, 0x00);  in set_rgb_quantization_range()
1233 		if (state->mode == ADV7842_MODE_COMP) {  in set_rgb_quantization_range()
1234 			/* YCrCb full range (0-255) */  in set_rgb_quantization_range()
1235 			io_write_and_or(sd, 0x02, 0x0f, 0x60);  in set_rgb_quantization_range()
1242 		/* RGB full range (0-255) */  in set_rgb_quantization_range()
1243 		io_write_and_or(sd, 0x02, 0x0f, 0x10);  in set_rgb_quantization_range()
1245 		if (is_analog_input(sd) || hdmi_signal)  in set_rgb_quantization_range()
1248 		/* Adjust gain/offset for DVI-D signals only */  in set_rgb_quantization_range()
1250 			adv7842_set_offset(sd, false, 0x40, 0x40, 0x40);  in set_rgb_quantization_range()
1252 			adv7842_set_gain(sd, false, 0xe0, 0xe0, 0xe0);  in set_rgb_quantization_range()
1253 			adv7842_set_offset(sd, false, 0x70, 0x70, 0x70);  in set_rgb_quantization_range()
1261 	struct v4l2_subdev *sd = to_sd(ctrl);  in adv7842_s_ctrl()  local
1262 	struct adv7842_state *state = to_state(sd);  in adv7842_s_ctrl()
1268 	switch (ctrl->id) {  in adv7842_s_ctrl()
1271 		cp_write(sd, 0x3c, ctrl->val);  in adv7842_s_ctrl()
1272 		sdp_write(sd, 0x14, ctrl->val);  in adv7842_s_ctrl()
1276 		cp_write(sd, 0x3a, ctrl->val);  in adv7842_s_ctrl()
1277 		sdp_write(sd, 0x13, ctrl->val);  in adv7842_s_ctrl()
1278 		/* ignore lsb sdp 0x17[1:0] */  in adv7842_s_ctrl()
1281 		cp_write(sd, 0x3b, ctrl->val);  in adv7842_s_ctrl()
1282 		sdp_write(sd, 0x15, ctrl->val);  in adv7842_s_ctrl()
1286 		cp_write(sd, 0x3d, ctrl->val);  in adv7842_s_ctrl()
1287 		sdp_write(sd, 0x16, ctrl->val);  in adv7842_s_ctrl()
1292 		afe_write(sd, 0xc8, ctrl->val);  in adv7842_s_ctrl()
1295 		cp_write_and_or(sd, 0xbf, ~0x04, (ctrl->val << 2));  in adv7842_s_ctrl()
1296 		sdp_write_and_or(sd, 0xdd, ~0x04, (ctrl->val << 2));  in adv7842_s_ctrl()
1299 		u8 R = (ctrl->val & 0xff0000) >> 16;  in adv7842_s_ctrl()
1300 		u8 G = (ctrl->val & 0x00ff00) >> 8;  in adv7842_s_ctrl()
1301 		u8 B = (ctrl->val & 0x0000ff);  in adv7842_s_ctrl()
1302 		/* RGB -> YUV, numerical approximation */  in adv7842_s_ctrl()
1304 		int U = -38 * R - 74 * G + 112 * B;  in adv7842_s_ctrl()
1305 		int V = 112 * R - 94 * G - 18 * B;  in adv7842_s_ctrl()
1316 		v4l2_dbg(1, debug, sd, "R %x, G %x, B %x\n", R, G, B);  in adv7842_s_ctrl()
1317 		v4l2_dbg(1, debug, sd, "Y %x, U %x, V %x\n", Y, U, V);  in adv7842_s_ctrl()
1320 		cp_write(sd, 0xc1, R);  in adv7842_s_ctrl()
1321 		cp_write(sd, 0xc0, G);  in adv7842_s_ctrl()
1322 		cp_write(sd, 0xc2, B);  in adv7842_s_ctrl()
1324 		sdp_write(sd, 0xde, Y);  in adv7842_s_ctrl()
1325 		sdp_write(sd, 0xdf, (V & 0xf0) | ((U >> 4) & 0x0f));  in adv7842_s_ctrl()
1329 		state->rgb_quantization_range = ctrl->val;  in adv7842_s_ctrl()
1330 		set_rgb_quantization_range(sd);  in adv7842_s_ctrl()
1333 	return -EINVAL;  in adv7842_s_ctrl()
1338 	struct v4l2_subdev *sd = to_sd(ctrl);  in adv7842_g_volatile_ctrl()  local
1340 	if (ctrl->id == V4L2_CID_DV_RX_IT_CONTENT_TYPE) {  in adv7842_g_volatile_ctrl()
1341 		ctrl->val = V4L2_DV_IT_CONTENT_TYPE_NO_ITC;  in adv7842_g_volatile_ctrl()
1342 		if ((io_read(sd, 0x60) & 1) && (infoframe_read(sd, 0x03) & 0x80))  in adv7842_g_volatile_ctrl()
1343 			ctrl->val = (infoframe_read(sd, 0x05) >> 4) & 3;  in adv7842_g_volatile_ctrl()
1346 	return -EINVAL;  in adv7842_g_volatile_ctrl()
1349 static inline bool no_power(struct v4l2_subdev *sd)  in no_power()  argument
1351 	return io_read(sd, 0x0c) & 0x24;  in no_power()
1354 static inline bool no_cp_signal(struct v4l2_subdev *sd)  in no_cp_signal()  argument
1356 	return ((cp_read(sd, 0xb5) & 0xd0) != 0xd0) || !(cp_read(sd, 0xb1) & 0x80);  in no_cp_signal()
1359 static inline bool is_hdmi(struct v4l2_subdev *sd)  in is_hdmi()  argument
1361 	return hdmi_read(sd, 0x05) & 0x80;  in is_hdmi()
1364 static int adv7842_g_input_status(struct v4l2_subdev *sd, u32 *status)  in adv7842_g_input_status()  argument
1366 	struct adv7842_state *state = to_state(sd);  in adv7842_g_input_status()
1370 	if (io_read(sd, 0x0c) & 0x24)  in adv7842_g_input_status()
1373 	if (state->mode == ADV7842_MODE_SDP) {  in adv7842_g_input_status()
1375 		if (!(sdp_read(sd, 0x5A) & 0x01))  in adv7842_g_input_status()
1378 		v4l2_dbg(1, debug, sd, "%s: SDP status = 0x%x\n",  in adv7842_g_input_status()
1383 	if ((cp_read(sd, 0xb5) & 0xd0) != 0xd0 ||  in adv7842_g_input_status()
1384 			!(cp_read(sd, 0xb1) & 0x80))  in adv7842_g_input_status()
1388 	if (is_digital_input(sd) && ((io_read(sd, 0x74) & 0x03) != 0x03))  in adv7842_g_input_status()
1391 	v4l2_dbg(1, debug, sd, "%s: CP status = 0x%x\n",  in adv7842_g_input_status()
1403 static int stdi2dv_timings(struct v4l2_subdev *sd,  in stdi2dv_timings()  argument
1407 	struct adv7842_state *state = to_state(sd);  in stdi2dv_timings()
1408 	u32 hfreq = (ADV7842_fsc * 8) / stdi->bl;  in stdi2dv_timings()
1416 					   adv7842_get_dv_timings_cap(sd),  in stdi2dv_timings()
1419 		if (vtotal(bt) != stdi->lcf + 1)  in stdi2dv_timings()
1421 		if (bt->vsync != stdi->lcvs)  in stdi2dv_timings()
1426 		if ((pix_clk < bt->pixelclock + 1000000) &&  in stdi2dv_timings()
1427 		    (pix_clk > bt->pixelclock - 1000000)) {  in stdi2dv_timings()
1433 	if (v4l2_detect_cvt(stdi->lcf + 1, hfreq, stdi->lcvs, 0,  in stdi2dv_timings()
1434 			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |  in stdi2dv_timings()
1435 			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),  in stdi2dv_timings()
1438 	if (v4l2_detect_gtf(stdi->lcf + 1, hfreq, stdi->lcvs,  in stdi2dv_timings()
1439 			(stdi->hs_pol == '+' ? V4L2_DV_HSYNC_POS_POL : 0) |  in stdi2dv_timings()
1440 			(stdi->vs_pol == '+' ? V4L2_DV_VSYNC_POS_POL : 0),  in stdi2dv_timings()
1441 			false, state->aspect_ratio, timings))  in stdi2dv_timings()
1444 	v4l2_dbg(2, debug, sd,  in stdi2dv_timings()
1446 		__func__, stdi->lcvs, stdi->lcf, stdi->bl,  in stdi2dv_timings()
1447 		stdi->hs_pol, stdi->vs_pol);  in stdi2dv_timings()
1448 	return -1;  in stdi2dv_timings()
1451 static int read_stdi(struct v4l2_subdev *sd, struct stdi_readback *stdi)  in read_stdi()  argument
1455 	adv7842_g_input_status(sd, &status);  in read_stdi()
1457 		v4l2_dbg(2, debug, sd, "%s: no signal\n", __func__);  in read_stdi()
1458 		return -ENOLINK;  in read_stdi()
1461 	stdi->bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);  in read_stdi()
1462 	stdi->lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);  in read_stdi()
1463 	stdi->lcvs = cp_read(sd, 0xb3) >> 3;  in read_stdi()
1465 	if ((cp_read(sd, 0xb5) & 0x80) && ((cp_read(sd, 0xb5) & 0x03) == 0x01)) {  in read_stdi()
1466 		stdi->hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?  in read_stdi()
1467 			((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');  in read_stdi()
1468 		stdi->vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?  in read_stdi()
1469 			((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');  in read_stdi()
1471 		stdi->hs_pol = 'x';  in read_stdi()
1472 		stdi->vs_pol = 'x';  in read_stdi()
1474 	stdi->interlaced = (cp_read(sd, 0xb1) & 0x40) ? true : false;  in read_stdi()
1476 	if (stdi->lcf < 239 || stdi->bl < 8 || stdi->bl == 0x3fff) {  in read_stdi()
1477 		v4l2_dbg(2, debug, sd, "%s: invalid signal\n", __func__);  in read_stdi()
1478 		return -ENOLINK;  in read_stdi()
1481 	v4l2_dbg(2, debug, sd,  in read_stdi()
1482 		"%s: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, %chsync, %cvsync, %s\n",  in read_stdi()
1483 		 __func__, stdi->lcf, stdi->bl, stdi->lcvs,  in read_stdi()
1484 		 stdi->hs_pol, stdi->vs_pol,  in read_stdi()
1485 		 stdi->interlaced ? "interlaced" : "progressive");  in read_stdi()
1490 static int adv7842_enum_dv_timings(struct v4l2_subdev *sd,  in adv7842_enum_dv_timings()  argument
1493 	if (timings->pad != 0)  in adv7842_enum_dv_timings()
1494 		return -EINVAL;  in adv7842_enum_dv_timings()
1497 		adv7842_get_dv_timings_cap(sd), adv7842_check_dv_timings, NULL);  in adv7842_enum_dv_timings()
1500 static int adv7842_dv_timings_cap(struct v4l2_subdev *sd,  in adv7842_dv_timings_cap()  argument
1503 	if (cap->pad != 0)  in adv7842_dv_timings_cap()
1504 		return -EINVAL;  in adv7842_dv_timings_cap()
1506 	*cap = *adv7842_get_dv_timings_cap(sd);  in adv7842_dv_timings_cap()
1512 static void adv7842_fill_optional_dv_timings_fields(struct v4l2_subdev *sd,  in adv7842_fill_optional_dv_timings_fields()  argument
1515 	v4l2_find_dv_timings_cap(timings, adv7842_get_dv_timings_cap(sd),  in adv7842_fill_optional_dv_timings_fields()
1516 			is_digital_input(sd) ? 250000 : 1000000,  in adv7842_fill_optional_dv_timings_fields()
1518 	timings->bt.flags |= V4L2_DV_FL_CAN_DETECT_REDUCED_FPS;  in adv7842_fill_optional_dv_timings_fields()
1521 static int adv7842_query_dv_timings(struct v4l2_subdev *sd, unsigned int pad,  in adv7842_query_dv_timings()  argument
1524 	struct adv7842_state *state = to_state(sd);  in adv7842_query_dv_timings()
1525 	struct v4l2_bt_timings *bt = &timings->bt;  in adv7842_query_dv_timings()
1528 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);  in adv7842_query_dv_timings()
1531 		return -EINVAL;  in adv7842_query_dv_timings()
1536 	if (state->mode == ADV7842_MODE_SDP)  in adv7842_query_dv_timings()
1537 		return -ENODATA;  in adv7842_query_dv_timings()
1540 	if (read_stdi(sd, &stdi)) {  in adv7842_query_dv_timings()
1541 		state->restart_stdi_once = true;  in adv7842_query_dv_timings()
1542 		v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);  in adv7842_query_dv_timings()
1543 		return -ENOLINK;  in adv7842_query_dv_timings()
1545 	bt->interlaced = stdi.interlaced ?  in adv7842_query_dv_timings()
1547 	bt->standards = V4L2_DV_BT_STD_CEA861 | V4L2_DV_BT_STD_DMT |  in adv7842_query_dv_timings()
1550 	if (is_digital_input(sd)) {  in adv7842_query_dv_timings()
1553 		timings->type = V4L2_DV_BT_656_1120;  in adv7842_query_dv_timings()
1555 		bt->width = (hdmi_read(sd, 0x07) & 0x0f) * 256 + hdmi_read(sd, 0x08);  in adv7842_query_dv_timings()
1556 		bt->height = (hdmi_read(sd, 0x09) & 0x0f) * 256 + hdmi_read(sd, 0x0a);  in adv7842_query_dv_timings()
1557 		freq = ((hdmi_read(sd, 0x51) << 1) + (hdmi_read(sd, 0x52) >> 7)) * 1000000;  in adv7842_query_dv_timings()
1558 		freq += ((hdmi_read(sd, 0x52) & 0x7f) * 7813);  in adv7842_query_dv_timings()
1559 		if (is_hdmi(sd)) {  in adv7842_query_dv_timings()
1561 			freq = freq * 8 / (((hdmi_read(sd, 0x0b) & 0xc0) >> 6) * 2 + 8);  in adv7842_query_dv_timings()
1563 		bt->pixelclock = freq;  in adv7842_query_dv_timings()
1564 		bt->hfrontporch = (hdmi_read(sd, 0x20) & 0x03) * 256 +  in adv7842_query_dv_timings()
1565 			hdmi_read(sd, 0x21);  in adv7842_query_dv_timings()
1566 		bt->hsync = (hdmi_read(sd, 0x22) & 0x03) * 256 +  in adv7842_query_dv_timings()
1567 			hdmi_read(sd, 0x23);  in adv7842_query_dv_timings()
1568 		bt->hbackporch = (hdmi_read(sd, 0x24) & 0x03) * 256 +  in adv7842_query_dv_timings()
1569 			hdmi_read(sd, 0x25);  in adv7842_query_dv_timings()
1570 		bt->vfrontporch = ((hdmi_read(sd, 0x2a) & 0x1f) * 256 +  in adv7842_query_dv_timings()
1571 			hdmi_read(sd, 0x2b)) / 2;  in adv7842_query_dv_timings()
1572 		bt->vsync = ((hdmi_read(sd, 0x2e) & 0x1f) * 256 +  in adv7842_query_dv_timings()
1573 			hdmi_read(sd, 0x2f)) / 2;  in adv7842_query_dv_timings()
1574 		bt->vbackporch = ((hdmi_read(sd, 0x32) & 0x1f) * 256 +  in adv7842_query_dv_timings()
1575 			hdmi_read(sd, 0x33)) / 2;  in adv7842_query_dv_timings()
1576 		bt->polarities = ((hdmi_read(sd, 0x05) & 0x10) ? V4L2_DV_VSYNC_POS_POL : 0) |  in adv7842_query_dv_timings()
1577 			((hdmi_read(sd, 0x05) & 0x20) ? V4L2_DV_HSYNC_POS_POL : 0);  in adv7842_query_dv_timings()
1578 		if (bt->interlaced == V4L2_DV_INTERLACED) {  in adv7842_query_dv_timings()
1579 			bt->height += (hdmi_read(sd, 0x0b) & 0x0f) * 256 +  in adv7842_query_dv_timings()
1580 					hdmi_read(sd, 0x0c);  in adv7842_query_dv_timings()
1581 			bt->il_vfrontporch = ((hdmi_read(sd, 0x2c) & 0x1f) * 256 +  in adv7842_query_dv_timings()
1582 					hdmi_read(sd, 0x2d)) / 2;  in adv7842_query_dv_timings()
1583 			bt->il_vsync = ((hdmi_read(sd, 0x30) & 0x1f) * 256 +  in adv7842_query_dv_timings()
1584 					hdmi_read(sd, 0x31)) / 2;  in adv7842_query_dv_timings()
1585 			bt->il_vbackporch = ((hdmi_read(sd, 0x34) & 0x1f) * 256 +  in adv7842_query_dv_timings()
1586 					hdmi_read(sd, 0x35)) / 2;  in adv7842_query_dv_timings()
1588 			bt->il_vfrontporch = 0;  in adv7842_query_dv_timings()
1589 			bt->il_vsync = 0;  in adv7842_query_dv_timings()
1590 			bt->il_vbackporch = 0;  in adv7842_query_dv_timings()
1592 		adv7842_fill_optional_dv_timings_fields(sd, timings);  in adv7842_query_dv_timings()
1593 		if ((timings->bt.flags & V4L2_DV_FL_CAN_REDUCE_FPS) &&  in adv7842_query_dv_timings()
1594 		    freq < bt->pixelclock) {  in adv7842_query_dv_timings()
1595 			u32 reduced_freq = ((u32)bt->pixelclock / 1001) * 1000;  in adv7842_query_dv_timings()
1596 			u32 delta_freq = abs(freq - reduced_freq);  in adv7842_query_dv_timings()
1598 			if (delta_freq < ((u32)bt->pixelclock - reduced_freq) / 2)  in adv7842_query_dv_timings()
1599 				timings->bt.flags |= V4L2_DV_FL_REDUCED_FPS;  in adv7842_query_dv_timings()
1603 		 * Since LCVS values are inaccurate [REF_03, p. 339-340],  in adv7842_query_dv_timings()
1604 		 * stdi2dv_timings() is called with lcvs +-1 if the first attempt fails.  in adv7842_query_dv_timings()
1606 		if (!stdi2dv_timings(sd, &stdi, timings))  in adv7842_query_dv_timings()
1608 		stdi.lcvs += 1;  in adv7842_query_dv_timings()
1609 		v4l2_dbg(1, debug, sd, "%s: lcvs + 1 = %d\n", __func__, stdi.lcvs);  in adv7842_query_dv_timings()
1610 		if (!stdi2dv_timings(sd, &stdi, timings))  in adv7842_query_dv_timings()
1612 		stdi.lcvs -= 2;  in adv7842_query_dv_timings()
1613 		v4l2_dbg(1, debug, sd, "%s: lcvs - 1 = %d\n", __func__, stdi.lcvs);  in adv7842_query_dv_timings()
1614 		if (stdi2dv_timings(sd, &stdi, timings)) {  in adv7842_query_dv_timings()
1624 			if (state->restart_stdi_once) {  in adv7842_query_dv_timings()
1625 				v4l2_dbg(1, debug, sd, "%s: restart STDI\n", __func__);  in adv7842_query_dv_timings()
1627 				/* enter one-shot mode */  in adv7842_query_dv_timings()
1628 				cp_write_and_or(sd, 0x86, 0xf9, 0x00);  in adv7842_query_dv_timings()
1630 				cp_write_and_or(sd, 0x86, 0xf9, 0x04);  in adv7842_query_dv_timings()
1632 				cp_write_and_or(sd, 0x86, 0xf9, 0x02);  in adv7842_query_dv_timings()
1633 				state->restart_stdi_once = false;  in adv7842_query_dv_timings()
1634 				return -ENOLINK;  in adv7842_query_dv_timings()
1636 			v4l2_dbg(1, debug, sd, "%s: format not supported\n", __func__);  in adv7842_query_dv_timings()
1637 			return -ERANGE;  in adv7842_query_dv_timings()
1639 		state->restart_stdi_once = true;  in adv7842_query_dv_timings()
1643 	if (debug > 1)  in adv7842_query_dv_timings()
1644 		v4l2_print_dv_timings(sd->name, "adv7842_query_dv_timings:",  in adv7842_query_dv_timings()
1649 static int adv7842_s_dv_timings(struct v4l2_subdev *sd, unsigned int pad,  in adv7842_s_dv_timings()  argument
1652 	struct adv7842_state *state = to_state(sd);  in adv7842_s_dv_timings()
1656 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);  in adv7842_s_dv_timings()
1659 		return -EINVAL;  in adv7842_s_dv_timings()
1661 	if (state->mode == ADV7842_MODE_SDP)  in adv7842_s_dv_timings()
1662 		return -ENODATA;  in adv7842_s_dv_timings()
1664 	if (v4l2_match_dv_timings(&state->timings, timings, 0, false)) {  in adv7842_s_dv_timings()
1665 		v4l2_dbg(1, debug, sd, "%s: no change\n", __func__);  in adv7842_s_dv_timings()
1669 	bt = &timings->bt;  in adv7842_s_dv_timings()
1671 	if (!v4l2_valid_dv_timings(timings, adv7842_get_dv_timings_cap(sd),  in adv7842_s_dv_timings()
1673 		return -ERANGE;  in adv7842_s_dv_timings()
1675 	adv7842_fill_optional_dv_timings_fields(sd, timings);  in adv7842_s_dv_timings()
1677 	state->timings = *timings;  in adv7842_s_dv_timings()
1679 	cp_write(sd, 0x91, bt->interlaced ? 0x40 : 0x00);  in adv7842_s_dv_timings()
1682 	err = configure_predefined_video_timings(sd, timings);  in adv7842_s_dv_timings()
1686 		configure_custom_video_timings(sd, bt);  in adv7842_s_dv_timings()
1689 	set_rgb_quantization_range(sd);  in adv7842_s_dv_timings()
1692 	if (debug > 1)  in adv7842_s_dv_timings()
1693 		v4l2_print_dv_timings(sd->name, "adv7842_s_dv_timings: ",  in adv7842_s_dv_timings()
1698 static int adv7842_g_dv_timings(struct v4l2_subdev *sd, unsigned int pad,  in adv7842_g_dv_timings()  argument
1701 	struct adv7842_state *state = to_state(sd);  in adv7842_g_dv_timings()
1704 		return -EINVAL;  in adv7842_g_dv_timings()
1706 	if (state->mode == ADV7842_MODE_SDP)  in adv7842_g_dv_timings()
1707 		return -ENODATA;  in adv7842_g_dv_timings()
1708 	*timings = state->timings;  in adv7842_g_dv_timings()
1712 static void enable_input(struct v4l2_subdev *sd)  in enable_input()  argument
1714 	struct adv7842_state *state = to_state(sd);  in enable_input()
1716 	set_rgb_quantization_range(sd);  in enable_input()
1717 	switch (state->mode) {  in enable_input()
1721 		io_write(sd, 0x15, 0xb0);   /* Disable Tristate of Pins (no audio) */  in enable_input()
1724 		hdmi_write(sd, 0x01, 0x00); /* Enable HDMI clock terminators */  in enable_input()
1725 		io_write(sd, 0x15, 0xa0);   /* Disable Tristate of Pins */  in enable_input()
1726 		hdmi_write_and_or(sd, 0x1a, 0xef, 0x00); /* Unmute audio */  in enable_input()
1729 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",  in enable_input()
1730 			 __func__, state->mode);  in enable_input()
1735 static void disable_input(struct v4l2_subdev *sd)  in disable_input()  argument
1737 	hdmi_write_and_or(sd, 0x1a, 0xef, 0x10); /* Mute audio [REF_01, c. 2.2.2] */  in disable_input()
1739 	io_write(sd, 0x15, 0xbe);   /* Tristate all outputs from video core */  in disable_input()
1740 	hdmi_write(sd, 0x01, 0x78); /* Disable HDMI clock terminators */  in disable_input()
1743 static void sdp_csc_coeff(struct v4l2_subdev *sd,  in sdp_csc_coeff()  argument
1747 	sdp_io_write_and_or(sd, 0xe0, 0xbf, c->manual ? 0x00 : 0x40);  in sdp_csc_coeff()
1749 	if (!c->manual)  in sdp_csc_coeff()
1753 	sdp_io_write_and_or(sd, 0xe0, 0x7f, c->scaling == 2 ? 0x80 : 0x00);  in sdp_csc_coeff()
1756 	sdp_io_write_and_or(sd, 0xe0, 0xe0, c->A1 >> 8);  in sdp_csc_coeff()
1757 	sdp_io_write(sd, 0xe1, c->A1);  in sdp_csc_coeff()
1758 	sdp_io_write_and_or(sd, 0xe2, 0xe0, c->A2 >> 8);  in sdp_csc_coeff()
1759 	sdp_io_write(sd, 0xe3, c->A2);  in sdp_csc_coeff()
1760 	sdp_io_write_and_or(sd, 0xe4, 0xe0, c->A3 >> 8);  in sdp_csc_coeff()
1761 	sdp_io_write(sd, 0xe5, c->A3);  in sdp_csc_coeff()
1764 	sdp_io_write_and_or(sd, 0xe6, 0x80, c->A4 >> 8);  in sdp_csc_coeff()
1765 	sdp_io_write(sd, 0xe7, c->A4);  in sdp_csc_coeff()
1768 	sdp_io_write_and_or(sd, 0xe8, 0xe0, c->B1 >> 8);  in sdp_csc_coeff()
1769 	sdp_io_write(sd, 0xe9, c->B1);  in sdp_csc_coeff()
1770 	sdp_io_write_and_or(sd, 0xea, 0xe0, c->B2 >> 8);  in sdp_csc_coeff()
1771 	sdp_io_write(sd, 0xeb, c->B2);  in sdp_csc_coeff()
1772 	sdp_io_write_and_or(sd, 0xec, 0xe0, c->B3 >> 8);  in sdp_csc_coeff()
1773 	sdp_io_write(sd, 0xed, c->B3);  in sdp_csc_coeff()
1776 	sdp_io_write_and_or(sd, 0xee, 0x80, c->B4 >> 8);  in sdp_csc_coeff()
1777 	sdp_io_write(sd, 0xef, c->B4);  in sdp_csc_coeff()
1780 	sdp_io_write_and_or(sd, 0xf0, 0xe0, c->C1 >> 8);  in sdp_csc_coeff()
1781 	sdp_io_write(sd, 0xf1, c->C1);  in sdp_csc_coeff()
1782 	sdp_io_write_and_or(sd, 0xf2, 0xe0, c->C2 >> 8);  in sdp_csc_coeff()
1783 	sdp_io_write(sd, 0xf3, c->C2);  in sdp_csc_coeff()
1784 	sdp_io_write_and_or(sd, 0xf4, 0xe0, c->C3 >> 8);  in sdp_csc_coeff()
1785 	sdp_io_write(sd, 0xf5, c->C3);  in sdp_csc_coeff()
1788 	sdp_io_write_and_or(sd, 0xf6, 0x80, c->C4 >> 8);  in sdp_csc_coeff()
1789 	sdp_io_write(sd, 0xf7, c->C4);  in sdp_csc_coeff()
1792 static void select_input(struct v4l2_subdev *sd,  in select_input()  argument
1795 	struct adv7842_state *state = to_state(sd);  in select_input()
1797 	switch (state->mode) {  in select_input()
1799 		io_write(sd, 0x00, vid_std_select); /* video std: CVBS or YC mode */  in select_input()
1800 		io_write(sd, 0x01, 0); /* prim mode */  in select_input()
1802 		cp_write_and_or(sd, 0x81, 0xef, 0x10);  in select_input()
1804 		afe_write(sd, 0x00, 0x00); /* power up ADC */  in select_input()
1805 		afe_write(sd, 0xc8, 0x00); /* phase control */  in select_input()
1807 		io_write(sd, 0xdd, 0x90); /* Manual 2x output clock */  in select_input()
1811 		afe_write_and_or(sd, 0x02, 0x7f, 0x80);  in select_input()
1813 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/  in select_input()
1814 			afe_write(sd, 0x04, 0x00); /* ADC2 N/C,ADC3 N/C*/  in select_input()
1816 			afe_write(sd, 0x03, 0xa0); /* ADC0 to AIN10 (CVBS), ADC1 N/C*/  in select_input()
1817 			afe_write(sd, 0x04, 0xc0); /* ADC2 to AIN12, ADC3 N/C*/  in select_input()
1819 		afe_write(sd, 0x0c, 0x1f); /* ADI recommend write */  in select_input()
1820 		afe_write(sd, 0x12, 0x63); /* ADI recommend write */  in select_input()
1822 		sdp_io_write(sd, 0xb2, 0x60); /* Disable AV codes */  in select_input()
1823 		sdp_io_write(sd, 0xc8, 0xe3); /* Disable Ancillary data */  in select_input()
1826 		sdp_write(sd, 0x00, 0x3F); /* Autodetect PAL NTSC (not SECAM) */  in select_input()
1827 		sdp_write(sd, 0x01, 0x00); /* Pedestal Off */  in select_input()
1829 		sdp_write(sd, 0x03, 0xE4); /* Manual VCR Gain Luma 0x40B */  in select_input()
1830 		sdp_write(sd, 0x04, 0x0B); /* Manual Luma setting */  in select_input()
1831 		sdp_write(sd, 0x05, 0xC3); /* Manual Chroma setting 0x3FE */  in select_input()
1832 		sdp_write(sd, 0x06, 0xFE); /* Manual Chroma setting */  in select_input()
1833 		sdp_write(sd, 0x12, 0x0D); /* Frame TBC,I_P, 3D comb enabled */  in select_input()
1834 		sdp_write(sd, 0xA7, 0x00); /* ADI Recommended Write */  in select_input()
1835 		sdp_io_write(sd, 0xB0, 0x00); /* Disable H and v blanking */  in select_input()
1838 		sdp_write_and_or(sd, 0x12, 0xf6, 0x09);  in select_input()
1845 		afe_write_and_or(sd, 0x02, 0x7f, 0x00);  in select_input()
1847 		io_write(sd, 0x00, vid_std_select); /* video std */  in select_input()
1848 		io_write(sd, 0x01, 0x02); /* prim mode */  in select_input()
1849 		cp_write_and_or(sd, 0x81, 0xef, 0x10); /* enable embedded syncs  in select_input()
1852 		afe_write(sd, 0x00, 0x00); /* power up ADC */  in select_input()
1853 		afe_write(sd, 0xc8, 0x00); /* phase control */  in select_input()
1854 		if (state->mode == ADV7842_MODE_COMP) {  in select_input()
1856 			io_write_and_or(sd, 0x02, 0x0f, 0x60);  in select_input()
1859 			io_write_and_or(sd, 0x02, 0x0f, 0x10);  in select_input()
1865 		afe_write(sd, 0x0c, 0x1f); /* ADC Range improvement */  in select_input()
1866 		afe_write(sd, 0x12, 0x63); /* ADC Range improvement */  in select_input()
1869 		cp_write(sd, 0x73, 0x10);  in select_input()
1870 		cp_write(sd, 0x74, 0x04);  in select_input()
1871 		cp_write(sd, 0x75, 0x01);  in select_input()
1872 		cp_write(sd, 0x76, 0x00);  in select_input()
1874 		cp_write(sd, 0x3e, 0x04); /* CP core pre-gain control */  in select_input()
1875 		cp_write(sd, 0xc3, 0x39); /* CP coast control. Graphics mode */  in select_input()
1876 		cp_write(sd, 0x40, 0x5c); /* CP core pre-gain control. Graphics mode */  in select_input()
1881 		afe_write_and_or(sd, 0x02, 0x7f, 0x00);  in select_input()
1883 		if (state->hdmi_port_a)  in select_input()
1884 			hdmi_write(sd, 0x00, 0x02); /* select port A */  in select_input()
1886 			hdmi_write(sd, 0x00, 0x03); /* select port B */  in select_input()
1887 		io_write(sd, 0x00, vid_std_select); /* video std */  in select_input()
1888 		io_write(sd, 0x01, 5); /* prim mode */  in select_input()
1889 		cp_write_and_or(sd, 0x81, 0xef, 0x00); /* disable embedded syncs  in select_input()
1895 		hdmi_write(sd, 0xc0, 0x00);  in select_input()
1896 		hdmi_write(sd, 0x0d, 0x34); /* ADI recommended write */  in select_input()
1897 		hdmi_write(sd, 0x3d, 0x10); /* ADI recommended write */  in select_input()
1898 		hdmi_write(sd, 0x44, 0x85); /* TMDS PLL optimization */  in select_input()
1899 		hdmi_write(sd, 0x46, 0x1f); /* ADI recommended write */  in select_input()
1900 		hdmi_write(sd, 0x57, 0xb6); /* TMDS PLL optimization */  in select_input()
1901 		hdmi_write(sd, 0x58, 0x03); /* TMDS PLL optimization */  in select_input()
1902 		hdmi_write(sd, 0x60, 0x88); /* TMDS PLL optimization */  in select_input()
1903 		hdmi_write(sd, 0x61, 0x88); /* TMDS PLL optimization */  in select_input()
1904 		hdmi_write(sd, 0x6c, 0x18); /* Disable ISRC clearing bit,  in select_input()
1906 		hdmi_write(sd, 0x75, 0x10); /* DDC drive strength */  in select_input()
1907 		hdmi_write(sd, 0x85, 0x1f); /* equaliser */  in select_input()
1908 		hdmi_write(sd, 0x87, 0x70); /* ADI recommended write */  in select_input()
1909 		hdmi_write(sd, 0x89, 0x04); /* equaliser */  in select_input()
1910 		hdmi_write(sd, 0x8a, 0x1e); /* equaliser */  in select_input()
1911 		hdmi_write(sd, 0x93, 0x04); /* equaliser */  in select_input()
1912 		hdmi_write(sd, 0x94, 0x1e); /* equaliser */  in select_input()
1913 		hdmi_write(sd, 0x99, 0xa1); /* ADI recommended write */  in select_input()
1914 		hdmi_write(sd, 0x9b, 0x09); /* ADI recommended write */  in select_input()
1915 		hdmi_write(sd, 0x9d, 0x02); /* equaliser */  in select_input()
1917 		afe_write(sd, 0x00, 0xff); /* power down ADC */  in select_input()
1918 		afe_write(sd, 0xc8, 0x40); /* phase control */  in select_input()
1921 		cp_write(sd, 0x73, 0x10);  in select_input()
1922 		cp_write(sd, 0x74, 0x04);  in select_input()
1923 		cp_write(sd, 0x75, 0x01);  in select_input()
1924 		cp_write(sd, 0x76, 0x00);  in select_input()
1929 		afe_write(sd, 0x12, 0xfb); /* ADC noise shaping filter controls */  in select_input()
1930 		afe_write(sd, 0x0c, 0x0d); /* CP core gain controls */  in select_input()
1931 		cp_write(sd, 0x3e, 0x00); /* CP core pre-gain control */  in select_input()
1934 		cp_write(sd, 0xc3, 0x33); /* Component mode */  in select_input()
1937 		io_write_and_or(sd, 0x02, 0x0f, 0xf0);  in select_input()
1941 		v4l2_dbg(2, debug, sd, "%s: Unknown mode %d\n",  in select_input()
1942 			 __func__, state->mode);  in select_input()
1947 static int adv7842_s_routing(struct v4l2_subdev *sd,  in adv7842_s_routing()  argument
1950 	struct adv7842_state *state = to_state(sd);  in adv7842_s_routing()
1952 	v4l2_dbg(2, debug, sd, "%s: input %d\n", __func__, input);  in adv7842_s_routing()
1956 		state->mode = ADV7842_MODE_HDMI;  in adv7842_s_routing()
1957 		state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;  in adv7842_s_routing()
1958 		state->hdmi_port_a = true;  in adv7842_s_routing()
1961 		state->mode = ADV7842_MODE_HDMI;  in adv7842_s_routing()
1962 		state->vid_std_select = ADV7842_HDMI_COMP_VID_STD_HD_1250P;  in adv7842_s_routing()
1963 		state->hdmi_port_a = false;  in adv7842_s_routing()
1966 		state->mode = ADV7842_MODE_COMP;  in adv7842_s_routing()
1967 		state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;  in adv7842_s_routing()
1970 		state->mode = ADV7842_MODE_RGB;  in adv7842_s_routing()
1971 		state->vid_std_select = ADV7842_RGB_VID_STD_AUTO_GRAPH_MODE;  in adv7842_s_routing()
1974 		state->mode = ADV7842_MODE_SDP;  in adv7842_s_routing()
1975 		state->vid_std_select = ADV7842_SDP_VID_STD_CVBS_SD_4x1;  in adv7842_s_routing()
1978 		state->mode = ADV7842_MODE_SDP;  in adv7842_s_routing()
1979 		state->vid_std_select = ADV7842_SDP_VID_STD_YC_SD4_x1;  in adv7842_s_routing()
1982 		return -EINVAL;  in adv7842_s_routing()
1985 	disable_input(sd);  in adv7842_s_routing()
1986 	select_input(sd, state->vid_std_select);  in adv7842_s_routing()
1987 	enable_input(sd);  in adv7842_s_routing()
1989 	v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);  in adv7842_s_routing()
1994 static int adv7842_enum_mbus_code(struct v4l2_subdev *sd,  in adv7842_enum_mbus_code()  argument
1998 	if (code->index >= ARRAY_SIZE(adv7842_formats))  in adv7842_enum_mbus_code()
1999 		return -EINVAL;  in adv7842_enum_mbus_code()
2000 	code->code = adv7842_formats[code->index].code;  in adv7842_enum_mbus_code()
2009 	format->width = state->timings.bt.width;  in adv7842_fill_format()
2010 	format->height = state->timings.bt.height;  in adv7842_fill_format()
2011 	format->field = V4L2_FIELD_NONE;  in adv7842_fill_format()
2012 	format->colorspace = V4L2_COLORSPACE_SRGB;  in adv7842_fill_format()
2014 	if (state->timings.bt.flags & V4L2_DV_FL_IS_CE_VIDEO)  in adv7842_fill_format()
2015 		format->colorspace = (state->timings.bt.height <= 576) ?  in adv7842_fill_format()
2028  *           |	GBR(0)	GRB(1)	BGR(2)	RGB(3)	BRG(4)	RBG(5)
2029  * ----------+-------------------------------------------------
2031  * GRB (1-2) |	BGR	RGB	GBR	GRB	RBG	BRG
2032  * RBG (2-3) |	GRB	GBR	BRG	RBG	BGR	RGB
2033  * BGR (1-3) |	RBG	BRG	RGB	BGR	GRB	GBR
2046 		_BUS(GRB) /* 1-2 */ = _SEL(BGR, RGB, GBR, GRB, RBG, BRG),  in adv7842_op_ch_sel()
2047 		_BUS(RBG) /* 2-3 */ = _SEL(GRB, GBR, BRG, RBG, BGR, RGB),  in adv7842_op_ch_sel()
2048 		_BUS(BGR) /* 1-3 */ = _SEL(RBG, BRG, RGB, BGR, GRB, GBR),  in adv7842_op_ch_sel()
2053 	return op_ch_sel[state->pdata.bus_order][state->format->op_ch_sel >> 5];  in adv7842_op_ch_sel()
2058 	struct v4l2_subdev *sd = &state->sd;  in adv7842_setup_format()  local
2060 	io_write_clr_set(sd, 0x02, 0x02,  in adv7842_setup_format()
2061 			state->format->rgb_out ? ADV7842_RGB_OUT : 0);  in adv7842_setup_format()
2062 	io_write(sd, 0x03, state->format->op_format_sel |  in adv7842_setup_format()
2063 		 state->pdata.op_format_mode_sel);  in adv7842_setup_format()
2064 	io_write_clr_set(sd, 0x04, 0xe0, adv7842_op_ch_sel(state));  in adv7842_setup_format()
2065 	io_write_clr_set(sd, 0x05, 0x01,  in adv7842_setup_format()
2066 			state->format->swap_cb_cr ? ADV7842_OP_SWAP_CB_CR : 0);  in adv7842_setup_format()
2067 	set_rgb_quantization_range(sd);  in adv7842_setup_format()
2070 static int adv7842_get_format(struct v4l2_subdev *sd,  in adv7842_get_format()  argument
2074 	struct adv7842_state *state = to_state(sd);  in adv7842_get_format()
2076 	if (format->pad != ADV7842_PAD_SOURCE)  in adv7842_get_format()
2077 		return -EINVAL;  in adv7842_get_format()
2079 	if (state->mode == ADV7842_MODE_SDP) {  in adv7842_get_format()
2081 		if (!(sdp_read(sd, 0x5a) & 0x01))  in adv7842_get_format()
2082 			return -EINVAL;  in adv7842_get_format()
2083 		format->format.code = MEDIA_BUS_FMT_YUYV8_2X8;  in adv7842_get_format()
2084 		format->format.width = 720;  in adv7842_get_format()
2086 		if (state->norm & V4L2_STD_525_60)  in adv7842_get_format()
2087 			format->format.height = 480;  in adv7842_get_format()
2089 			format->format.height = 576;  in adv7842_get_format()
2090 		format->format.colorspace = V4L2_COLORSPACE_SMPTE170M;  in adv7842_get_format()
2094 	adv7842_fill_format(state, &format->format);  in adv7842_get_format()
2096 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {  in adv7842_get_format()
2099 		fmt = v4l2_subdev_state_get_format(sd_state, format->pad);  in adv7842_get_format()
2100 		format->format.code = fmt->code;  in adv7842_get_format()
2102 		format->format.code = state->format->code;  in adv7842_get_format()
2108 static int adv7842_set_format(struct v4l2_subdev *sd,  in adv7842_set_format()  argument
2112 	struct adv7842_state *state = to_state(sd);  in adv7842_set_format()
2115 	if (format->pad != ADV7842_PAD_SOURCE)  in adv7842_set_format()
2116 		return -EINVAL;  in adv7842_set_format()
2118 	if (state->mode == ADV7842_MODE_SDP)  in adv7842_set_format()
2119 		return adv7842_get_format(sd, sd_state, format);  in adv7842_set_format()
2121 	info = adv7842_format_info(state, format->format.code);  in adv7842_set_format()
2125 	adv7842_fill_format(state, &format->format);  in adv7842_set_format()
2126 	format->format.code = info->code;  in adv7842_set_format()
2128 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {  in adv7842_set_format()
2131 		fmt = v4l2_subdev_state_get_format(sd_state, format->pad);  in adv7842_set_format()
2132 		fmt->code = format->format.code;  in adv7842_set_format()
2134 		state->format = info;  in adv7842_set_format()
2141 static void adv7842_irq_enable(struct v4l2_subdev *sd, bool enable)  in adv7842_irq_enable()  argument
2145 		io_write(sd, 0x46, 0x9c);  in adv7842_irq_enable()
2147 		io_write(sd, 0x5a, 0x10);  in adv7842_irq_enable()
2149 		io_write(sd, 0x73, 0x03);  in adv7842_irq_enable()
2151 		io_write(sd, 0x78, 0x03);  in adv7842_irq_enable()
2153 		io_write(sd, 0xa0, 0x09);  in adv7842_irq_enable()
2155 		io_write(sd, 0x69, 0x08);  in adv7842_irq_enable()
2157 		io_write(sd, 0x46, 0x0);  in adv7842_irq_enable()
2158 		io_write(sd, 0x5a, 0x0);  in adv7842_irq_enable()
2159 		io_write(sd, 0x73, 0x0);  in adv7842_irq_enable()
2160 		io_write(sd, 0x78, 0x0);  in adv7842_irq_enable()
2161 		io_write(sd, 0xa0, 0x0);  in adv7842_irq_enable()
2162 		io_write(sd, 0x69, 0x0);  in adv7842_irq_enable()
2167 static void adv7842_cec_tx_raw_status(struct v4l2_subdev *sd, u8 tx_raw_status)  in adv7842_cec_tx_raw_status()  argument
2169 	struct adv7842_state *state = to_state(sd);  in adv7842_cec_tx_raw_status()
2171 	if ((cec_read(sd, 0x11) & 0x01) == 0) {  in adv7842_cec_tx_raw_status()
2172 		v4l2_dbg(1, debug, sd, "%s: tx raw: tx disabled\n", __func__);  in adv7842_cec_tx_raw_status()
2177 		v4l2_dbg(1, debug, sd, "%s: tx raw: arbitration lost\n",  in adv7842_cec_tx_raw_status()
2179 		cec_transmit_done(state->cec_adap, CEC_TX_STATUS_ARB_LOST,  in adv7842_cec_tx_raw_status()
2180 				  1, 0, 0, 0);  in adv7842_cec_tx_raw_status()
2188 		v4l2_dbg(1, debug, sd, "%s: tx raw: retry failed\n", __func__);  in adv7842_cec_tx_raw_status()
2194 		nack_cnt = cec_read(sd, 0x14) & 0xf;  in adv7842_cec_tx_raw_status()
2197 		low_drive_cnt = cec_read(sd, 0x14) >> 4;  in adv7842_cec_tx_raw_status()
2200 		cec_transmit_done(state->cec_adap, status,  in adv7842_cec_tx_raw_status()
2205 		v4l2_dbg(1, debug, sd, "%s: tx raw: ready ok\n", __func__);  in adv7842_cec_tx_raw_status()
2206 		cec_transmit_done(state->cec_adap, CEC_TX_STATUS_OK, 0, 0, 0, 0);  in adv7842_cec_tx_raw_status()
2211 static void adv7842_cec_isr(struct v4l2_subdev *sd, bool *handled)  in adv7842_cec_isr()  argument
2216 	cec_irq = io_read(sd, 0x93) & 0x0f;  in adv7842_cec_isr()
2220 	v4l2_dbg(1, debug, sd, "%s: cec: irq 0x%x\n", __func__, cec_irq);  in adv7842_cec_isr()
2221 	adv7842_cec_tx_raw_status(sd, cec_irq);  in adv7842_cec_isr()
2223 		struct adv7842_state *state = to_state(sd);  in adv7842_cec_isr()
2226 		msg.len = cec_read(sd, 0x25) & 0x1f;  in adv7842_cec_isr()
2234 				msg.msg[i] = cec_read(sd, i + 0x15);  in adv7842_cec_isr()
2235 			cec_write(sd, 0x26, 0x01); /* re-enable rx */  in adv7842_cec_isr()
2236 			cec_received_msg(state->cec_adap, &msg);  in adv7842_cec_isr()
2240 	io_write(sd, 0x94, cec_irq);  in adv7842_cec_isr()
2249 	struct v4l2_subdev *sd = &state->sd;  in adv7842_cec_adap_enable()  local
2251 	if (!state->cec_enabled_adap && enable) {  in adv7842_cec_adap_enable()
2252 		cec_write_clr_set(sd, 0x2a, 0x01, 0x01); /* power up cec */  in adv7842_cec_adap_enable()
2253 		cec_write(sd, 0x2c, 0x01);	/* cec soft reset */  in adv7842_cec_adap_enable()
2254 		cec_write_clr_set(sd, 0x11, 0x01, 0); /* initially disable tx */  in adv7842_cec_adap_enable()
2260 		io_write_clr_set(sd, 0x96, 0x0f, 0x0f);  in adv7842_cec_adap_enable()
2261 		cec_write(sd, 0x26, 0x01);            /* enable rx */  in adv7842_cec_adap_enable()
2262 	} else if (state->cec_enabled_adap && !enable) {  in adv7842_cec_adap_enable()
2264 		io_write_clr_set(sd, 0x96, 0x0f, 0x00);  in adv7842_cec_adap_enable()
2265 		/* disable address mask 1-3 */  in adv7842_cec_adap_enable()
2266 		cec_write_clr_set(sd, 0x27, 0x70, 0x00);  in adv7842_cec_adap_enable()
2268 		cec_write_clr_set(sd, 0x2a, 0x01, 0x00);  in adv7842_cec_adap_enable()
2269 		state->cec_valid_addrs = 0;  in adv7842_cec_adap_enable()
2271 	state->cec_enabled_adap = enable;  in adv7842_cec_adap_enable()
2278 	struct v4l2_subdev *sd = &state->sd;  in adv7842_cec_adap_log_addr()  local
2281 	if (!state->cec_enabled_adap)  in adv7842_cec_adap_log_addr()
2282 		return addr == CEC_LOG_ADDR_INVALID ? 0 : -EIO;  in adv7842_cec_adap_log_addr()
2285 		cec_write_clr_set(sd, 0x27, 0x70, 0);  in adv7842_cec_adap_log_addr()
2286 		state->cec_valid_addrs = 0;  in adv7842_cec_adap_log_addr()
2291 		bool is_valid = state->cec_valid_addrs & (1 << i);  in adv7842_cec_adap_log_addr()
2295 		if (is_valid && state->cec_addr[i] == addr)  in adv7842_cec_adap_log_addr()
2301 			return -ENXIO;  in adv7842_cec_adap_log_addr()
2303 	state->cec_addr[i] = addr;  in adv7842_cec_adap_log_addr()
2304 	state->cec_valid_addrs |= 1 << i;  in adv7842_cec_adap_log_addr()
2309 		cec_write_clr_set(sd, 0x27, 0x10, 0x10);  in adv7842_cec_adap_log_addr()
2311 		cec_write_clr_set(sd, 0x28, 0x0f, addr);  in adv7842_cec_adap_log_addr()
2313 	case 1:  in adv7842_cec_adap_log_addr()
2314 		/* enable address mask 1 */  in adv7842_cec_adap_log_addr()
2315 		cec_write_clr_set(sd, 0x27, 0x20, 0x20);  in adv7842_cec_adap_log_addr()
2316 		/* set address for mask 1 */  in adv7842_cec_adap_log_addr()
2317 		cec_write_clr_set(sd, 0x28, 0xf0, addr << 4);  in adv7842_cec_adap_log_addr()
2321 		cec_write_clr_set(sd, 0x27, 0x40, 0x40);  in adv7842_cec_adap_log_addr()
2322 		/* set address for mask 1 */  in adv7842_cec_adap_log_addr()
2323 		cec_write_clr_set(sd, 0x29, 0x0f, addr);  in adv7842_cec_adap_log_addr()
2333 	struct v4l2_subdev *sd = &state->sd;  in adv7842_cec_adap_transmit()  local
2334 	u8 len = msg->len;  in adv7842_cec_adap_transmit()
2338 	 * The number of retries is the number of attempts - 1, but retry  in adv7842_cec_adap_transmit()
2342 	cec_write_clr_set(sd, 0x12, 0x70, max(1, attempts - 1) << 4);  in adv7842_cec_adap_transmit()
2345 		v4l2_err(sd, "%s: len exceeded 16 (%d)\n", __func__, len);  in adv7842_cec_adap_transmit()
2346 		return -EINVAL;  in adv7842_cec_adap_transmit()
2351 		cec_write(sd, i, msg->msg[i]);  in adv7842_cec_adap_transmit()
2354 	cec_write(sd, 0x10, len);  in adv7842_cec_adap_transmit()
2356 	cec_write(sd, 0x11, 0x01);  in adv7842_cec_adap_transmit()
2367 static int adv7842_isr(struct v4l2_subdev *sd, u32 status, bool *handled)  in adv7842_isr()  argument
2369 	struct adv7842_state *state = to_state(sd);  in adv7842_isr()
2373 	adv7842_irq_enable(sd, false);  in adv7842_isr()
2376 	irq_status[0] = io_read(sd, 0x43);  in adv7842_isr()
2377 	irq_status[1] = io_read(sd, 0x57);  in adv7842_isr()
2378 	irq_status[2] = io_read(sd, 0x70);  in adv7842_isr()
2379 	irq_status[3] = io_read(sd, 0x75);  in adv7842_isr()
2380 	irq_status[4] = io_read(sd, 0x9d);  in adv7842_isr()
2381 	irq_status[5] = io_read(sd, 0x66);  in adv7842_isr()
2385 		io_write(sd, 0x44, irq_status[0]);  in adv7842_isr()
2386 	if (irq_status[1])  in adv7842_isr()
2387 		io_write(sd, 0x58, irq_status[1]);  in adv7842_isr()
2389 		io_write(sd, 0x71, irq_status[2]);  in adv7842_isr()
2391 		io_write(sd, 0x76, irq_status[3]);  in adv7842_isr()
2393 		io_write(sd, 0x9e, irq_status[4]);  in adv7842_isr()
2395 		io_write(sd, 0x67, irq_status[5]);  in adv7842_isr()
2397 	adv7842_irq_enable(sd, true);  in adv7842_isr()
2399 	v4l2_dbg(1, debug, sd, "%s: irq %x, %x, %x, %x, %x, %x\n", __func__,  in adv7842_isr()
2400 		 irq_status[0], irq_status[1], irq_status[2],  in adv7842_isr()
2407 	if (state->mode == ADV7842_MODE_SDP)  in adv7842_isr()
2408 		fmt_change_sdp = (irq_status[1] & 0x30) | (irq_status[4] & 0x09);  in adv7842_isr()
2413 	if (is_digital_input(sd))  in adv7842_isr()
2420 		v4l2_dbg(1, debug, sd,  in adv7842_isr()
2424 		v4l2_subdev_notify_event(sd, &adv7842_ev_fmt);  in adv7842_isr()
2431 		v4l2_dbg(1, debug, sd, "%s: irq %s mode\n", __func__,  in adv7842_isr()
2432 			 (io_read(sd, 0x65) & 0x08) ? "HDMI" : "DVI");  in adv7842_isr()
2433 		set_rgb_quantization_range(sd);  in adv7842_isr()
2440 	adv7842_cec_isr(sd, handled);  in adv7842_isr()
2445 		v4l2_dbg(1, debug, sd, "%s: irq tx_5v\n", __func__);  in adv7842_isr()
2446 		adv7842_s_detect_tx_5v_ctrl(sd);  in adv7842_isr()
2453 static int adv7842_get_edid(struct v4l2_subdev *sd, struct v4l2_edid *edid)  in adv7842_get_edid()  argument
2455 	struct adv7842_state *state = to_state(sd);  in adv7842_get_edid()
2459 	memset(edid->reserved, 0, sizeof(edid->reserved));  in adv7842_get_edid()
2461 	switch (edid->pad) {  in adv7842_get_edid()
2464 		if (state->hdmi_edid.present & (0x04 << edid->pad)) {  in adv7842_get_edid()
2465 			data = state->hdmi_edid.edid;  in adv7842_get_edid()
2466 			blocks = state->hdmi_edid.blocks;  in adv7842_get_edid()
2470 		if (state->vga_edid.present) {  in adv7842_get_edid()
2471 			data = state->vga_edid.edid;  in adv7842_get_edid()
2472 			blocks = state->vga_edid.blocks;  in adv7842_get_edid()
2476 		return -EINVAL;  in adv7842_get_edid()
2479 	if (edid->start_block == 0 && edid->blocks == 0) {  in adv7842_get_edid()
2480 		edid->blocks = blocks;  in adv7842_get_edid()
2485 		return -ENODATA;  in adv7842_get_edid()
2487 	if (edid->start_block >= blocks)  in adv7842_get_edid()
2488 		return -EINVAL;  in adv7842_get_edid()
2490 	if (edid->start_block + edid->blocks > blocks)  in adv7842_get_edid()
2491 		edid->blocks = blocks - edid->start_block;  in adv7842_get_edid()
2493 	memcpy(edid->edid, data + edid->start_block * 128, edid->blocks * 128);  in adv7842_get_edid()
2501  * of segment 1 (i.e. the third block of the EDID) is for VGA.
2505 static int adv7842_set_edid(struct v4l2_subdev *sd, struct v4l2_edid *e)  in adv7842_set_edid()  argument
2507 	struct adv7842_state *state = to_state(sd);  in adv7842_set_edid()
2508 	unsigned int max_blocks = e->pad == ADV7842_EDID_PORT_VGA ? 1 : 4;  in adv7842_set_edid()
2511 	memset(e->reserved, 0, sizeof(e->reserved));  in adv7842_set_edid()
2513 	if (e->pad > ADV7842_EDID_PORT_VGA)  in adv7842_set_edid()
2514 		return -EINVAL;  in adv7842_set_edid()
2515 	if (e->start_block != 0)  in adv7842_set_edid()
2516 		return -EINVAL;  in adv7842_set_edid()
2517 	if (e->pad < ADV7842_EDID_PORT_VGA && state->vga_edid.blocks)  in adv7842_set_edid()
2519 	if (e->pad == ADV7842_EDID_PORT_VGA && state->hdmi_edid.blocks > 2)  in adv7842_set_edid()
2520 		return -EBUSY;  in adv7842_set_edid()
2521 	if (e->blocks > max_blocks) {  in adv7842_set_edid()
2522 		e->blocks = max_blocks;  in adv7842_set_edid()
2523 		return -E2BIG;  in adv7842_set_edid()
2527 	if (e->blocks)  in adv7842_set_edid()
2528 		state->aspect_ratio = v4l2_calc_aspect_ratio(e->edid[0x15],  in adv7842_set_edid()
2529 							     e->edid[0x16]);  in adv7842_set_edid()
2531 	switch (e->pad) {  in adv7842_set_edid()
2533 		memset(state->vga_edid.edid, 0, sizeof(state->vga_edid.edid));  in adv7842_set_edid()
2534 		state->vga_edid.blocks = e->blocks;  in adv7842_set_edid()
2535 		state->vga_edid.present = e->blocks ? 0x1 : 0x0;  in adv7842_set_edid()
2536 		if (e->blocks)  in adv7842_set_edid()
2537 			memcpy(state->vga_edid.edid, e->edid, 128);  in adv7842_set_edid()
2538 		err = edid_write_vga_segment(sd);  in adv7842_set_edid()
2542 		memset(state->hdmi_edid.edid, 0, sizeof(state->hdmi_edid.edid));  in adv7842_set_edid()
2543 		state->hdmi_edid.blocks = e->blocks;  in adv7842_set_edid()
2544 		if (e->blocks) {  in adv7842_set_edid()
2545 			state->hdmi_edid.present |= 0x04 << e->pad;  in adv7842_set_edid()
2546 			memcpy(state->hdmi_edid.edid, e->edid, 128 * e->blocks);  in adv7842_set_edid()
2548 			state->hdmi_edid.present &= ~(0x04 << e->pad);  in adv7842_set_edid()
2549 			adv7842_s_detect_tx_5v_ctrl(sd);  in adv7842_set_edid()
2551 		err = edid_write_hdmi_segment(sd, e->pad);  in adv7842_set_edid()
2554 		return -EINVAL;  in adv7842_set_edid()
2557 		v4l2_err(sd, "error %d writing edid on port %d\n", err, e->pad);  in adv7842_set_edid()
2568 static void log_infoframe(struct v4l2_subdev *sd, const struct adv7842_cfg_read_infoframe *cri)  in log_infoframe()  argument
2574 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in log_infoframe()
2575 	struct device *dev = &client->dev;  in log_infoframe()
2577 	if (!(io_read(sd, 0x60) & cri->present_mask)) {  in log_infoframe()
2578 		v4l2_info(sd, "%s infoframe not received\n", cri->desc);  in log_infoframe()
2583 		buffer[i] = infoframe_read(sd, cri->head_addr + i);  in log_infoframe()
2585 	len = buffer[2] + 1;  in log_infoframe()
2588 		v4l2_err(sd, "%s: invalid %s infoframe length %d\n", __func__, cri->desc, len);  in log_infoframe()
2593 		buffer[i + 3] = infoframe_read(sd, cri->payload_addr + i);  in log_infoframe()
2596 		v4l2_err(sd, "%s: unpack of %s infoframe failed\n", __func__, cri->desc);  in log_infoframe()
2603 static void adv7842_log_infoframes(struct v4l2_subdev *sd)  in adv7842_log_infoframes()  argument
2613 	if (!(hdmi_read(sd, 0x05) & 0x80)) {  in adv7842_log_infoframes()
2614 		v4l2_info(sd, "receive DVI-D signal, no infoframes\n");  in adv7842_log_infoframes()
2619 		log_infoframe(sd, &cri[i]);  in adv7842_log_infoframes()
2630 	"HDMI-Comp",
2631 	"HDMI-GR",
2644 static int adv7842_sdp_log_status(struct v4l2_subdev *sd)  in adv7842_sdp_log_status()  argument
2647 	u8 sdp_signal_detected = sdp_read(sd, 0x5A) & 0x01;  in adv7842_sdp_log_status()
2649 	v4l2_info(sd, "Chip powered %s\n", no_power(sd) ? "off" : "on");  in adv7842_sdp_log_status()
2650 	v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x\n",  in adv7842_sdp_log_status()
2651 		  io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f);  in adv7842_sdp_log_status()
2653 	v4l2_info(sd, "SDP: free run: %s\n",  in adv7842_sdp_log_status()
2654 		(sdp_read(sd, 0x56) & 0x01) ? "on" : "off");  in adv7842_sdp_log_status()
2655 	v4l2_info(sd, "SDP: %s\n", sdp_signal_detected ?  in adv7842_sdp_log_status()
2656 		"valid SD/PR signal detected" : "invalid/no signal");  in adv7842_sdp_log_status()
2659 			"NTSC-M/J",  in adv7842_sdp_log_status()
2660 			"1?",  in adv7842_sdp_log_status()
2661 			"NTSC-443",  in adv7842_sdp_log_status()
2663 			"PAL-M",  in adv7842_sdp_log_status()
2665 			"PAL-60",  in adv7842_sdp_log_status()
2667 			"PAL-CombN",  in adv7842_sdp_log_status()
2669 			"PAL-BGHID",  in adv7842_sdp_log_status()
2672 		v4l2_info(sd, "SDP: standard %s\n",  in adv7842_sdp_log_status()
2673 			sdp_std_txt[sdp_read(sd, 0x52) & 0x0f]);  in adv7842_sdp_log_status()
2674 		v4l2_info(sd, "SDP: %s\n",  in adv7842_sdp_log_status()
2675 			(sdp_read(sd, 0x59) & 0x08) ? "50Hz" : "60Hz");  in adv7842_sdp_log_status()
2676 		v4l2_info(sd, "SDP: %s\n",  in adv7842_sdp_log_status()
2677 			(sdp_read(sd, 0x57) & 0x08) ? "Interlaced" : "Progressive");  in adv7842_sdp_log_status()
2678 		v4l2_info(sd, "SDP: deinterlacer %s\n",  in adv7842_sdp_log_status()
2679 			(sdp_read(sd, 0x12) & 0x08) ? "enabled" : "disabled");  in adv7842_sdp_log_status()
2680 		v4l2_info(sd, "SDP: csc %s mode\n",  in adv7842_sdp_log_status()
2681 			(sdp_io_read(sd, 0xe0) & 0x40) ? "auto" : "manual");  in adv7842_sdp_log_status()
2686 static int adv7842_cp_log_status(struct v4l2_subdev *sd)  in adv7842_cp_log_status()  argument
2689 	struct adv7842_state *state = to_state(sd);  in adv7842_cp_log_status()
2691 	u8 reg_io_0x02 = io_read(sd, 0x02);  in adv7842_cp_log_status()
2692 	u8 reg_io_0x21 = io_read(sd, 0x21);  in adv7842_cp_log_status()
2693 	u8 reg_rep_0x77 = rep_read(sd, 0x77);  in adv7842_cp_log_status()
2694 	u8 reg_rep_0x7d = rep_read(sd, 0x7d);  in adv7842_cp_log_status()
2695 	bool audio_pll_locked = hdmi_read(sd, 0x04) & 0x01;  in adv7842_cp_log_status()
2696 	bool audio_sample_packet_detect = hdmi_read(sd, 0x18) & 0x01;  in adv7842_cp_log_status()
2697 	bool audio_mute = io_read(sd, 0x65) & 0x40;  in adv7842_cp_log_status()
2700 		"bypassed", "YPbPr601 -> RGB", "reserved", "YPbPr709 -> RGB",  in adv7842_cp_log_status()
2701 		"reserved", "RGB -> YPbPr601", "reserved", "RGB -> YPbPr709",  in adv7842_cp_log_status()
2702 		"reserved", "YPbPr709 -> YPbPr601", "YPbPr601 -> YPbPr709",  in adv7842_cp_log_status()
2706 		"RGB limited range (16-235)", "RGB full range (0-255)",  in adv7842_cp_log_status()
2707 		"YCbCr Bt.601 (16-235)", "YCbCr Bt.709 (16-235)",  in adv7842_cp_log_status()
2709 		"YCbCr Bt.601 (0-255)", "YCbCr Bt.709 (0-255)",  in adv7842_cp_log_status()
2715 		"RGB limited range (16-235)",  in adv7842_cp_log_status()
2716 		"RGB full range (0-255)",  in adv7842_cp_log_status()
2719 		"8-bits per channel",  in adv7842_cp_log_status()
2720 		"10-bits per channel",  in adv7842_cp_log_status()
2721 		"12-bits per channel",  in adv7842_cp_log_status()
2722 		"16-bits per channel (not supported)"  in adv7842_cp_log_status()
2725 	v4l2_info(sd, "-----Chip status-----\n");  in adv7842_cp_log_status()
2726 	v4l2_info(sd, "Chip power: %s\n", no_power(sd) ? "off" : "on");  in adv7842_cp_log_status()
2727 	v4l2_info(sd, "HDMI/DVI-D port selected: %s\n",  in adv7842_cp_log_status()
2728 			state->hdmi_port_a ? "A" : "B");  in adv7842_cp_log_status()
2729 	v4l2_info(sd, "EDID A %s, B %s\n",  in adv7842_cp_log_status()
2734 	v4l2_info(sd, "HPD A %s, B %s\n",  in adv7842_cp_log_status()
2737 	v4l2_info(sd, "CEC: %s\n", state->cec_enabled_adap ?  in adv7842_cp_log_status()
2739 	if (state->cec_enabled_adap) {  in adv7842_cp_log_status()
2743 			bool is_valid = state->cec_valid_addrs & (1 << i);  in adv7842_cp_log_status()
2746 				v4l2_info(sd, "CEC Logical Address: 0x%x\n",  in adv7842_cp_log_status()
2747 					  state->cec_addr[i]);  in adv7842_cp_log_status()
2751 	v4l2_info(sd, "-----Signal status-----\n");  in adv7842_cp_log_status()
2752 	if (state->hdmi_port_a) {  in adv7842_cp_log_status()
2753 		v4l2_info(sd, "Cable detected (+5V power): %s\n",  in adv7842_cp_log_status()
2754 			  io_read(sd, 0x6f) & 0x02 ? "true" : "false");  in adv7842_cp_log_status()
2755 		v4l2_info(sd, "TMDS signal detected: %s\n",  in adv7842_cp_log_status()
2756 			  (io_read(sd, 0x6a) & 0x02) ? "true" : "false");  in adv7842_cp_log_status()
2757 		v4l2_info(sd, "TMDS signal locked: %s\n",  in adv7842_cp_log_status()
2758 			  (io_read(sd, 0x6a) & 0x20) ? "true" : "false");  in adv7842_cp_log_status()
2760 		v4l2_info(sd, "Cable detected (+5V power):%s\n",  in adv7842_cp_log_status()
2761 			  io_read(sd, 0x6f) & 0x01 ? "true" : "false");  in adv7842_cp_log_status()
2762 		v4l2_info(sd, "TMDS signal detected: %s\n",  in adv7842_cp_log_status()
2763 			  (io_read(sd, 0x6a) & 0x01) ? "true" : "false");  in adv7842_cp_log_status()
2764 		v4l2_info(sd, "TMDS signal locked: %s\n",  in adv7842_cp_log_status()
2765 			  (io_read(sd, 0x6a) & 0x10) ? "true" : "false");  in adv7842_cp_log_status()
2767 	v4l2_info(sd, "CP free run: %s\n",  in adv7842_cp_log_status()
2768 		  (!!(cp_read(sd, 0xff) & 0x10) ? "on" : "off"));  in adv7842_cp_log_status()
2769 	v4l2_info(sd, "Prim-mode = 0x%x, video std = 0x%x, v_freq = 0x%x\n",  in adv7842_cp_log_status()
2770 		  io_read(sd, 0x01) & 0x0f, io_read(sd, 0x00) & 0x3f,  in adv7842_cp_log_status()
2771 		  (io_read(sd, 0x01) & 0x70) >> 4);  in adv7842_cp_log_status()
2773 	v4l2_info(sd, "-----Video Timings-----\n");  in adv7842_cp_log_status()
2774 	if (no_cp_signal(sd)) {  in adv7842_cp_log_status()
2775 		v4l2_info(sd, "STDI: not locked\n");  in adv7842_cp_log_status()
2777 		u32 bl = ((cp_read(sd, 0xb1) & 0x3f) << 8) | cp_read(sd, 0xb2);  in adv7842_cp_log_status()
2778 		u32 lcf = ((cp_read(sd, 0xb3) & 0x7) << 8) | cp_read(sd, 0xb4);  in adv7842_cp_log_status()
2779 		u32 lcvs = cp_read(sd, 0xb3) >> 3;  in adv7842_cp_log_status()
2780 		u32 fcl = ((cp_read(sd, 0xb8) & 0x1f) << 8) | cp_read(sd, 0xb9);  in adv7842_cp_log_status()
2781 		char hs_pol = ((cp_read(sd, 0xb5) & 0x10) ?  in adv7842_cp_log_status()
2782 				((cp_read(sd, 0xb5) & 0x08) ? '+' : '-') : 'x');  in adv7842_cp_log_status()
2783 		char vs_pol = ((cp_read(sd, 0xb5) & 0x40) ?  in adv7842_cp_log_status()
2784 				((cp_read(sd, 0xb5) & 0x20) ? '+' : '-') : 'x');  in adv7842_cp_log_status()
2785 		v4l2_info(sd,  in adv7842_cp_log_status()
2786 …	"STDI: lcf (frame height - 1) = %d, bl = %d, lcvs (vsync) = %d, fcl = %d, %s, %chsync, %cvsync\n",  in adv7842_cp_log_status()
2788 			(cp_read(sd, 0xb1) & 0x40) ?  in adv7842_cp_log_status()
2792 	if (adv7842_query_dv_timings(sd, 0, &timings))  in adv7842_cp_log_status()
2793 		v4l2_info(sd, "No video detected\n");  in adv7842_cp_log_status()
2795 		v4l2_print_dv_timings(sd->name, "Detected format: ",  in adv7842_cp_log_status()
2797 	v4l2_print_dv_timings(sd->name, "Configured format: ",  in adv7842_cp_log_status()
2798 			&state->timings, true);  in adv7842_cp_log_status()
2800 	if (no_cp_signal(sd))  in adv7842_cp_log_status()
2803 	v4l2_info(sd, "-----Color space-----\n");  in adv7842_cp_log_status()
2804 	v4l2_info(sd, "RGB quantization range ctrl: %s\n",  in adv7842_cp_log_status()
2805 		  rgb_quantization_range_txt[state->rgb_quantization_range]);  in adv7842_cp_log_status()
2806 	v4l2_info(sd, "Input color space: %s\n",  in adv7842_cp_log_status()
2808 	v4l2_info(sd, "Output color space: %s %s, alt-gamma %s\n",  in adv7842_cp_log_status()
2811 			"(16-235)" : "(0-255)",  in adv7842_cp_log_status()
2813 	v4l2_info(sd, "Color space conversion: %s\n",  in adv7842_cp_log_status()
2814 		  csc_coeff_sel_rb[cp_read(sd, 0xf4) >> 4]);  in adv7842_cp_log_status()
2816 	if (!is_digital_input(sd))  in adv7842_cp_log_status()
2819 	v4l2_info(sd, "-----%s status-----\n", is_hdmi(sd) ? "HDMI" : "DVI-D");  in adv7842_cp_log_status()
2820 	v4l2_info(sd, "HDCP encrypted content: %s\n",  in adv7842_cp_log_status()
2821 			(hdmi_read(sd, 0x05) & 0x40) ? "true" : "false");  in adv7842_cp_log_status()
2822 	v4l2_info(sd, "HDCP keys read: %s%s\n",  in adv7842_cp_log_status()
2823 			(hdmi_read(sd, 0x04) & 0x20) ? "yes" : "no",  in adv7842_cp_log_status()
2824 			(hdmi_read(sd, 0x04) & 0x10) ? "ERROR" : "");  in adv7842_cp_log_status()
2825 	if (!is_hdmi(sd))  in adv7842_cp_log_status()
2828 	v4l2_info(sd, "Audio: pll %s, samples %s, %s\n",  in adv7842_cp_log_status()
2833 		v4l2_info(sd, "Audio format: %s\n",  in adv7842_cp_log_status()
2834 			(hdmi_read(sd, 0x07) & 0x40) ? "multi-channel" : "stereo");  in adv7842_cp_log_status()
2836 	v4l2_info(sd, "Audio CTS: %u\n", (hdmi_read(sd, 0x5b) << 12) +  in adv7842_cp_log_status()
2837 			(hdmi_read(sd, 0x5c) << 8) +  in adv7842_cp_log_status()
2838 			(hdmi_read(sd, 0x5d) & 0xf0));  in adv7842_cp_log_status()
2839 	v4l2_info(sd, "Audio N: %u\n", ((hdmi_read(sd, 0x5d) & 0x0f) << 16) +  in adv7842_cp_log_status()
2840 			(hdmi_read(sd, 0x5e) << 8) +  in adv7842_cp_log_status()
2841 			hdmi_read(sd, 0x5f));  in adv7842_cp_log_status()
2842 	v4l2_info(sd, "AV Mute: %s\n",  in adv7842_cp_log_status()
2843 			(hdmi_read(sd, 0x04) & 0x40) ? "on" : "off");  in adv7842_cp_log_status()
2844 	v4l2_info(sd, "Deep color mode: %s\n",  in adv7842_cp_log_status()
2845 			deep_color_mode_txt[hdmi_read(sd, 0x0b) >> 6]);  in adv7842_cp_log_status()
2847 	adv7842_log_infoframes(sd);  in adv7842_cp_log_status()
2852 static int adv7842_log_status(struct v4l2_subdev *sd)  in adv7842_log_status()  argument
2854 	struct adv7842_state *state = to_state(sd);  in adv7842_log_status()
2856 	if (state->mode == ADV7842_MODE_SDP)  in adv7842_log_status()
2857 		return adv7842_sdp_log_status(sd);  in adv7842_log_status()
2858 	return adv7842_cp_log_status(sd);  in adv7842_log_status()
2861 static int adv7842_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)  in adv7842_querystd()  argument
2863 	struct adv7842_state *state = to_state(sd);  in adv7842_querystd()
2865 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);  in adv7842_querystd()
2867 	if (state->mode != ADV7842_MODE_SDP)  in adv7842_querystd()
2868 		return -ENODATA;  in adv7842_querystd()
2870 	if (!(sdp_read(sd, 0x5A) & 0x01)) {  in adv7842_querystd()
2872 		v4l2_dbg(1, debug, sd, "%s: no valid signal\n", __func__);  in adv7842_querystd()
2876 	switch (sdp_read(sd, 0x52) & 0x0f) {  in adv7842_querystd()
2878 		/* NTSC-M/J */  in adv7842_querystd()
2882 		/* NTSC-443 */  in adv7842_querystd()
2890 		/* PAL-M */  in adv7842_querystd()
2894 		/* PAL-60 */  in adv7842_querystd()
2898 		/* PAL-CombN */  in adv7842_querystd()
2902 		/* PAL-BGHID */  in adv7842_querystd()
2916 static void adv7842_s_sdp_io(struct v4l2_subdev *sd, struct adv7842_sdp_io_sync_adjustment *s)  in adv7842_s_sdp_io()  argument
2918 	if (s && s->adjust) {  in adv7842_s_sdp_io()
2919 		sdp_io_write(sd, 0x94, (s->hs_beg >> 8) & 0xf);  in adv7842_s_sdp_io()
2920 		sdp_io_write(sd, 0x95, s->hs_beg & 0xff);  in adv7842_s_sdp_io()
2921 		sdp_io_write(sd, 0x96, (s->hs_width >> 8) & 0xf);  in adv7842_s_sdp_io()
2922 		sdp_io_write(sd, 0x97, s->hs_width & 0xff);  in adv7842_s_sdp_io()
2923 		sdp_io_write(sd, 0x98, (s->de_beg >> 8) & 0xf);  in adv7842_s_sdp_io()
2924 		sdp_io_write(sd, 0x99, s->de_beg & 0xff);  in adv7842_s_sdp_io()
2925 		sdp_io_write(sd, 0x9a, (s->de_end >> 8) & 0xf);  in adv7842_s_sdp_io()
2926 		sdp_io_write(sd, 0x9b, s->de_end & 0xff);  in adv7842_s_sdp_io()
2927 		sdp_io_write(sd, 0xa8, s->vs_beg_o);  in adv7842_s_sdp_io()
2928 		sdp_io_write(sd, 0xa9, s->vs_beg_e);  in adv7842_s_sdp_io()
2929 		sdp_io_write(sd, 0xaa, s->vs_end_o);  in adv7842_s_sdp_io()
2930 		sdp_io_write(sd, 0xab, s->vs_end_e);  in adv7842_s_sdp_io()
2931 		sdp_io_write(sd, 0xac, s->de_v_beg_o);  in adv7842_s_sdp_io()
2932 		sdp_io_write(sd, 0xad, s->de_v_beg_e);  in adv7842_s_sdp_io()
2933 		sdp_io_write(sd, 0xae, s->de_v_end_o);  in adv7842_s_sdp_io()
2934 		sdp_io_write(sd, 0xaf, s->de_v_end_e);  in adv7842_s_sdp_io()
2937 		sdp_io_write(sd, 0x94, 0x00);  in adv7842_s_sdp_io()
2938 		sdp_io_write(sd, 0x95, 0x00);  in adv7842_s_sdp_io()
2939 		sdp_io_write(sd, 0x96, 0x00);  in adv7842_s_sdp_io()
2940 		sdp_io_write(sd, 0x97, 0x20);  in adv7842_s_sdp_io()
2941 		sdp_io_write(sd, 0x98, 0x00);  in adv7842_s_sdp_io()
2942 		sdp_io_write(sd, 0x99, 0x00);  in adv7842_s_sdp_io()
2943 		sdp_io_write(sd, 0x9a, 0x00);  in adv7842_s_sdp_io()
2944 		sdp_io_write(sd, 0x9b, 0x00);  in adv7842_s_sdp_io()
2945 		sdp_io_write(sd, 0xa8, 0x04);  in adv7842_s_sdp_io()
2946 		sdp_io_write(sd, 0xa9, 0x04);  in adv7842_s_sdp_io()
2947 		sdp_io_write(sd, 0xaa, 0x04);  in adv7842_s_sdp_io()
2948 		sdp_io_write(sd, 0xab, 0x04);  in adv7842_s_sdp_io()
2949 		sdp_io_write(sd, 0xac, 0x04);  in adv7842_s_sdp_io()
2950 		sdp_io_write(sd, 0xad, 0x04);  in adv7842_s_sdp_io()
2951 		sdp_io_write(sd, 0xae, 0x04);  in adv7842_s_sdp_io()
2952 		sdp_io_write(sd, 0xaf, 0x04);  in adv7842_s_sdp_io()
2956 static int adv7842_s_std(struct v4l2_subdev *sd, v4l2_std_id norm)  in adv7842_s_std()  argument
2958 	struct adv7842_state *state = to_state(sd);  in adv7842_s_std()
2959 	struct adv7842_platform_data *pdata = &state->pdata;  in adv7842_s_std()
2961 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);  in adv7842_s_std()
2963 	if (state->mode != ADV7842_MODE_SDP)  in adv7842_s_std()
2964 		return -ENODATA;  in adv7842_s_std()
2967 		adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_625);  in adv7842_s_std()
2969 		adv7842_s_sdp_io(sd, &pdata->sdp_io_sync_525);  in adv7842_s_std()
2971 		adv7842_s_sdp_io(sd, NULL);  in adv7842_s_std()
2974 		state->norm = norm;  in adv7842_s_std()
2977 	return -EINVAL;  in adv7842_s_std()
2980 static int adv7842_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)  in adv7842_g_std()  argument
2982 	struct adv7842_state *state = to_state(sd);  in adv7842_g_std()
2984 	v4l2_dbg(1, debug, sd, "%s:\n", __func__);  in adv7842_g_std()
2986 	if (state->mode != ADV7842_MODE_SDP)  in adv7842_g_std()
2987 		return -ENODATA;  in adv7842_g_std()
2989 	*norm = state->norm;  in adv7842_g_std()
2993 /* ----------------------------------------------------------------------- */
2995 static int adv7842_core_init(struct v4l2_subdev *sd)  in adv7842_core_init()  argument
2997 	struct adv7842_state *state = to_state(sd);  in adv7842_core_init()
2998 	struct adv7842_platform_data *pdata = &state->pdata;  in adv7842_core_init()
2999 	hdmi_write(sd, 0x48,  in adv7842_core_init()
3000 		   (pdata->disable_pwrdnb ? 0x80 : 0) |  in adv7842_core_init()
3001 		   (pdata->disable_cable_det_rst ? 0x40 : 0));  in adv7842_core_init()
3003 	disable_input(sd);  in adv7842_core_init()
3009 	rep_write_and_or(sd, 0x77, 0xd3, 0x20);  in adv7842_core_init()
3012 	io_write(sd, 0x0c, 0x42);   /* Power up part and power down VDP */  in adv7842_core_init()
3013 	io_write(sd, 0x15, 0x80);   /* Power up pads */  in adv7842_core_init()
3016 	io_write(sd, 0x02, 0xf0 | pdata->alt_gamma << 3);  in adv7842_core_init()
3017 	io_write_and_or(sd, 0x05, 0xf0, pdata->blank_data << 3 |  in adv7842_core_init()
3018 			pdata->insert_av_codes << 2 |  in adv7842_core_init()
3019 			pdata->replicate_av_codes << 1);  in adv7842_core_init()
3023 	hdmi_write_and_or(sd, 0x1a, 0xf1, 0x08); /* Wait 1 s before unmute */  in adv7842_core_init()
3026 	io_write_and_or(sd, 0x14, 0xc0,  in adv7842_core_init()
3027 			pdata->dr_str_data << 4 |  in adv7842_core_init()
3028 			pdata->dr_str_clk << 2 |  in adv7842_core_init()
3029 			pdata->dr_str_sync);  in adv7842_core_init()
3032 	cp_write_and_or(sd, 0xba, 0xfc, pdata->hdmi_free_run_enable |  in adv7842_core_init()
3033 					(pdata->hdmi_free_run_mode << 1));  in adv7842_core_init()
3036 	sdp_write_and_or(sd, 0xdd, 0xf0, pdata->sdp_free_run_force |  in adv7842_core_init()
3037 					 (pdata->sdp_free_run_cbar_en << 1) |  in adv7842_core_init()
3038 					 (pdata->sdp_free_run_man_col_en << 2) |  in adv7842_core_init()
3039 					 (pdata->sdp_free_run_auto << 3));  in adv7842_core_init()
3042 	cp_write(sd, 0x69, 0x14);   /* Enable CP CSC */  in adv7842_core_init()
3043 	io_write(sd, 0x06, 0xa6);   /* positive VS and HS and DE */  in adv7842_core_init()
3044 	cp_write(sd, 0xf3, 0xdc); /* Low threshold to enter/exit free run mode */  in adv7842_core_init()
3045 	afe_write(sd, 0xb5, 0x01);  /* Setting MCLK to 256Fs */  in adv7842_core_init()
3047 	afe_write(sd, 0x02, pdata->ain_sel); /* Select analog input muxing mode */  in adv7842_core_init()
3048 	io_write_and_or(sd, 0x30, ~(1 << 4), pdata->output_bus_lsb_to_msb << 4);  in adv7842_core_init()
3050 	sdp_csc_coeff(sd, &pdata->sdp_csc_coeff);  in adv7842_core_init()
3053 	if (pdata->sd_ram_size >= 128) {  in adv7842_core_init()
3054 		sdp_write(sd, 0x12, 0x0d); /* Frame TBC,3D comb enabled */  in adv7842_core_init()
3055 		if (pdata->sd_ram_ddr) {  in adv7842_core_init()
3057 			sdp_io_write(sd, 0x6f, 0x00); /* DDR mode */  in adv7842_core_init()
3058 			sdp_io_write(sd, 0x75, 0x0a); /* 128 MB memory size */  in adv7842_core_init()
3059 			sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */  in adv7842_core_init()
3060 			sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */  in adv7842_core_init()
3061 			sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */  in adv7842_core_init()
3063 			sdp_io_write(sd, 0x75, 0x0a); /* 64 MB memory size ?*/  in adv7842_core_init()
3064 			sdp_io_write(sd, 0x74, 0x00); /* must be zero for sdr sdram */  in adv7842_core_init()
3065 			sdp_io_write(sd, 0x79, 0x33); /* CAS latency to 3,  in adv7842_core_init()
3067 			sdp_io_write(sd, 0x6f, 0x01); /* SDR mode */  in adv7842_core_init()
3068 			sdp_io_write(sd, 0x7a, 0xa5); /* Timing Adjustment */  in adv7842_core_init()
3069 			sdp_io_write(sd, 0x7b, 0x8f); /* Timing Adjustment */  in adv7842_core_init()
3070 			sdp_io_write(sd, 0x60, 0x01); /* SDRAM reset */  in adv7842_core_init()
3074 		 * Manual UG-214, rev 0 is bit confusing on this bit  in adv7842_core_init()
3075 		 * but a '1' disables any signal if the Ram is active.  in adv7842_core_init()
3077 		sdp_io_write(sd, 0x29, 0x10); /* Tristate memory interface */  in adv7842_core_init()
3080 	select_input(sd, pdata->vid_std_select);  in adv7842_core_init()
3082 	enable_input(sd);  in adv7842_core_init()
3084 	if (pdata->hpa_auto) {  in adv7842_core_init()
3086 		hdmi_write(sd, 0x69, 0x5c);  in adv7842_core_init()
3089 		hdmi_write(sd, 0x69, 0xa3);  in adv7842_core_init()
3091 		io_write_and_or(sd, 0x20, 0xcf, 0x00);  in adv7842_core_init()
3095 	io_write(sd, 0x19, 0x80 | pdata->llc_dll_phase);  in adv7842_core_init()
3096 	io_write(sd, 0x33, 0x40);  in adv7842_core_init()
3099 	io_write(sd, 0x40, 0xf2); /* Configure INT1 */  in adv7842_core_init()
3101 	adv7842_irq_enable(sd, true);  in adv7842_core_init()
3103 	return v4l2_ctrl_handler_setup(sd->ctrl_handler);  in adv7842_core_init()
3106 /* ----------------------------------------------------------------------- */
3108 static int adv7842_ddr_ram_test(struct v4l2_subdev *sd)  in adv7842_ddr_ram_test()  argument
3121 	io_write(sd, 0x00, 0x01);  /* Program SDP 4x1 */  in adv7842_ddr_ram_test()
3122 	io_write(sd, 0x01, 0x00);  /* Program SDP mode */  in adv7842_ddr_ram_test()
3123 	afe_write(sd, 0x80, 0x92); /* SDP Recommended Write */  in adv7842_ddr_ram_test()
3124 	afe_write(sd, 0x9B, 0x01); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3125 	afe_write(sd, 0x9C, 0x60); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3126 	afe_write(sd, 0x9E, 0x02); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3127 	afe_write(sd, 0xA0, 0x0B); /* SDP Recommended Write ADV7844ES1 */  in adv7842_ddr_ram_test()
3128 	afe_write(sd, 0xC3, 0x02); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3129 	io_write(sd, 0x0C, 0x40);  /* Power up ADV7844 */  in adv7842_ddr_ram_test()
3130 	io_write(sd, 0x15, 0xBA);  /* Enable outputs */  in adv7842_ddr_ram_test()
3131 	sdp_write(sd, 0x12, 0x00); /* Disable 3D comb, Frame TBC & 3DNR */  in adv7842_ddr_ram_test()
3132 	io_write(sd, 0xFF, 0x04);  /* Reset memory controller */  in adv7842_ddr_ram_test()
3136 	sdp_write(sd, 0x12, 0x00);    /* Disable 3D Comb, Frame TBC & 3DNR */  in adv7842_ddr_ram_test()
3137 	sdp_io_write(sd, 0x2A, 0x01); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3138 	sdp_io_write(sd, 0x7c, 0x19); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3139 	sdp_io_write(sd, 0x80, 0x87); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3140 	sdp_io_write(sd, 0x81, 0x4a); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3141 	sdp_io_write(sd, 0x82, 0x2c); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3142 	sdp_io_write(sd, 0x83, 0x0e); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3143 	sdp_io_write(sd, 0x84, 0x94); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3144 	sdp_io_write(sd, 0x85, 0x62); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3145 	sdp_io_write(sd, 0x7d, 0x00); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3146 	sdp_io_write(sd, 0x7e, 0x1a); /* Memory BIST Initialisation */  in adv7842_ddr_ram_test()
3150 	sdp_io_write(sd, 0xd9, 0xd5); /* Enable BIST Test */  in adv7842_ddr_ram_test()
3151 	sdp_write(sd, 0x12, 0x05); /* Enable FRAME TBC & 3D COMB */  in adv7842_ddr_ram_test()
3156 		u8 result = sdp_io_read(sd, 0xdb);  in adv7842_ddr_ram_test()
3167 	v4l2_dbg(1, debug, sd,  in adv7842_ddr_ram_test()
3172 		return -EIO;  in adv7842_ddr_ram_test()
3176 static void adv7842_rewrite_i2c_addresses(struct v4l2_subdev *sd,  in adv7842_rewrite_i2c_addresses()  argument
3179 	io_write(sd, 0xf1, pdata->i2c_sdp << 1);  in adv7842_rewrite_i2c_addresses()
3180 	io_write(sd, 0xf2, pdata->i2c_sdp_io << 1);  in adv7842_rewrite_i2c_addresses()
3181 	io_write(sd, 0xf3, pdata->i2c_avlink << 1);  in adv7842_rewrite_i2c_addresses()
3182 	io_write(sd, 0xf4, pdata->i2c_cec << 1);  in adv7842_rewrite_i2c_addresses()
3183 	io_write(sd, 0xf5, pdata->i2c_infoframe << 1);  in adv7842_rewrite_i2c_addresses()
3185 	io_write(sd, 0xf8, pdata->i2c_afe << 1);  in adv7842_rewrite_i2c_addresses()
3186 	io_write(sd, 0xf9, pdata->i2c_repeater << 1);  in adv7842_rewrite_i2c_addresses()
3187 	io_write(sd, 0xfa, pdata->i2c_edid << 1);  in adv7842_rewrite_i2c_addresses()
3188 	io_write(sd, 0xfb, pdata->i2c_hdmi << 1);  in adv7842_rewrite_i2c_addresses()
3190 	io_write(sd, 0xfd, pdata->i2c_cp << 1);  in adv7842_rewrite_i2c_addresses()
3191 	io_write(sd, 0xfe, pdata->i2c_vdp << 1);  in adv7842_rewrite_i2c_addresses()
3194 static int adv7842_command_ram_test(struct v4l2_subdev *sd)  in adv7842_command_ram_test()  argument
3196 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in adv7842_command_ram_test()
3197 	struct adv7842_state *state = to_state(sd);  in adv7842_command_ram_test()
3198 	struct adv7842_platform_data *pdata = client->dev.platform_data;  in adv7842_command_ram_test()
3203 		return -ENODEV;  in adv7842_command_ram_test()
3205 	if (!pdata->sd_ram_size || !pdata->sd_ram_ddr) {  in adv7842_command_ram_test()
3206 		v4l2_info(sd, "no sdram or no ddr sdram\n");  in adv7842_command_ram_test()
3207 		return -EINVAL;  in adv7842_command_ram_test()
3210 	main_reset(sd);  in adv7842_command_ram_test()
3212 	adv7842_rewrite_i2c_addresses(sd, pdata);  in adv7842_command_ram_test()
3215 	ret = adv7842_ddr_ram_test(sd);  in adv7842_command_ram_test()
3217 	main_reset(sd);  in adv7842_command_ram_test()
3219 	adv7842_rewrite_i2c_addresses(sd, pdata);  in adv7842_command_ram_test()
3221 	/* and re-init chip and state */  in adv7842_command_ram_test()
3222 	adv7842_core_init(sd);  in adv7842_command_ram_test()
3224 	disable_input(sd);  in adv7842_command_ram_test()
3226 	select_input(sd, state->vid_std_select);  in adv7842_command_ram_test()
3228 	enable_input(sd);  in adv7842_command_ram_test()
3230 	edid_write_vga_segment(sd);  in adv7842_command_ram_test()
3231 	edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_A);  in adv7842_command_ram_test()
3232 	edid_write_hdmi_segment(sd, ADV7842_EDID_PORT_B);  in adv7842_command_ram_test()
3234 	timings = state->timings;  in adv7842_command_ram_test()
3236 	memset(&state->timings, 0, sizeof(struct v4l2_dv_timings));  in adv7842_command_ram_test()
3238 	adv7842_s_dv_timings(sd, 0, &timings);  in adv7842_command_ram_test()
3243 static long adv7842_ioctl(struct v4l2_subdev *sd, unsigned int cmd, void *arg)  in adv7842_ioctl()  argument
3247 		return adv7842_command_ram_test(sd);  in adv7842_ioctl()
3249 	return -ENOTTY;  in adv7842_ioctl()
3252 static int adv7842_subscribe_event(struct v4l2_subdev *sd,  in adv7842_subscribe_event()  argument
3256 	switch (sub->type) {  in adv7842_subscribe_event()
3258 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);  in adv7842_subscribe_event()
3260 		return v4l2_ctrl_subdev_subscribe_event(sd, fh, sub);  in adv7842_subscribe_event()
3262 		return -EINVAL;  in adv7842_subscribe_event()
3266 static int adv7842_registered(struct v4l2_subdev *sd)  in adv7842_registered()  argument
3268 	struct adv7842_state *state = to_state(sd);  in adv7842_registered()
3269 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in adv7842_registered()
3272 	err = cec_register_adapter(state->cec_adap, &client->dev);  in adv7842_registered()
3274 		cec_delete_adapter(state->cec_adap);  in adv7842_registered()
3278 static void adv7842_unregistered(struct v4l2_subdev *sd)  in adv7842_unregistered()  argument
3280 	struct adv7842_state *state = to_state(sd);  in adv7842_unregistered()
3282 	cec_unregister_adapter(state->cec_adap);  in adv7842_unregistered()
3285 /* ----------------------------------------------------------------------- */
3336 /* -------------------------- custom ctrls ---------------------------------- */
3345 	.step = 1,
3354 	.max = 1,
3355 	.step = 1,
3356 	.def = 1,
3369 static void adv7842_unregister_clients(struct v4l2_subdev *sd)  in adv7842_unregister_clients()  argument
3371 	struct adv7842_state *state = to_state(sd);  in adv7842_unregister_clients()
3372 	i2c_unregister_device(state->i2c_avlink);  in adv7842_unregister_clients()
3373 	i2c_unregister_device(state->i2c_cec);  in adv7842_unregister_clients()
3374 	i2c_unregister_device(state->i2c_infoframe);  in adv7842_unregister_clients()
3375 	i2c_unregister_device(state->i2c_sdp_io);  in adv7842_unregister_clients()
3376 	i2c_unregister_device(state->i2c_sdp);  in adv7842_unregister_clients()
3377 	i2c_unregister_device(state->i2c_afe);  in adv7842_unregister_clients()
3378 	i2c_unregister_device(state->i2c_repeater);  in adv7842_unregister_clients()
3379 	i2c_unregister_device(state->i2c_edid);  in adv7842_unregister_clients()
3380 	i2c_unregister_device(state->i2c_hdmi);  in adv7842_unregister_clients()
3381 	i2c_unregister_device(state->i2c_cp);  in adv7842_unregister_clients()
3382 	i2c_unregister_device(state->i2c_vdp);  in adv7842_unregister_clients()
3384 	state->i2c_avlink = NULL;  in adv7842_unregister_clients()
3385 	state->i2c_cec = NULL;  in adv7842_unregister_clients()
3386 	state->i2c_infoframe = NULL;  in adv7842_unregister_clients()
3387 	state->i2c_sdp_io = NULL;  in adv7842_unregister_clients()
3388 	state->i2c_sdp = NULL;  in adv7842_unregister_clients()
3389 	state->i2c_afe = NULL;  in adv7842_unregister_clients()
3390 	state->i2c_repeater = NULL;  in adv7842_unregister_clients()
3391 	state->i2c_edid = NULL;  in adv7842_unregister_clients()
3392 	state->i2c_hdmi = NULL;  in adv7842_unregister_clients()
3393 	state->i2c_cp = NULL;  in adv7842_unregister_clients()
3394 	state->i2c_vdp = NULL;  in adv7842_unregister_clients()
3397 static struct i2c_client *adv7842_dummy_client(struct v4l2_subdev *sd, const char *desc,  in adv7842_dummy_client()  argument
3400 	struct i2c_client *client = v4l2_get_subdevdata(sd);  in adv7842_dummy_client()
3403 	io_write(sd, io_reg, addr << 1);  in adv7842_dummy_client()
3406 		v4l2_err(sd, "no %s i2c addr configured\n", desc);  in adv7842_dummy_client()
3410 	cp = i2c_new_dummy_device(client->adapter, io_read(sd, io_reg) >> 1);  in adv7842_dummy_client()
3412 		v4l2_err(sd, "register %s on i2c addr 0x%x failed with %ld\n",  in adv7842_dummy_client()
3420 static int adv7842_register_clients(struct v4l2_subdev *sd)  in adv7842_register_clients()  argument
3422 	struct adv7842_state *state = to_state(sd);  in adv7842_register_clients()
3423 	struct adv7842_platform_data *pdata = &state->pdata;  in adv7842_register_clients()
3425 	state->i2c_avlink = adv7842_dummy_client(sd, "avlink", pdata->i2c_avlink, 0xf3);  in adv7842_register_clients()
3426 	state->i2c_cec = adv7842_dummy_client(sd, "cec", pdata->i2c_cec, 0xf4);  in adv7842_register_clients()
3427 	state->i2c_infoframe = adv7842_dummy_client(sd, "infoframe", pdata->i2c_infoframe, 0xf5);  in adv7842_register_clients()
3428 	state->i2c_sdp_io = adv7842_dummy_client(sd, "sdp_io", pdata->i2c_sdp_io, 0xf2);  in adv7842_register_clients()
3429 	state->i2c_sdp = adv7842_dummy_client(sd, "sdp", pdata->i2c_sdp, 0xf1);  in adv7842_register_clients()
3430 	state->i2c_afe = adv7842_dummy_client(sd, "afe", pdata->i2c_afe, 0xf8);  in adv7842_register_clients()
3431 	state->i2c_repeater = adv7842_dummy_client(sd, "repeater", pdata->i2c_repeater, 0xf9);  in adv7842_register_clients()
3432 	state->i2c_edid = adv7842_dummy_client(sd, "edid", pdata->i2c_edid, 0xfa);  in adv7842_register_clients()
3433 	state->i2c_hdmi = adv7842_dummy_client(sd, "hdmi", pdata->i2c_hdmi, 0xfb);  in adv7842_register_clients()
3434 	state->i2c_cp = adv7842_dummy_client(sd, "cp", pdata->i2c_cp, 0xfd);  in adv7842_register_clients()
3435 	state->i2c_vdp = adv7842_dummy_client(sd, "vdp", pdata->i2c_vdp, 0xfe);  in adv7842_register_clients()
3437 	if (!state->i2c_avlink ||  in adv7842_register_clients()
3438 	    !state->i2c_cec ||  in adv7842_register_clients()
3439 	    !state->i2c_infoframe ||  in adv7842_register_clients()
3440 	    !state->i2c_sdp_io ||  in adv7842_register_clients()
3441 	    !state->i2c_sdp ||  in adv7842_register_clients()
3442 	    !state->i2c_afe ||  in adv7842_register_clients()
3443 	    !state->i2c_repeater ||  in adv7842_register_clients()
3444 	    !state->i2c_edid ||  in adv7842_register_clients()
3445 	    !state->i2c_hdmi ||  in adv7842_register_clients()
3446 	    !state->i2c_cp ||  in adv7842_register_clients()
3447 	    !state->i2c_vdp)  in adv7842_register_clients()
3448 		return -1;  in adv7842_register_clients()
3458 	struct adv7842_platform_data *pdata = client->dev.platform_data;  in adv7842_probe()
3461 	struct v4l2_subdev *sd;  in adv7842_probe()  local
3467 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))  in adv7842_probe()
3468 		return -EIO;  in adv7842_probe()
3470 	v4l_dbg(1, debug, client, "detecting adv7842 client on address 0x%x\n",  in adv7842_probe()
3471 		client->addr << 1);  in adv7842_probe()
3475 		return -ENODEV;  in adv7842_probe()
3478 	state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);  in adv7842_probe()
3480 		return -ENOMEM;  in adv7842_probe()
3483 	state->pdata = *pdata;  in adv7842_probe()
3484 	state->timings = cea640x480;  in adv7842_probe()
3485 	state->format = adv7842_format_info(state, MEDIA_BUS_FMT_YUYV8_2X8);  in adv7842_probe()
3487 	sd = &state->sd;  in adv7842_probe()
3488 	v4l2_i2c_subdev_init(sd, client, &adv7842_ops);  in adv7842_probe()
3489 	sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE | V4L2_SUBDEV_FL_HAS_EVENTS;  in adv7842_probe()
3490 	sd->internal_ops = &adv7842_int_ops;  in adv7842_probe()
3491 	state->mode = pdata->mode;  in adv7842_probe()
3493 	state->hdmi_port_a = pdata->input == ADV7842_SELECT_HDMI_PORT_A;  in adv7842_probe()
3494 	state->restart_stdi_once = true;  in adv7842_probe()
3500 		v4l2_info(sd, "got rev=0x%04x on first read attempt\n", rev);  in adv7842_probe()
3505 		v4l2_info(sd, "not an adv7842 on address 0x%x (rev=0x%04x)\n",  in adv7842_probe()
3506 			  client->addr << 1, rev);  in adv7842_probe()
3507 		return -ENODEV;  in adv7842_probe()
3510 	if (pdata->chip_reset)  in adv7842_probe()
3511 		main_reset(sd);  in adv7842_probe()
3514 	hdl = &state->hdl;  in adv7842_probe()
3519 			  V4L2_CID_BRIGHTNESS, -128, 127, 1, 0);  in adv7842_probe()
3521 			  V4L2_CID_CONTRAST, 0, 255, 1, 128);  in adv7842_probe()
3523 			  V4L2_CID_SATURATION, 0, 255, 1, 128);  in adv7842_probe()
3525 			  V4L2_CID_HUE, 0, 128, 1, 0);  in adv7842_probe()
3530 		ctrl->flags |= V4L2_CTRL_FLAG_VOLATILE;  in adv7842_probe()
3533 	state->detect_tx_5v_ctrl = v4l2_ctrl_new_std(hdl, NULL,  in adv7842_probe()
3535 	state->analog_sampling_phase_ctrl = v4l2_ctrl_new_custom(hdl,  in adv7842_probe()
3537 	state->free_run_color_ctrl_manual = v4l2_ctrl_new_custom(hdl,  in adv7842_probe()
3539 	state->free_run_color_ctrl = v4l2_ctrl_new_custom(hdl,  in adv7842_probe()
3541 	state->rgb_quantization_range_ctrl =  in adv7842_probe()
3545 	sd->ctrl_handler = hdl;  in adv7842_probe()
3546 	if (hdl->error) {  in adv7842_probe()
3547 		err = hdl->error;  in adv7842_probe()
3550 	if (adv7842_s_detect_tx_5v_ctrl(sd)) {  in adv7842_probe()
3551 		err = -ENODEV;  in adv7842_probe()
3555 	if (adv7842_register_clients(sd) < 0) {  in adv7842_probe()
3556 		err = -ENOMEM;  in adv7842_probe()
3557 		v4l2_err(sd, "failed to create all i2c clients\n");  in adv7842_probe()
3562 	INIT_DELAYED_WORK(&state->delayed_work_enable_hotplug,  in adv7842_probe()
3565 	sd->entity.function = MEDIA_ENT_F_DV_DECODER;  in adv7842_probe()
3567 		state->pads[i].flags = MEDIA_PAD_FL_SINK;  in adv7842_probe()
3568 	state->pads[ADV7842_PAD_SOURCE].flags = MEDIA_PAD_FL_SOURCE;  in adv7842_probe()
3569 	err = media_entity_pads_init(&sd->entity, ADV7842_PAD_SOURCE + 1,  in adv7842_probe()
3570 				     state->pads);  in adv7842_probe()
3574 	err = adv7842_core_init(sd);  in adv7842_probe()
3579 	state->cec_adap = cec_allocate_adapter(&adv7842_cec_adap_ops,  in adv7842_probe()
3580 		state, dev_name(&client->dev),  in adv7842_probe()
3582 	err = PTR_ERR_OR_ZERO(state->cec_adap);  in adv7842_probe()
3587 	v4l2_info(sd, "%s found @ 0x%x (%s)\n", client->name,  in adv7842_probe()
3588 		  client->addr << 1, client->adapter->name);  in adv7842_probe()
3592 	media_entity_cleanup(&sd->entity);  in adv7842_probe()
3594 	cancel_delayed_work(&state->delayed_work_enable_hotplug);  in adv7842_probe()
3596 	adv7842_unregister_clients(sd);  in adv7842_probe()
3602 /* ----------------------------------------------------------------------- */
3606 	struct v4l2_subdev *sd = i2c_get_clientdata(client);  in adv7842_remove()  local
3607 	struct adv7842_state *state = to_state(sd);  in adv7842_remove()
3609 	adv7842_irq_enable(sd, false);  in adv7842_remove()
3610 	cancel_delayed_work_sync(&state->delayed_work_enable_hotplug);  in adv7842_remove()
3611 	v4l2_device_unregister_subdev(sd);  in adv7842_remove()
3612 	media_entity_cleanup(&sd->entity);  in adv7842_remove()
3613 	adv7842_unregister_clients(sd);  in adv7842_remove()
3614 	v4l2_ctrl_handler_free(sd->ctrl_handler);  in adv7842_remove()
3617 /* ----------------------------------------------------------------------- */
3625 /* ----------------------------------------------------------------------- */