Lines Matching +full:10 +full:khz
45 * 64, (write 0x05 to reg), freq step size 158kHz
46 * 10, (write 0x0a to reg), freq step size 1.011kHz (used here)
47 * 5, (write 0x09 to reg), freq step size 2.022kHz
50 #define _RDIV 10
103 reg = 10; in zl10036_write()
164 * 10[0xe1]: 1 | 1 | 1 | 0 | 0 | LS2 | LS1 | LS0
191 /* fbw is measured in kHz */ in zl10036_set_bandwidth()
208 #define _BR_MAXIMUM (_XTAL/575) /* _XTAL / 575kHz = 17 */ in zl10036_set_bandwidth()
254 * maximum br is 63 -> max time = 2 /10 MHz = 2e-7 */ in zl10036_set_bandwidth()
306 if ((frequency < fe->ops.info.frequency_min_hz / kHz) in zl10036_set_params()
307 || (frequency > fe->ops.info.frequency_max_hz / kHz)) in zl10036_set_params()
317 /* scale to kHz */ in zl10036_set_params()
360 msleep(10); in zl10036_set_params()
384 /* could also be one block from reg 2 to 13 and additional 10/11 */ in zl10036_init_regs()
391 { 0xe3, 0x5b }, /* 10/11: lock window level */ in zl10036_init_regs()
393 { 0xe3, 0xf9 }, /* 10/11: unlock window level */ in zl10036_init_regs()