Lines Matching refs:tda1004x_write_mask
160 static int tda1004x_write_mask(struct tda1004x_state *state, int reg, int mask, int data) in tda1004x_write_mask() function
201 result = tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 2); in tda1004x_enable_tuner_i2c()
210 return tda1004x_write_mask(state, TDA1004X_CONFC4, 2, 0); in tda1004x_disable_tuner_i2c()
365 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); // we want to read from the DSP in tda1004x_check_upload_ok()
397 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x10, 0); in tda10045_fwupload()
398 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda10045_fwupload()
399 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda10045_fwupload()
487 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 1, 0); in tda10046_fwupload()
491 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, state->config->gpio_config &0x0f); in tda10046_fwupload()
498 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0); in tda10046_fwupload()
546 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); // going to boot from HOST in tda10046_fwupload()
613 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0); // wake up the ADC in tda10045_init()
616 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10045_init()
617 tda1004x_write_mask(state, TDA1004X_AUTO, 8, 0); // select HP stream in tda10045_init()
618 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x40, 0); // set polarity of VAGC signal in tda10045_init()
619 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x80, 0x80); // enable pulse killer in tda10045_init()
620 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); // enable auto offset in tda10045_init()
621 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0x0); // no frequency offset in tda10045_init()
624 tda1004x_write_mask(state, TDA1004X_VBER_MSB, 0xe0, 0xa0); // 10^6 VBER measurement bits in tda10045_init()
625 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x10, 0); // VAGC polarity in tda10045_init()
628 tda1004x_write_mask(state, 0x1f, 0x01, state->config->invert_oclk); in tda10045_init()
644 tda1004x_write_mask(state, TDA1004X_CONFC4, 0x20, 0); // disable DSP watchdog timer in tda10046_init()
651 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
655 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
659 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x00); // set AGC polarities in tda10046_init()
665 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0xf0, 0x60); // set AGC polarities in tda10046_init()
669 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x40); in tda10046_init()
670 tda1004x_write_mask(state, 0x3a, 0x80, state->config->invert_oclk << 7); in tda10046_init()
672 tda1004x_write_mask(state, TDA10046H_CONF_TRISTATE1, 0xc0, 0x80); in tda10046_init()
673 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x10, in tda10046_init()
677 tda1004x_write_mask (state, TDA10046H_CONF_TRISTATE1, 0x3e, 0x38); // Turn IF AGC output on in tda10046_init()
702 tda1004x_write_mask(state, TDA1004X_AUTO, 0x10, 0x10); in tda1004x_set_fe()
703 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x80, 0); in tda1004x_set_fe()
704 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0xC0, 0); in tda1004x_set_fe()
707 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 0); in tda1004x_set_fe()
730 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 1); // enable auto in tda1004x_set_fe()
731 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x03, 0); /* turn off modulation bits */ in tda1004x_set_fe()
732 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0); // turn off hierarchy bits in tda1004x_set_fe()
733 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x3f, 0); // turn off FEC bits in tda1004x_set_fe()
735 tda1004x_write_mask(state, TDA1004X_AUTO, 1, 0); // disable auto in tda1004x_set_fe()
741 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 7, tmp); in tda1004x_set_fe()
747 tda1004x_write_mask(state, TDA1004X_IN_CONF2, 0x38, tmp << 3); in tda1004x_set_fe()
752 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 0); in tda1004x_set_fe()
756 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 1); in tda1004x_set_fe()
760 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 3, 2); in tda1004x_set_fe()
770 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 0 << 5); in tda1004x_set_fe()
774 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 1 << 5); in tda1004x_set_fe()
778 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 2 << 5); in tda1004x_set_fe()
782 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x60, 3 << 5); in tda1004x_set_fe()
807 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0); in tda1004x_set_fe()
811 tda1004x_write_mask(state, TDA1004X_CONFC1, 0x20, 0x20); in tda1004x_set_fe()
821 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
822 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
826 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
827 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 1 << 2); in tda1004x_set_fe()
831 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
832 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 2 << 2); in tda1004x_set_fe()
836 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 0); in tda1004x_set_fe()
837 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 3 << 2); in tda1004x_set_fe()
841 tda1004x_write_mask(state, TDA1004X_AUTO, 2, 2); in tda1004x_set_fe()
842 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x0c, 0 << 2); in tda1004x_set_fe()
852 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
853 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0 << 4); in tda1004x_set_fe()
857 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 0); in tda1004x_set_fe()
858 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 1 << 4); in tda1004x_set_fe()
862 tda1004x_write_mask(state, TDA1004X_AUTO, 4, 4); in tda1004x_set_fe()
863 tda1004x_write_mask(state, TDA1004X_IN_CONF1, 0x10, 0); in tda1004x_set_fe()
873 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 8); in tda1004x_set_fe()
874 tda1004x_write_mask(state, TDA1004X_CONFC4, 8, 0); in tda1004x_set_fe()
878 tda1004x_write_mask(state, TDA1004X_AUTO, 0x40, 0x40); in tda1004x_set_fe()
880 tda1004x_write_mask(state, TDA10046H_AGC_CONF, 4, 1); in tda1004x_set_fe()
1138 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1139 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1140 tda1004x_write_mask(state, TDA1004X_UNCOR, 0x80, 0); in tda1004x_read_ucblocks()
1189 tda1004x_write_mask(state, TDA1004X_CONFADC1, 0x10, 0x10); in tda1004x_sleep()
1198 tda1004x_write_mask(state, TDA10046H_CONF_POLARITY, 0x0f, in tda1004x_sleep()
1201 tda1004x_write_mask(state, TDA1004X_CONFADC2, 0xc0, 0xc0); in tda1004x_sleep()
1202 tda1004x_write_mask(state, TDA1004X_CONFC4, 1, 1); in tda1004x_sleep()