Lines Matching refs:stv0367_writereg
122 int stv0367_writereg(struct stv0367_state *state, u16 reg, u8 data) in stv0367_writereg() function
204 stv0367_writereg(state, (label >> 16) & 0xffff, reg); in stv0367_writebits()
251 stv0367_writereg(state, deftab[i].addr, deftab[i].value); in stv0367_write_table()
270 stv0367_writereg(state, R367TER_PLLMDIV, 0x1b); in stv0367_pll_setup()
271 stv0367_writereg(state, R367TER_PLLNDIV, 0xe8); in stv0367_pll_setup()
280 stv0367_writereg(state, R367TER_PLLMDIV, 0x2); in stv0367_pll_setup()
281 stv0367_writereg(state, R367TER_PLLNDIV, 0x1b); in stv0367_pll_setup()
284 stv0367_writereg(state, R367TER_PLLMDIV, 0xa); in stv0367_pll_setup()
285 stv0367_writereg(state, R367TER_PLLNDIV, 0x55); in stv0367_pll_setup()
290 stv0367_writereg(state, R367TER_PLLMDIV, 0x1); in stv0367_pll_setup()
291 stv0367_writereg(state, R367TER_PLLNDIV, 0x8); in stv0367_pll_setup()
294 stv0367_writereg(state, R367TER_PLLMDIV, 0xc); in stv0367_pll_setup()
295 stv0367_writereg(state, R367TER_PLLNDIV, 0x55); in stv0367_pll_setup()
300 stv0367_writereg(state, R367TER_PLLSETUP, 0x18); in stv0367_pll_setup()
329 stv0367_writereg(state, R367TER_I2CRPT, tmp); in stv0367ter_gate_ctrl()
488 stv0367_writereg(state, in stv0367ter_filt_coeff_init()
491 stv0367_writereg(state, in stv0367ter_filt_coeff_init()
757 stv0367_writereg(state, R367TER_CHC_CTL, 0x01); in stv0367ter_lock_algo()
762 stv0367_writereg(state, R367TER_CHC_CTL, 0x11); in stv0367ter_lock_algo()
806 stv0367_writereg(state, R367TER_CHC_CTL, 0x11); in stv0367ter_lock_algo()
829 stv0367_writereg(state, R367TER_SFDLYSETH, 0xc0); in stv0367ter_lock_algo()
830 stv0367_writereg(state, R367TER_SFDLYSETM, 0x60); in stv0367ter_lock_algo()
831 stv0367_writereg(state, R367TER_SFDLYSETL, 0x0); in stv0367ter_lock_algo()
833 stv0367_writereg(state, R367TER_SFDLYSETH, 0x0); in stv0367ter_lock_algo()
963 stv0367_writereg(state, R367TER_I2CRPT, 0xa0); in stv0367ter_init()
964 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ter_init()
1795 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1798 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x64); in stv0367cab_SetQamSize()
1799 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1800 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); in stv0367cab_SetQamSize()
1801 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1802 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1803 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); in stv0367cab_SetQamSize()
1804 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); in stv0367cab_SetQamSize()
1805 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x8a); in stv0367cab_SetQamSize()
1808 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1809 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x6e); in stv0367cab_SetQamSize()
1810 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); in stv0367cab_SetQamSize()
1811 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1812 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xb7); in stv0367cab_SetQamSize()
1813 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x9d); in stv0367cab_SetQamSize()
1814 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); in stv0367cab_SetQamSize()
1815 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); in stv0367cab_SetQamSize()
1818 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x82); in stv0367cab_SetQamSize()
1819 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); in stv0367cab_SetQamSize()
1821 stv0367_writereg(state, R367CAB_FSM_STATE, 0xb0); in stv0367cab_SetQamSize()
1822 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1823 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa5); in stv0367cab_SetQamSize()
1825 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); in stv0367cab_SetQamSize()
1826 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1827 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); in stv0367cab_SetQamSize()
1829 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); in stv0367cab_SetQamSize()
1830 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); in stv0367cab_SetQamSize()
1831 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1833 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x95); in stv0367cab_SetQamSize()
1834 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); in stv0367cab_SetQamSize()
1835 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0x99); in stv0367cab_SetQamSize()
1838 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1839 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x76); in stv0367cab_SetQamSize()
1840 stv0367_writereg(state, R367CAB_FSM_STATE, 0x90); in stv0367cab_SetQamSize()
1841 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xb1); in stv0367cab_SetQamSize()
1843 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1845 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa6); in stv0367cab_SetQamSize()
1847 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0x97); in stv0367cab_SetQamSize()
1849 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x8e); in stv0367cab_SetQamSize()
1850 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x7f); in stv0367cab_SetQamSize()
1851 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); in stv0367cab_SetQamSize()
1854 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x94); in stv0367cab_SetQamSize()
1855 stv0367_writereg(state, R367CAB_AGC_PWR_REF_L, 0x5a); in stv0367cab_SetQamSize()
1856 stv0367_writereg(state, R367CAB_FSM_STATE, 0xa0); in stv0367cab_SetQamSize()
1858 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1860 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xc1); in stv0367cab_SetQamSize()
1862 stv0367_writereg(state, R367CAB_EQU_CTR_LPF_GAIN, 0xd1); in stv0367cab_SetQamSize()
1864 stv0367_writereg(state, R367CAB_EQU_CRL_LPF_GAIN, 0xa7); in stv0367cab_SetQamSize()
1865 stv0367_writereg(state, R367CAB_EQU_CRL_LD_SEN, 0x85); in stv0367cab_SetQamSize()
1866 stv0367_writereg(state, R367CAB_EQU_CRL_LIMITER, 0x40); in stv0367cab_SetQamSize()
1867 stv0367_writereg(state, R367CAB_EQU_PNT_GAIN, 0xa7); in stv0367cab_SetQamSize()
1870 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1873 stv0367_writereg(state, R367CAB_IQDEM_ADJ_AGC_REF, 0x00); in stv0367cab_SetQamSize()
1908 stv0367_writereg(state, R367CAB_MIX_NCO_LL, sampled_if); in stv0367cab_set_derot_freq()
1909 stv0367_writereg(state, R367CAB_MIX_NCO_HL, (sampled_if >> 8)); in stv0367cab_set_derot_freq()
1976 stv0367_writereg(state, R367CAB_EQU_CRL_TFR, (u8)u32_tmp); in stv0367cab_set_srate()
2063 stv0367_writereg(state, R367CAB_SRC_NCO_LL, u32_tmp); in stv0367cab_set_srate()
2064 stv0367_writereg(state, R367CAB_SRC_NCO_LH, (u32_tmp >> 8)); in stv0367cab_set_srate()
2065 stv0367_writereg(state, R367CAB_SRC_NCO_HL, (u32_tmp >> 16)); in stv0367cab_set_srate()
2066 stv0367_writereg(state, R367CAB_SRC_NCO_HH, (u32_tmp >> 24)); in stv0367cab_set_srate()
2068 stv0367_writereg(state, R367CAB_IQDEM_GAIN_SRC_L, u32_tmp1 & 0x00ff); in stv0367cab_set_srate()
2295 stv0367_writereg(state, R367CAB_ANACTRL, 0x00);/*PLL enabled and used */ in stv0367cab_init()
2384 stv0367_writereg(state, R367CAB_CTRL_1, 0x04); in stv0367cab_algo()
2411 stv0367_writereg(state, R367CAB_CTRL_1, 0x00); in stv0367cab_algo()
2912 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00); in stv0367ddb_setup_ter()
2913 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x00); in stv0367ddb_setup_ter()
2914 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x00); /* R367CAB_CTRL_1 */ in stv0367ddb_setup_ter()
2915 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x00); /* R367CAB_CTRL_2 */ in stv0367ddb_setup_ter()
2916 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00); in stv0367ddb_setup_ter()
2917 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00); in stv0367ddb_setup_ter()
2921 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x89); in stv0367ddb_setup_ter()
2922 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */ in stv0367ddb_setup_ter()
2926 stv0367_writereg(state, R367TER_ANACTRL, 0x0D); in stv0367ddb_setup_ter()
2927 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); /* Set OFDM */ in stv0367ddb_setup_ter()
2934 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ddb_setup_ter()
2941 stv0367_writereg(state, R367TER_DEBUG_LT4, 0x00); in stv0367ddb_setup_cab()
2942 stv0367_writereg(state, R367TER_DEBUG_LT5, 0x01); in stv0367ddb_setup_cab()
2943 stv0367_writereg(state, R367TER_DEBUG_LT6, 0x06); /* R367CAB_CTRL_1 */ in stv0367ddb_setup_cab()
2944 stv0367_writereg(state, R367TER_DEBUG_LT7, 0x03); /* R367CAB_CTRL_2 */ in stv0367ddb_setup_cab()
2945 stv0367_writereg(state, R367TER_DEBUG_LT8, 0x00); in stv0367ddb_setup_cab()
2946 stv0367_writereg(state, R367TER_DEBUG_LT9, 0x00); in stv0367ddb_setup_cab()
2950 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8B); in stv0367ddb_setup_cab()
2952 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); in stv0367ddb_setup_cab()
2956 stv0367_writereg(state, R367TER_ANACTRL, 0x0D); in stv0367ddb_setup_cab()
2958 stv0367_writereg(state, R367TER_TOPCTRL, 0x10); in stv0367ddb_setup_cab()
2965 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ddb_setup_cab()
3156 stv0367_writereg(state, R367TER_TOPCTRL, 0x10); in stv0367ddb_init()
3165 stv0367_writereg(state, R367TER_TOPCTRL, 0x00); in stv0367ddb_init()
3169 stv0367_writereg(state, R367TER_GAIN_SRC1, 0x2A); in stv0367ddb_init()
3170 stv0367_writereg(state, R367TER_GAIN_SRC2, 0xD6); in stv0367ddb_init()
3171 stv0367_writereg(state, R367TER_INC_DEROT1, 0x55); in stv0367ddb_init()
3172 stv0367_writereg(state, R367TER_INC_DEROT2, 0x55); in stv0367ddb_init()
3173 stv0367_writereg(state, R367TER_TRL_CTL, 0x14); in stv0367ddb_init()
3174 stv0367_writereg(state, R367TER_TRL_NOMRATE1, 0xAE); in stv0367ddb_init()
3175 stv0367_writereg(state, R367TER_TRL_NOMRATE2, 0x56); in stv0367ddb_init()
3176 stv0367_writereg(state, R367TER_FEPATH_CFG, 0x0); in stv0367ddb_init()
3180 stv0367_writereg(state, R367TER_TSCFGH, 0x70); in stv0367ddb_init()
3181 stv0367_writereg(state, R367TER_TSCFGM, 0xC0); in stv0367ddb_init()
3182 stv0367_writereg(state, R367TER_TSCFGL, 0x20); in stv0367ddb_init()
3183 stv0367_writereg(state, R367TER_TSSPEED, 0x40); /* Fixed at 54 MHz */ in stv0367ddb_init()
3185 stv0367_writereg(state, R367TER_TSCFGH, 0x71); in stv0367ddb_init()
3186 stv0367_writereg(state, R367TER_TSCFGH, 0x70); in stv0367ddb_init()
3188 stv0367_writereg(state, R367TER_TOPCTRL, 0x10); in stv0367ddb_init()
3191 stv0367_writereg(state, R367TER_AGC12C, 0x01); /* AGC Pin setup */ in stv0367ddb_init()
3193 stv0367_writereg(state, R367TER_AGCCTRL1, 0x8A); in stv0367ddb_init()
3198 stv0367_writereg(state, R367CAB_OUTFORMAT_0, 0x85); in stv0367ddb_init()
3201 stv0367_writereg(state, R367TER_ANACTRL, 0x0D); in stv0367ddb_init()
3208 stv0367_writereg(state, R367TER_ANADIGCTRL, 0x8b); in stv0367ddb_init()
3209 stv0367_writereg(state, R367TER_DUAL_AD12, 0x04); /* ADCQ disabled */ in stv0367ddb_init()
3212 stv0367_writereg(state, R367CAB_FSM_SNR2_HTH, 0x23); in stv0367ddb_init()
3214 stv0367_writereg(state, R367CAB_IQ_QAM, 0x01); in stv0367ddb_init()
3216 stv0367_writereg(state, R367CAB_EQU_FFE_LEAKAGE, 0x83); in stv0367ddb_init()
3218 stv0367_writereg(state, R367CAB_IQDEM_ADJ_EN, 0x05); in stv0367ddb_init()
3221 stv0367_writereg(state, R367TER_ANACTRL, 0x00); in stv0367ddb_init()
3223 stv0367_writereg(state, R367TER_I2CRPT, (0x08 | ((5 & 0x07) << 4))); in stv0367ddb_init()