Lines Matching +full:0 +full:x21
242 {DVBT_DAGC_TRG_VAL, 0x39},
243 {DVBT_AGC_TARG_VAL_0, 0x0},
244 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
245 {DVBT_AAGC_LOOP_GAIN, 0x16},
246 {DVBT_LOOP_GAIN2_3_0, 0x6},
247 {DVBT_LOOP_GAIN2_4, 0x1},
248 {DVBT_LOOP_GAIN3, 0x16},
249 {DVBT_VTOP1, 0x35},
250 {DVBT_VTOP2, 0x21},
251 {DVBT_VTOP3, 0x21},
252 {DVBT_KRF1, 0x0},
253 {DVBT_KRF2, 0x40},
254 {DVBT_KRF3, 0x10},
255 {DVBT_KRF4, 0x10},
256 {DVBT_IF_AGC_MIN, 0x80},
257 {DVBT_IF_AGC_MAX, 0x7f},
258 {DVBT_RF_AGC_MIN, 0x9c},
259 {DVBT_RF_AGC_MAX, 0x7f},
260 {DVBT_POLAR_RF_AGC, 0x0},
261 {DVBT_POLAR_IF_AGC, 0x0},
262 {DVBT_AD7_SETTING, 0xe9f4},
266 {DVBT_DAGC_TRG_VAL, 0x39},
267 {DVBT_AGC_TARG_VAL_0, 0x0},
268 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
269 {DVBT_AAGC_LOOP_GAIN, 0x16},
270 {DVBT_LOOP_GAIN2_3_0, 0x6},
271 {DVBT_LOOP_GAIN2_4, 0x1},
272 {DVBT_LOOP_GAIN3, 0x16},
273 {DVBT_VTOP1, 0x35},
274 {DVBT_VTOP2, 0x21},
275 {DVBT_VTOP3, 0x21},
276 {DVBT_KRF1, 0x0},
277 {DVBT_KRF2, 0x40},
278 {DVBT_KRF3, 0x10},
279 {DVBT_KRF4, 0x10},
280 {DVBT_IF_AGC_MIN, 0x80},
281 {DVBT_IF_AGC_MAX, 0x7f},
282 {DVBT_RF_AGC_MIN, 0x9c},
283 {DVBT_RF_AGC_MAX, 0x7f},
284 {DVBT_POLAR_RF_AGC, 0x0},
285 {DVBT_POLAR_IF_AGC, 0x0},
286 {DVBT_AD7_SETTING, 0xe9f4},
287 {DVBT_OPT_ADC_IQ, 0x1},
288 {DVBT_AD_AVI, 0x0},
289 {DVBT_AD_AVQ, 0x0},
290 {DVBT_SPEC_INV, 0x0},
294 {DVBT_DAGC_TRG_VAL, 0x5a},
295 {DVBT_AGC_TARG_VAL_0, 0x0},
296 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
297 {DVBT_AAGC_LOOP_GAIN, 0x16},
298 {DVBT_LOOP_GAIN2_3_0, 0x6},
299 {DVBT_LOOP_GAIN2_4, 0x1},
300 {DVBT_LOOP_GAIN3, 0x16},
301 {DVBT_VTOP1, 0x35},
302 {DVBT_VTOP2, 0x21},
303 {DVBT_VTOP3, 0x21},
304 {DVBT_KRF1, 0x0},
305 {DVBT_KRF2, 0x40},
306 {DVBT_KRF3, 0x10},
307 {DVBT_KRF4, 0x10},
308 {DVBT_IF_AGC_MIN, 0x80},
309 {DVBT_IF_AGC_MAX, 0x7f},
310 {DVBT_RF_AGC_MIN, 0x80},
311 {DVBT_RF_AGC_MAX, 0x7f},
312 {DVBT_POLAR_RF_AGC, 0x0},
313 {DVBT_POLAR_IF_AGC, 0x0},
314 {DVBT_AD7_SETTING, 0xe9bf},
315 {DVBT_EN_GI_PGA, 0x0},
316 {DVBT_THD_LOCK_UP, 0x0},
317 {DVBT_THD_LOCK_DW, 0x0},
318 {DVBT_THD_UP1, 0x11},
319 {DVBT_THD_DW1, 0xef},
320 {DVBT_INTER_CNT_LEN, 0xc},
321 {DVBT_GI_PGA_STATE, 0x0},
322 {DVBT_EN_AGC_PGA, 0x1},
323 {DVBT_IF_AGC_MAN, 0x0},
324 {DVBT_SPEC_INV, 0x0},
328 {DVBT_DAGC_TRG_VAL, 0x5a},
329 {DVBT_AGC_TARG_VAL_0, 0x0},
330 {DVBT_AGC_TARG_VAL_8_1, 0x5a},
331 {DVBT_AAGC_LOOP_GAIN, 0x18},
332 {DVBT_LOOP_GAIN2_3_0, 0x8},
333 {DVBT_LOOP_GAIN2_4, 0x1},
334 {DVBT_LOOP_GAIN3, 0x18},
335 {DVBT_VTOP1, 0x35},
336 {DVBT_VTOP2, 0x21},
337 {DVBT_VTOP3, 0x21},
338 {DVBT_KRF1, 0x0},
339 {DVBT_KRF2, 0x40},
340 {DVBT_KRF3, 0x10},
341 {DVBT_KRF4, 0x10},
342 {DVBT_IF_AGC_MIN, 0x80},
343 {DVBT_IF_AGC_MAX, 0x7f},
344 {DVBT_RF_AGC_MIN, 0x80},
345 {DVBT_RF_AGC_MAX, 0x7f},
346 {DVBT_POLAR_RF_AGC, 0x0},
347 {DVBT_POLAR_IF_AGC, 0x0},
348 {DVBT_AD7_SETTING, 0xe9d4},
349 {DVBT_EN_GI_PGA, 0x0},
350 {DVBT_THD_LOCK_UP, 0x0},
351 {DVBT_THD_LOCK_DW, 0x0},
352 {DVBT_THD_UP1, 0x14},
353 {DVBT_THD_DW1, 0xec},
354 {DVBT_INTER_CNT_LEN, 0xc},
355 {DVBT_GI_PGA_STATE, 0x0},
356 {DVBT_EN_AGC_PGA, 0x1},
357 {DVBT_REG_GPE, 0x1},
358 {DVBT_REG_GPO, 0x1},
359 {DVBT_REG_MONSEL, 0x1},
360 {DVBT_REG_MON, 0x1},
361 {DVBT_REG_4MSEL, 0x0},
362 {DVBT_SPEC_INV, 0x0},
366 {DVBT_DAGC_TRG_VAL, 0x39},
367 {DVBT_AGC_TARG_VAL_0, 0x0},
368 {DVBT_AGC_TARG_VAL_8_1, 0x40},
369 {DVBT_AAGC_LOOP_GAIN, 0x16},
370 {DVBT_LOOP_GAIN2_3_0, 0x8},
371 {DVBT_LOOP_GAIN2_4, 0x1},
372 {DVBT_LOOP_GAIN3, 0x18},
373 {DVBT_VTOP1, 0x35},
374 {DVBT_VTOP2, 0x21},
375 {DVBT_VTOP3, 0x21},
376 {DVBT_KRF1, 0x0},
377 {DVBT_KRF2, 0x40},
378 {DVBT_KRF3, 0x10},
379 {DVBT_KRF4, 0x10},
380 {DVBT_IF_AGC_MIN, 0x80},
381 {DVBT_IF_AGC_MAX, 0x7f},
382 {DVBT_RF_AGC_MIN, 0x80},
383 {DVBT_RF_AGC_MAX, 0x7f},
384 {DVBT_POLAR_RF_AGC, 0x0},
385 {DVBT_POLAR_IF_AGC, 0x0},
386 {DVBT_AD7_SETTING, 0xe9f4},
387 {DVBT_SPEC_INV, 0x1},
391 {DVBT_DAGC_TRG_VAL, 0x39},
392 {DVBT_AGC_TARG_VAL_0, 0x0},
393 {DVBT_AGC_TARG_VAL_8_1, 0x40},
394 {DVBT_AAGC_LOOP_GAIN, 0x16},
395 {DVBT_LOOP_GAIN2_3_0, 0x8},
396 {DVBT_LOOP_GAIN2_4, 0x1},
397 {DVBT_LOOP_GAIN3, 0x18},
398 {DVBT_VTOP1, 0x35},
399 {DVBT_VTOP2, 0x21},
400 {DVBT_VTOP3, 0x21},
401 {DVBT_KRF1, 0x0},
402 {DVBT_KRF2, 0x40},
403 {DVBT_KRF3, 0x10},
404 {DVBT_KRF4, 0x10},
405 {DVBT_IF_AGC_MIN, 0x80},
406 {DVBT_IF_AGC_MAX, 0x7f},
407 {DVBT_RF_AGC_MIN, 0x80},
408 {DVBT_RF_AGC_MAX, 0x7f},
409 {DVBT_POLAR_RF_AGC, 0x0},
410 {DVBT_POLAR_IF_AGC, 0x0},
411 {DVBT_AD7_SETTING, 0xe9f4},
412 {DVBT_SPEC_INV, 0x0},