45 } while (0)
47 #define deb_info(args...)  dprintk(0x01, args)
58 		.flags = 0,  in m88rs2000_writereg()
66 		deb_info("%s: writereg error (reg == 0x%02x, val == 0x%02x, ret == %i)\n",  in m88rs2000_writereg()
69 	return (ret != 1) ? -EREMOTEIO : 0;  in m88rs2000_writereg()
76 	u8 b1[] = { 0 };  in m88rs2000_readreg()
81 			.flags = 0,  in m88rs2000_readreg()
95 		deb_info("%s: readreg error (reg == 0x%02x, ret == %i)\n",  in m88rs2000_readreg()
98 	return b1[0];  in m88rs2000_readreg()
106 	/* Must not be 0x00 or 0xff */  in m88rs2000_get_mclk()
107 	reg = m88rs2000_readreg(state, 0x86);  in m88rs2000_get_mclk()
108 	if (!reg || reg == 0xff)  in m88rs2000_get_mclk()
109 		return 0;  in m88rs2000_get_mclk()
132 	if (tmp < 0)  in m88rs2000_set_carrieroffset()
136 	ret = m88rs2000_writereg(state, 0x9c, (u8)(tmp >> 4));  in m88rs2000_set_carrieroffset()
138 	reg = m88rs2000_readreg(state, 0x9d);  in m88rs2000_set_carrieroffset()
139 	reg &= 0xf;  in m88rs2000_set_carrieroffset()
140 	reg |= (u8)(tmp & 0xf) << 4;  in m88rs2000_set_carrieroffset()
142 	ret |= m88rs2000_writereg(state, 0x9d, reg);  in m88rs2000_set_carrieroffset()
167 	b[0] = (u8) (temp >> 16) & 0xff;  in m88rs2000_set_symbolrate()
168 	b[1] = (u8) (temp >> 8) & 0xff;  in m88rs2000_set_symbolrate()
169 	b[2] = (u8) temp & 0xff;  in m88rs2000_set_symbolrate()
171 	ret = m88rs2000_writereg(state, 0x93, b[2]);  in m88rs2000_set_symbolrate()
172 	ret |= m88rs2000_writereg(state, 0x94, b[1]);  in m88rs2000_set_symbolrate()
173 	ret |= m88rs2000_writereg(state, 0x95, b[0]);  in m88rs2000_set_symbolrate()
176 		ret |= m88rs2000_writereg(state, 0xa0, 0x20);  in m88rs2000_set_symbolrate()
178 		ret |= m88rs2000_writereg(state, 0xa0, 0x60);  in m88rs2000_set_symbolrate()
180 	ret |= m88rs2000_writereg(state, 0xa1, 0xe0);  in m88rs2000_set_symbolrate()
183 		ret |= m88rs2000_writereg(state, 0xa3, 0x20);  in m88rs2000_set_symbolrate()
185 		ret |= m88rs2000_writereg(state, 0xa3, 0x98);  in m88rs2000_set_symbolrate()
187 		ret |= m88rs2000_writereg(state, 0xa3, 0x90);  in m88rs2000_set_symbolrate()
201 	m88rs2000_writereg(state, 0x9a, 0x30);  in m88rs2000_send_diseqc_msg()
202 	reg = m88rs2000_readreg(state, 0xb2);  in m88rs2000_send_diseqc_msg()
203 	reg &= 0x3f;  in m88rs2000_send_diseqc_msg()
204 	m88rs2000_writereg(state, 0xb2, reg);  in m88rs2000_send_diseqc_msg()
205 	for (i = 0; i <  m->msg_len; i++)  in m88rs2000_send_diseqc_msg()
206 		m88rs2000_writereg(state, 0xb3 + i, m->msg[i]);  in m88rs2000_send_diseqc_msg()
208 	reg = m88rs2000_readreg(state, 0xb1);  in m88rs2000_send_diseqc_msg()
209 	reg &= 0x87;  in m88rs2000_send_diseqc_msg()
210 	reg |= ((m->msg_len - 1) << 3) | 0x07;  in m88rs2000_send_diseqc_msg()
211 	reg &= 0x7f;  in m88rs2000_send_diseqc_msg()
212 	m88rs2000_writereg(state, 0xb1, reg);  in m88rs2000_send_diseqc_msg()
214 	for (i = 0; i < 15; i++) {  in m88rs2000_send_diseqc_msg()
215 		if ((m88rs2000_readreg(state, 0xb1) & 0x40) == 0x0)  in m88rs2000_send_diseqc_msg()
220 	reg = m88rs2000_readreg(state, 0xb1);  in m88rs2000_send_diseqc_msg()
221 	if ((reg & 0x40) > 0x0) {  in m88rs2000_send_diseqc_msg()
222 		reg &= 0x7f;  in m88rs2000_send_diseqc_msg()
223 		reg |= 0x40;  in m88rs2000_send_diseqc_msg()
224 		m88rs2000_writereg(state, 0xb1, reg);  in m88rs2000_send_diseqc_msg()
227 	reg = m88rs2000_readreg(state, 0xb2);  in m88rs2000_send_diseqc_msg()
228 	reg &= 0x3f;  in m88rs2000_send_diseqc_msg()
229 	reg |= 0x80;  in m88rs2000_send_diseqc_msg()
230 	m88rs2000_writereg(state, 0xb2, reg);  in m88rs2000_send_diseqc_msg()
231 	m88rs2000_writereg(state, 0x9a, 0xb0);  in m88rs2000_send_diseqc_msg()
234 	return 0;  in m88rs2000_send_diseqc_msg()
243 	m88rs2000_writereg(state, 0x9a, 0x30);  in m88rs2000_send_diseqc_burst()
245 	reg0 = m88rs2000_readreg(state, 0xb1);  in m88rs2000_send_diseqc_burst()
246 	reg1 = m88rs2000_readreg(state, 0xb2);  in m88rs2000_send_diseqc_burst()
248 	m88rs2000_writereg(state, 0xb2, reg1);  in m88rs2000_send_diseqc_burst()
249 	m88rs2000_writereg(state, 0xb1, reg0);  in m88rs2000_send_diseqc_burst()
250 	m88rs2000_writereg(state, 0x9a, 0xb0);  in m88rs2000_send_diseqc_burst()
252 	return 0;  in m88rs2000_send_diseqc_burst()
260 	m88rs2000_writereg(state, 0x9a, 0x30);  in m88rs2000_set_tone()
261 	reg0 = m88rs2000_readreg(state, 0xb1);  in m88rs2000_set_tone()
262 	reg1 = m88rs2000_readreg(state, 0xb2);  in m88rs2000_set_tone()
264 	reg1 &= 0x3f;  in m88rs2000_set_tone()
268 		reg0 |= 0x4;  in m88rs2000_set_tone()
269 		reg0 &= 0xbc;  in m88rs2000_set_tone()
272 		reg1 |= 0x80;  in m88rs2000_set_tone()
277 	m88rs2000_writereg(state, 0xb2, reg1);  in m88rs2000_set_tone()
278 	m88rs2000_writereg(state, 0xb1, reg0);  in m88rs2000_set_tone()
279 	m88rs2000_writereg(state, 0x9a, 0xb0);  in m88rs2000_set_tone()
280 	return 0;  in m88rs2000_set_tone()
290 	{DEMOD_WRITE, 0x9a, 0x30},
291 	{DEMOD_WRITE, 0x00, 0x01},
292 	{WRITE_DELAY, 0x19, 0x00},
293 	{DEMOD_WRITE, 0x00, 0x00},
294 	{DEMOD_WRITE, 0x9a, 0xb0},
295 	{DEMOD_WRITE, 0x81, 0xc1},
296 	{DEMOD_WRITE, 0x81, 0x81},
297 	{DEMOD_WRITE, 0x86, 0xc6},
298 	{DEMOD_WRITE, 0x9a, 0x30},
299 	{DEMOD_WRITE, 0xf0, 0x22},
300 	{DEMOD_WRITE, 0xf1, 0xbf},
301 	{DEMOD_WRITE, 0xb0, 0x45},
302 	{DEMOD_WRITE, 0xb2, 0x01}, /* set voltage pin always set 1*/
303 	{DEMOD_WRITE, 0x9a, 0xb0},
304 	{0xff, 0xaa, 0xff}
308 	{DEMOD_WRITE, 0x9a, 0x30},
309 	{DEMOD_WRITE, 0xb0, 0x00},
310 	{DEMOD_WRITE, 0xf1, 0x89},
311 	{DEMOD_WRITE, 0x00, 0x01},
312 	{DEMOD_WRITE, 0x9a, 0xb0},
313 	{DEMOD_WRITE, 0x81, 0x81},
314 	{0xff, 0xaa, 0xff}
318 	{DEMOD_WRITE, 0x00, 0x01},
319 	{DEMOD_WRITE, 0x20, 0x81},
320 	{DEMOD_WRITE, 0x21, 0x80},
321 	{DEMOD_WRITE, 0x10, 0x33},
322 	{DEMOD_WRITE, 0x11, 0x44},
323 	{DEMOD_WRITE, 0x12, 0x07},
324 	{DEMOD_WRITE, 0x18, 0x20},
325 	{DEMOD_WRITE, 0x28, 0x04},
326 	{DEMOD_WRITE, 0x29, 0x8e},
327 	{DEMOD_WRITE, 0x3b, 0xff},
328 	{DEMOD_WRITE, 0x32, 0x10},
329 	{DEMOD_WRITE, 0x33, 0x02},
330 	{DEMOD_WRITE, 0x34, 0x30},
331 	{DEMOD_WRITE, 0x35, 0xff},
332 	{DEMOD_WRITE, 0x38, 0x50},
333 	{DEMOD_WRITE, 0x39, 0x68},
334 	{DEMOD_WRITE, 0x3c, 0x7f},
335 	{DEMOD_WRITE, 0x3d, 0x0f},
336 	{DEMOD_WRITE, 0x45, 0x20},
337 	{DEMOD_WRITE, 0x46, 0x24},
338 	{DEMOD_WRITE, 0x47, 0x7c},
339 	{DEMOD_WRITE, 0x48, 0x16},
340 	{DEMOD_WRITE, 0x49, 0x04},
341 	{DEMOD_WRITE, 0x4a, 0x01},
342 	{DEMOD_WRITE, 0x4b, 0x78},
343 	{DEMOD_WRITE, 0X4d, 0xd2},
344 	{DEMOD_WRITE, 0x4e, 0x6d},
345 	{DEMOD_WRITE, 0x50, 0x30},
346 	{DEMOD_WRITE, 0x51, 0x30},
347 	{DEMOD_WRITE, 0x54, 0x7b},
348 	{DEMOD_WRITE, 0x56, 0x09},
349 	{DEMOD_WRITE, 0x58, 0x59},
350 	{DEMOD_WRITE, 0x59, 0x37},
351 	{DEMOD_WRITE, 0x63, 0xfa},
352 	{0xff, 0xaa, 0xff}
356 	{DEMOD_WRITE, 0x97, 0x04},
357 	{DEMOD_WRITE, 0x99, 0x77},
358 	{DEMOD_WRITE, 0x9b, 0x64},
359 	{DEMOD_WRITE, 0x9e, 0x00},
360 	{DEMOD_WRITE, 0x9f, 0xf8},
361 	{DEMOD_WRITE, 0x98, 0xff},
362 	{DEMOD_WRITE, 0xc0, 0x0f},
363 	{DEMOD_WRITE, 0x89, 0x01},
364 	{DEMOD_WRITE, 0x00, 0x00},
365 	{WRITE_DELAY, 0x0a, 0x00},
366 	{DEMOD_WRITE, 0x00, 0x01},
367 	{DEMOD_WRITE, 0x00, 0x00},
368 	{DEMOD_WRITE, 0x9a, 0xb0},
369 	{0xff, 0xaa, 0xff}
375 	int ret = 0;  in m88rs2000_tab_set()
380 	for (i = 0; i < 255; i++) {  in m88rs2000_tab_set()
382 		case 0x01:  in m88rs2000_tab_set()
386 		case 0x10:  in m88rs2000_tab_set()
387 			if (tab[i].reg > 0)  in m88rs2000_tab_set()
390 		case 0xff:  in m88rs2000_tab_set()
391 			if (tab[i].reg == 0xaa && tab[i].val == 0xff)  in m88rs2000_tab_set()
392 				return 0;  in m88rs2000_tab_set()
394 		case 0x00:  in m88rs2000_tab_set()
399 		if (ret < 0)  in m88rs2000_tab_set()
402 	return 0;  in m88rs2000_tab_set()
411 	data = m88rs2000_readreg(state, 0xb2);  in m88rs2000_set_voltage()
412 	data |= 0x03; /* bit0 V/H, bit1 off/on */  in m88rs2000_set_voltage()
416 		data &= ~0x03;  in m88rs2000_set_voltage()
419 		data &= ~0x03;  in m88rs2000_set_voltage()
420 		data |= 0x01;  in m88rs2000_set_voltage()
426 	m88rs2000_writereg(state, 0xb2, data);  in m88rs2000_set_voltage()
428 	return 0;  in m88rs2000_set_voltage()
460 	u8 reg = m88rs2000_readreg(state, 0x8c);  in m88rs2000_read_status()
462 	*status = 0;  in m88rs2000_read_status()
464 	if ((reg & 0xee) == 0xee) {  in m88rs2000_read_status()
470 	return 0;  in m88rs2000_read_status()
478 	m88rs2000_writereg(state, 0x9a, 0x30);  in m88rs2000_read_ber()
479 	tmp0 = m88rs2000_readreg(state, 0xd8);  in m88rs2000_read_ber()
480 	if ((tmp0 & 0x10) != 0) {  in m88rs2000_read_ber()
481 		m88rs2000_writereg(state, 0x9a, 0xb0);  in m88rs2000_read_ber()
482 		*ber = 0xffffffff;  in m88rs2000_read_ber()
483 		return 0;  in m88rs2000_read_ber()
486 	*ber = (m88rs2000_readreg(state, 0xd7) << 8) |  in m88rs2000_read_ber()
487 		m88rs2000_readreg(state, 0xd6);  in m88rs2000_read_ber()
489 	tmp1 = m88rs2000_readreg(state, 0xd9);  in m88rs2000_read_ber()
490 	m88rs2000_writereg(state, 0xd9, (tmp1 & ~7) | 4);  in m88rs2000_read_ber()
492 	m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);  in m88rs2000_read_ber()
493 	m88rs2000_writereg(state, 0xd8, (tmp0 & ~8) | 0x30);  in m88rs2000_read_ber()
494 	m88rs2000_writereg(state, 0x9a, 0xb0);  in m88rs2000_read_ber()
496 	return 0;  in m88rs2000_read_ber()
505 	return 0;  in m88rs2000_read_signal_strength()
512 	*snr = 512 * m88rs2000_readreg(state, 0x65);  in m88rs2000_read_snr()
514 	return 0;  in m88rs2000_read_snr()
522 	*ucblocks = (m88rs2000_readreg(state, 0xd5) << 8) |  in m88rs2000_read_ucblocks()
523 			m88rs2000_readreg(state, 0xd4);  in m88rs2000_read_ucblocks()
524 	tmp = m88rs2000_readreg(state, 0xd8);  in m88rs2000_read_ucblocks()
525 	m88rs2000_writereg(state, 0xd8, tmp & ~0x20);  in m88rs2000_read_ucblocks()
527 	m88rs2000_writereg(state, 0xd8, tmp | 0x20);  in m88rs2000_read_ucblocks()
528 	m88rs2000_writereg(state, 0xd8, tmp | 0x20);  in m88rs2000_read_ucblocks()
530 	return 0;  in m88rs2000_read_ucblocks()
541 		fec_set = 0x8;  in m88rs2000_set_fec()
544 		fec_set = 0x10;  in m88rs2000_set_fec()
547 		fec_set = 0x20;  in m88rs2000_set_fec()
550 		fec_set = 0x40;  in m88rs2000_set_fec()
553 		fec_set = 0x80;  in m88rs2000_set_fec()
557 		fec_set = 0x0;  in m88rs2000_set_fec()
560 	reg = m88rs2000_readreg(state, 0x70);  in m88rs2000_set_fec()
561 	reg &= 0x7;  in m88rs2000_set_fec()
562 	ret = m88rs2000_writereg(state, 0x70, reg | fec_set);  in m88rs2000_set_fec()
564 	ret |= m88rs2000_writereg(state, 0x76, 0x8);  in m88rs2000_set_fec()
572 	m88rs2000_writereg(state, 0x9a, 0x30);  in m88rs2000_get_fec()
573 	reg = m88rs2000_readreg(state, 0x76);  in m88rs2000_get_fec()
574 	m88rs2000_writereg(state, 0x9a, 0xb0);  in m88rs2000_get_fec()
576 	reg &= 0xf0;  in m88rs2000_get_fec()
580 	case 0x4:  in m88rs2000_get_fec()
582 	case 0x3:  in m88rs2000_get_fec()
584 	case 0x2:  in m88rs2000_get_fec()
586 	case 0x1:  in m88rs2000_get_fec()
588 	case 0x0:  in m88rs2000_get_fec()
601 	enum fe_status status = 0;  in m88rs2000_set_frontend()
602 	int i, ret = 0;  in m88rs2000_set_frontend()
604 	s16 offset = 0;  in m88rs2000_set_frontend()
607 	state->no_lock_count = 0;  in m88rs2000_set_frontend()
619 	if (ret < 0)  in m88rs2000_set_frontend()
625 		if (ret < 0)  in m88rs2000_set_frontend()
630 		offset = 0;  in m88rs2000_set_frontend()
636 		ret = m88rs2000_writereg(state, 0x86, 0xc2);  in m88rs2000_set_frontend()
638 		ret = m88rs2000_writereg(state, 0x86, 0xc6);  in m88rs2000_set_frontend()
641 	if (ret < 0)  in m88rs2000_set_frontend()
646 		ret = m88rs2000_writereg(state, 0xf1, 0xa4);  in m88rs2000_set_frontend()
648 		ret = m88rs2000_writereg(state, 0xf1, 0xbf);  in m88rs2000_set_frontend()
651 	if (ret < 0)  in m88rs2000_set_frontend()
656 	ret |= m88rs2000_writereg(state, 0x85, 0x1);  in m88rs2000_set_frontend()
657 	ret |= m88rs2000_writereg(state, 0x8a, 0xbf);  in m88rs2000_set_frontend()
658 	ret |= m88rs2000_writereg(state, 0x8d, 0x1e);  in m88rs2000_set_frontend()
659 	ret |= m88rs2000_writereg(state, 0x90, 0xf1);  in m88rs2000_set_frontend()
660 	ret |= m88rs2000_writereg(state, 0x91, 0x08);  in m88rs2000_set_frontend()
662 	if (ret < 0)  in m88rs2000_set_frontend()
667 	if (ret < 0)  in m88rs2000_set_frontend()
672 	if (ret < 0)  in m88rs2000_set_frontend()
675 	for (i = 0; i < 25; i++) {  in m88rs2000_set_frontend()
676 		reg = m88rs2000_readreg(state, 0x8c);  in m88rs2000_set_frontend()
677 		if ((reg & 0xee) == 0xee) {  in m88rs2000_set_frontend()
683 			reg = m88rs2000_readreg(state, 0x70);  in m88rs2000_set_frontend()
684 			reg ^= 0x4;  in m88rs2000_set_frontend()
685 			m88rs2000_writereg(state, 0x70, reg);  in m88rs2000_set_frontend()
686 			state->no_lock_count = 0;  in m88rs2000_set_frontend()
694 		reg = m88rs2000_readreg(state, 0x65);  in m88rs2000_set_frontend()
699 	return 0;  in m88rs2000_set_frontend()
710 	return 0;  in m88rs2000_get_frontend()
726 	return 0;  in m88rs2000_get_tune_settings()
734 		m88rs2000_writereg(state, 0x81, 0x84);  in m88rs2000_i2c_gate_ctrl()
736 		m88rs2000_writereg(state, 0x81, 0x81);  in m88rs2000_i2c_gate_ctrl()
738 	return 0;  in m88rs2000_i2c_gate_ctrl()
796 	state->tuner_frequency = 0;  in m88rs2000_attach()
797 	state->symbol_rate = 0;  in m88rs2000_attach()
798 	state->fec_inner = 0;  in m88rs2000_attach()