32 	} while (0)
44 	struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 };  in l64781_writereg()
50 	return (ret != 1) ? -1 : 0;  in l64781_writereg()
57 	u8 b1 [] = { 0 };  in l64781_readreg()
58 …struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 …  in l64781_readreg()
65 	return b1[0];  in l64781_readreg()
70 	l64781_writereg (state, 0x2a, 0x00);  in apply_tps()
71 	l64781_writereg (state, 0x2a, 0x01);  in apply_tps()
78 	l64781_writereg (state, 0x2a, 0x02);  in apply_tps()
86 	l64781_writereg (state, 0x07, 0x9e); /* stall AFC */  in reset_afc()
87 	l64781_writereg (state, 0x08, 0);    /* AFC INIT FREQ */  in reset_afc()
88 	l64781_writereg (state, 0x09, 0);  in reset_afc()
89 	l64781_writereg (state, 0x0a, 0);  in reset_afc()
90 	l64781_writereg (state, 0x07, 0x8e);  in reset_afc()
91 	l64781_writereg (state, 0x0e, 0);    /* AGC gain to zero in beginning */  in reset_afc()
92 	l64781_writereg (state, 0x11, 0x80); /* stall TIM */  in reset_afc()
93 	l64781_writereg (state, 0x10, 0);    /* TIM_OFFSET_LSB */  in reset_afc()
94 	l64781_writereg (state, 0x12, 0);  in reset_afc()
95 	l64781_writereg (state, 0x13, 0);  in reset_afc()
96 	l64781_writereg (state, 0x11, 0x00);  in reset_afc()
101 	u8 buf [] = { 0x06 };  in reset_and_configure()
102 	struct i2c_msg msg = { .addr = 0x00, .flags = 0, .buf = buf, .len = 1 };  in reset_and_configure()
103 	// NOTE: this is correct in writing to address 0x00  in reset_and_configure()
105 	return (i2c_transfer(state->i2c, &msg, 1) == 1) ? 0 : -ENODEV;  in reset_and_configure()
113 	static const u8 fec_tab[] = { 7, 0, 1, 2, 9, 3, 10, 4 };  in apply_frontend_param()
115 	static const u8 qam_tab [] = { 2, 4, 0, 6 };  in apply_frontend_param()
120 /*	u32 ddfs_offset_variable = 0x6000-((1000000UL+ppm)/ */  in apply_frontend_param()
145 		if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0);  in apply_frontend_param()
179 	ddfs_offset_fixed = 0x4000-(ppm<<16)/bw/1000000;  in apply_frontend_param()
183 			bw & 0xFFFFFF);  in apply_frontend_param()
205 	l64781_writereg (state, 0x04, val0x04);  in apply_frontend_param()
206 	l64781_writereg (state, 0x05, val0x05);  in apply_frontend_param()
207 	l64781_writereg (state, 0x06, val0x06);  in apply_frontend_param()
212 	l64781_writereg (state, 0x15,  in apply_frontend_param()
214 	l64781_writereg (state, 0x16, init_freq & 0xff);  in apply_frontend_param()
215 	l64781_writereg (state, 0x17, (init_freq >> 8) & 0xff);  in apply_frontend_param()
216 	l64781_writereg (state, 0x18, (init_freq >> 16) & 0xff);  in apply_frontend_param()
218 	l64781_writereg (state, 0x1b, spi_bias & 0xff);  in apply_frontend_param()
219 	l64781_writereg (state, 0x1c, (spi_bias >> 8) & 0xff);  in apply_frontend_param()
220 	l64781_writereg (state, 0x1d, ((spi_bias >> 16) & 0x7f) |  in apply_frontend_param()
221 		(p->inversion == INVERSION_ON ? 0x80 : 0x00));  in apply_frontend_param()
223 	l64781_writereg (state, 0x22, ddfs_offset_fixed & 0xff);  in apply_frontend_param()
224 	l64781_writereg (state, 0x23, (ddfs_offset_fixed >> 8) & 0x3f);  in apply_frontend_param()
226 	l64781_readreg (state, 0x00);  /*  clear interrupt registers... */  in apply_frontend_param()
227 	l64781_readreg (state, 0x01);  /*  dto. */  in apply_frontend_param()
231 	return 0;  in apply_frontend_param()
241 	tmp = l64781_readreg(state, 0x04);  in get_frontend()
243 	case 0:  in get_frontend()
257 	case 0:  in get_frontend()
267 	tmp = l64781_readreg(state, 0x05);  in get_frontend()
269 	case 0:  in get_frontend()
288 	case 0:  in get_frontend()
307 	tmp = l64781_readreg(state, 0x06);  in get_frontend()
309 	case 0:  in get_frontend()
322 	case 0:  in get_frontend()
339 	tmp = l64781_readreg (state, 0x1d);  in get_frontend()
340 	p->inversion = (tmp & 0x80) ? INVERSION_ON : INVERSION_OFF;  in get_frontend()
342 	tmp = (int) (l64781_readreg (state, 0x08) |  in get_frontend()
343 		     (l64781_readreg (state, 0x09) << 8) |  in get_frontend()
344 		     (l64781_readreg (state, 0x0a) << 16));  in get_frontend()
347 	return 0;  in get_frontend()
353 	int sync = l64781_readreg (state, 0x32);  in l64781_read_status()
354 	int gain = l64781_readreg (state, 0x0e);  in l64781_read_status()
356 	l64781_readreg (state, 0x00);  /*  clear interrupt registers... */  in l64781_read_status()
357 	l64781_readreg (state, 0x01);  /*  dto. */  in l64781_read_status()
359 	*status = 0;  in l64781_read_status()
364 	if (sync & 0x02) /* VCXO locked, this criteria should be ok */  in l64781_read_status()
367 	if (sync & 0x20)  in l64781_read_status()
370 	if (sync & 0x40)  in l64781_read_status()
373 	if (sync == 0x7f)  in l64781_read_status()
376 	return 0;  in l64781_read_status()
383 	/*   XXX FIXME: set up counting period (reg 0x26...0x28)  in l64781_read_ber()
385 	*ber = l64781_readreg (state, 0x39)  in l64781_read_ber()
386 	    | (l64781_readreg (state, 0x3a) << 8);  in l64781_read_ber()
388 	return 0;  in l64781_read_ber()
395 	u8 gain = l64781_readreg (state, 0x0e);  in l64781_read_signal_strength()
398 	return 0;  in l64781_read_signal_strength()
405 	u8 avg_quality = 0xff - l64781_readreg (state, 0x33);  in l64781_read_snr()
408 	return 0;  in l64781_read_snr()
415 	*ucblocks = l64781_readreg (state, 0x37)  in l64781_read_ucblocks()
416 	   | (l64781_readreg (state, 0x38) << 8);  in l64781_read_ucblocks()
418 	return 0;  in l64781_read_ucblocks()
426 	return l64781_writereg (state, 0x3e, 0x5a);  in l64781_sleep()
436 	l64781_writereg (state, 0x3e, 0xa5);  in l64781_init()
439 	l64781_writereg (state, 0x2a, 0x04);  in l64781_init()
440 	l64781_writereg (state, 0x2a, 0x00);  in l64781_init()
444 	l64781_writereg (state, 0x07, 0x8e);  in l64781_init()
447 	l64781_writereg (state, 0x0b, 0x81);  in l64781_init()
450 	l64781_writereg (state, 0x0c, 0x84);  in l64781_init()
453 	l64781_writereg (state, 0x0d, 0x8c);  in l64781_init()
458 	/*l64781_writereg (state, 0x19, 0x92);*/  in l64781_init()
461 	l64781_writereg (state, 0x1e, 0x09);  in l64781_init()
465 		state->first = 0;  in l64781_init()
469 	return 0;  in l64781_init()
476 	fesettings->step_size = 0;  in l64781_get_tune_settings()
477 	fesettings->max_drift = 0;  in l64781_get_tune_settings()
478 	return 0;  in l64781_get_tune_settings()
494 	u8 b0 [] = { 0x1a };  in l64781_attach()
495 	u8 b1 [] = { 0x00 };  in l64781_attach()
496 	struct i2c_msg msg [] = { { .addr = config->demod_address, .flags = 0, .buf = b0, .len = 1 },  in l64781_attach()
512 	if (reset_and_configure(state) < 0) {  in l64781_attach()
524 	reg0x3e = l64781_readreg(state, 0x3e);  in l64781_attach()
526 	/* Reading the POWER_DOWN register always returns 0 */  in l64781_attach()
527 	if (reg0x3e != 0) {  in l64781_attach()
533 	l64781_writereg (state, 0x3e, 0x5a);  in l64781_attach()
535 	/* Responds to all reads with 0 */  in l64781_attach()
536 	if (l64781_readreg(state, 0x1a) != 0) {  in l64781_attach()
542 	l64781_writereg (state, 0x3e, 0xa5);  in l64781_attach()
545 	if (l64781_readreg(state, 0x1a) != 0xa1) {  in l64781_attach()
556 	if (reg0x3e >= 0)  in l64781_attach()
557 		l64781_writereg (state, 0x3e, reg0x3e);  /* restore reg 0x3e */  in l64781_attach()