Lines Matching defs:drxk_state
211 struct drxk_state { struct
212 struct dvb_frontend frontend;
213 struct dtv_frontend_properties props;
214 struct device *dev;
216 struct i2c_adapter *i2c;
217 u8 demod_address;
218 void *priv;
220 struct mutex mutex;
245 enum e_drxk_state m_drxk_state; /* State of Drxk (init,stopped,started) */ argument
246 enum operation_mode m_operation_mode; /* digital standards */
247 struct s_cfg_agc m_vsb_rf_agc_cfg; /* settings for VSB RF-AGC */
248 struct s_cfg_agc m_vsb_if_agc_cfg; /* settings for VSB IF-AGC */
249 u16 m_vsb_pga_cfg; /* settings for VSB PGA */
250 struct s_cfg_pre_saw m_vsb_pre_saw_cfg; /* settings for pre SAW sense */
251 s32 m_Quality83percent; /* MER level (*0.1 dB) for 83% quality indication */
252 s32 m_Quality93percent; /* MER level (*0.1 dB) for 93% quality indication */
253 bool m_smart_ant_inverted;
254 bool m_b_debug_enable_bridge;
255 … m_b_p_down_open_bridge; /* only open DRXK bridge before power-down once it has been accessed */
256 bool m_b_power_down; /* Power down when not used */
258 u32 m_iqm_fs_rate_ofs; /* frequency shift as written to DRXK register (28bit fixpoint) */
260 bool m_enable_mpeg_output; /* If TRUE, enable MPEG output */
261 bool m_insert_rs_byte; /* If TRUE, insert RS byte */
262 bool m_enable_parallel; /* If TRUE, parallel out otherwise serial */
263 bool m_invert_data; /* If TRUE, invert DATA signals */
264 bool m_invert_err; /* If TRUE, invert ERR signal */
265 bool m_invert_str; /* If TRUE, invert STR signals */
266 bool m_invert_val; /* If TRUE, invert VAL signals */
267 bool m_invert_clk; /* If TRUE, invert CLK signals */
268 bool m_dvbc_static_clk;
269 bool m_dvbt_static_clk; /* If TRUE, static MPEG clockrate will
272 u32 m_dvbt_bitrate;
273 u32 m_dvbc_bitrate;
275 u8 m_ts_data_strength;
276 u8 m_ts_clockk_strength;
278 bool m_itut_annex_c; /* If true, uses ITU-T DVB-C Annex C, instead of Annex A */
280 enum drxmpeg_str_width_t m_width_str; /* MPEG start width */
281 u32 m_mpeg_ts_static_bitrate; /* Maximum bitrate in b/s in case
285 s32 m_mpeg_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */
286 s32 m_demod_lock_time_out; /* WaitForLockStatus Timeout (counts from start time) */
288 bool m_disable_te_ihandling;
290 bool m_rf_agc_pol;
291 bool m_if_agc_pol;
293 struct s_cfg_agc m_atv_rf_agc_cfg; /* settings for ATV RF-AGC */
294 struct s_cfg_agc m_atv_if_agc_cfg; /* settings for ATV IF-AGC */
295 struct s_cfg_pre_saw m_atv_pre_saw_cfg; /* settings for ATV pre SAW sense */
296 bool m_phase_correction_bypass;
297 s16 m_atv_top_vid_peak;
298 u16 m_atv_top_noise_th;
299 enum e_drxk_sif_attenuation m_sif_attenuation;
300 bool m_enable_cvbs_output;
301 bool m_enable_sif_output;
302 bool m_b_mirror_freq_spect;
303 enum e_drxk_constellation m_constellation; /* constellation type of the channel */
304 u32 m_curr_symbol_rate; /* Current QAM symbol rate */
305 struct s_cfg_agc m_qam_rf_agc_cfg; /* settings for QAM RF-AGC */
306 struct s_cfg_agc m_qam_if_agc_cfg; /* settings for QAM IF-AGC */
307 u16 m_qam_pga_cfg; /* settings for QAM PGA */
308 struct s_cfg_pre_saw m_qam_pre_saw_cfg; /* settings for QAM pre SAW sense */
309 enum e_drxk_interleave_mode m_qam_interleave_mode; /* QAM Interleave mode */
310 u16 m_fec_rs_plen;
311 u16 m_fec_rs_prescale;
313 enum drxk_cfg_dvbt_sqi_speed m_sqi_speed;
315 u16 m_gpio;
316 u16 m_gpio_cfg;
318 struct s_cfg_agc m_dvbt_rf_agc_cfg; /* settings for QAM RF-AGC */
319 struct s_cfg_agc m_dvbt_if_agc_cfg; /* settings for QAM IF-AGC */
320 struct s_cfg_pre_saw m_dvbt_pre_saw_cfg; /* settings for QAM pre SAW sense */
322 u16 m_agcfast_clip_ctrl_delay;
323 bool m_adc_comp_passed;
324 u16 m_adcCompCoef[64];
325 u16 m_adc_state;
327 u8 *m_microcode;
328 int m_microcode_length;
329 bool m_drxk_a3_rom_code;
330 bool m_drxk_a3_patch_code;
332 bool m_rfmirror;
333 u8 m_device_spin;
334 u32 m_iqm_rc_rate;
336 enum drx_power_mode m_current_power_mode;
339 bool drxk_i2c_exclusive_lock;
346 u16 uio_mask; /* Bits used by UIO */
348 bool enable_merr_cfg;
349 bool single_master;
350 bool no_i2c_bridge;
351 bool antenna_dvbt;
352 u16 antenna_gpio;
354 enum fe_status fe_status;
357 const char *microcode_name;
358 struct completion fw_wait_load;
359 const struct firmware *fw;
360 int qam_demod_parameter_count;