Lines Matching +full:sense +full:- +full:gain +full:- +full:div
1 // SPDX-License-Identifier: GPL-2.0-only
3 * drxk_hard: DRX-K DVB-C/T demodulator driver
5 * Copyright (C) 2010-2011 Digital Devices GmbH
45 return state->m_operation_mode == OM_DVBT; in is_dvbt()
50 return state->m_operation_mode == OM_QAM_ITU_A || in is_qam()
51 state->m_operation_mode == OM_QAM_ITU_B || in is_qam()
52 state->m_operation_mode == OM_QAM_ITU_C; in is_qam()
164 R0 = (a % c) << 4; /* 32-28 == 4 shifts possible at max */ in Frac28a()
193 i2c_lock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_lock()
194 state->drxk_i2c_exclusive_lock = true; in drxk_i2c_lock()
201 if (!state->drxk_i2c_exclusive_lock) in drxk_i2c_unlock()
204 i2c_unlock_bus(state->i2c, I2C_LOCK_SEGMENT); in drxk_i2c_unlock()
205 state->drxk_i2c_exclusive_lock = false; in drxk_i2c_unlock()
211 if (state->drxk_i2c_exclusive_lock) in drxk_i2c_transfer()
212 return __i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
214 return i2c_transfer(state->i2c, msgs, len); in drxk_i2c_transfer()
236 status = -EIO; in i2c_write()
260 status = -EIO; in i2c_read()
272 u8 adr = state->demod_address, mm1[4], mm2[2], len; in read16_flags()
274 if (state->single_master) in read16_flags()
306 u8 adr = state->demod_address, mm1[4], mm2[4], len; in read32_flags()
308 if (state->single_master) in read32_flags()
340 u8 adr = state->demod_address, mm[6], len; in write16_flags()
342 if (state->single_master) in write16_flags()
369 u8 adr = state->demod_address, mm[8], len; in write32_flags()
371 if (state->single_master) in write32_flags()
404 if (state->single_master) in write_block()
408 int chunk = blk_size > state->m_chunk_size ? in write_block()
409 state->m_chunk_size : blk_size; in write_block()
410 u8 *adr_buf = &state->chunk[0]; in write_block()
420 if (chunk == state->m_chunk_size) in write_block()
421 chunk -= 2; in write_block()
428 memcpy(&state->chunk[adr_length], p_block, chunk); in write_block()
432 status = i2c_write(state, state->demod_address, in write_block()
433 &state->chunk[0], chunk + adr_length); in write_block()
441 blk_size -= chunk; in write_block()
458 status = i2c_read1(state, state->demod_address, &data); in power_up_device()
462 status = i2c_write(state, state->demod_address, in power_up_device()
468 status = i2c_read1(state, state->demod_address, in power_up_device()
488 state->m_current_power_mode = DRX_POWER_UP; in power_up_device()
502 * struct drxk_config, as they are probably board-specific in init_state()
554 state->m_has_lna = false; in init_state()
555 state->m_has_dvbt = false; in init_state()
556 state->m_has_dvbc = false; in init_state()
557 state->m_has_atv = false; in init_state()
558 state->m_has_oob = false; in init_state()
559 state->m_has_audio = false; in init_state()
561 if (!state->m_chunk_size) in init_state()
562 state->m_chunk_size = 124; in init_state()
564 state->m_osc_clock_freq = 0; in init_state()
565 state->m_smart_ant_inverted = false; in init_state()
566 state->m_b_p_down_open_bridge = false; in init_state()
569 state->m_sys_clock_freq = 151875; in init_state()
570 /* Timing div, 250ns/Psys */ in init_state()
571 /* Timing div, = (delay (nano seconds) * sysclk (kHz))/ 1000 */ in init_state()
572 state->m_hi_cfg_timing_div = ((state->m_sys_clock_freq / 1000) * in init_state()
575 if (state->m_hi_cfg_timing_div > SIO_HI_RA_RAM_PAR_2_CFG_DIV__M) in init_state()
576 state->m_hi_cfg_timing_div = SIO_HI_RA_RAM_PAR_2_CFG_DIV__M; in init_state()
577 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_state()
579 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_state()
581 state->m_b_power_down = (ul_power_down != 0); in init_state()
583 state->m_drxk_a3_patch_code = false; in init_state()
587 state->m_vsb_if_agc_cfg.ctrl_mode = ul_vsb_if_agc_mode; in init_state()
588 state->m_vsb_if_agc_cfg.output_level = ul_vsb_if_agc_output_level; in init_state()
589 state->m_vsb_if_agc_cfg.min_output_level = ul_vsb_if_agc_min_level; in init_state()
590 state->m_vsb_if_agc_cfg.max_output_level = ul_vsb_if_agc_max_level; in init_state()
591 state->m_vsb_if_agc_cfg.speed = ul_vsb_if_agc_speed; in init_state()
592 state->m_vsb_pga_cfg = 140; in init_state()
595 state->m_vsb_rf_agc_cfg.ctrl_mode = ul_vsb_rf_agc_mode; in init_state()
596 state->m_vsb_rf_agc_cfg.output_level = ul_vsb_rf_agc_output_level; in init_state()
597 state->m_vsb_rf_agc_cfg.min_output_level = ul_vsb_rf_agc_min_level; in init_state()
598 state->m_vsb_rf_agc_cfg.max_output_level = ul_vsb_rf_agc_max_level; in init_state()
599 state->m_vsb_rf_agc_cfg.speed = ul_vsb_rf_agc_speed; in init_state()
600 state->m_vsb_rf_agc_cfg.top = ul_vsb_rf_agc_top; in init_state()
601 state->m_vsb_rf_agc_cfg.cut_off_current = ul_vsb_rf_agc_cut_off_current; in init_state()
602 state->m_vsb_pre_saw_cfg.reference = 0x07; in init_state()
603 state->m_vsb_pre_saw_cfg.use_pre_saw = true; in init_state()
605 state->m_Quality83percent = DEFAULT_MER_83; in init_state()
606 state->m_Quality93percent = DEFAULT_MER_93; in init_state()
608 state->m_Quality83percent = ulQual83; in init_state()
609 state->m_Quality93percent = ulQual93; in init_state()
613 state->m_atv_if_agc_cfg.ctrl_mode = ul_atv_if_agc_mode; in init_state()
614 state->m_atv_if_agc_cfg.output_level = ul_atv_if_agc_output_level; in init_state()
615 state->m_atv_if_agc_cfg.min_output_level = ul_atv_if_agc_min_level; in init_state()
616 state->m_atv_if_agc_cfg.max_output_level = ul_atv_if_agc_max_level; in init_state()
617 state->m_atv_if_agc_cfg.speed = ul_atv_if_agc_speed; in init_state()
620 state->m_atv_rf_agc_cfg.ctrl_mode = ul_atv_rf_agc_mode; in init_state()
621 state->m_atv_rf_agc_cfg.output_level = ul_atv_rf_agc_output_level; in init_state()
622 state->m_atv_rf_agc_cfg.min_output_level = ul_atv_rf_agc_min_level; in init_state()
623 state->m_atv_rf_agc_cfg.max_output_level = ul_atv_rf_agc_max_level; in init_state()
624 state->m_atv_rf_agc_cfg.speed = ul_atv_rf_agc_speed; in init_state()
625 state->m_atv_rf_agc_cfg.top = ul_atv_rf_agc_top; in init_state()
626 state->m_atv_rf_agc_cfg.cut_off_current = ul_atv_rf_agc_cut_off_current; in init_state()
627 state->m_atv_pre_saw_cfg.reference = 0x04; in init_state()
628 state->m_atv_pre_saw_cfg.use_pre_saw = true; in init_state()
632 state->m_dvbt_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
633 state->m_dvbt_rf_agc_cfg.output_level = 0; in init_state()
634 state->m_dvbt_rf_agc_cfg.min_output_level = 0; in init_state()
635 state->m_dvbt_rf_agc_cfg.max_output_level = 0xFFFF; in init_state()
636 state->m_dvbt_rf_agc_cfg.top = 0x2100; in init_state()
637 state->m_dvbt_rf_agc_cfg.cut_off_current = 4000; in init_state()
638 state->m_dvbt_rf_agc_cfg.speed = 1; in init_state()
642 state->m_dvbt_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
643 state->m_dvbt_if_agc_cfg.output_level = 0; in init_state()
644 state->m_dvbt_if_agc_cfg.min_output_level = 0; in init_state()
645 state->m_dvbt_if_agc_cfg.max_output_level = 9000; in init_state()
646 state->m_dvbt_if_agc_cfg.top = 13424; in init_state()
647 state->m_dvbt_if_agc_cfg.cut_off_current = 0; in init_state()
648 state->m_dvbt_if_agc_cfg.speed = 3; in init_state()
649 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay = 30; in init_state()
650 state->m_dvbt_if_agc_cfg.ingain_tgt_max = 30000; in init_state()
651 /* state->m_dvbtPgaCfg = 140; */ in init_state()
653 state->m_dvbt_pre_saw_cfg.reference = 4; in init_state()
654 state->m_dvbt_pre_saw_cfg.use_pre_saw = false; in init_state()
657 state->m_qam_rf_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_OFF; in init_state()
658 state->m_qam_rf_agc_cfg.output_level = 0; in init_state()
659 state->m_qam_rf_agc_cfg.min_output_level = 6023; in init_state()
660 state->m_qam_rf_agc_cfg.max_output_level = 27000; in init_state()
661 state->m_qam_rf_agc_cfg.top = 0x2380; in init_state()
662 state->m_qam_rf_agc_cfg.cut_off_current = 4000; in init_state()
663 state->m_qam_rf_agc_cfg.speed = 3; in init_state()
666 state->m_qam_if_agc_cfg.ctrl_mode = DRXK_AGC_CTRL_AUTO; in init_state()
667 state->m_qam_if_agc_cfg.output_level = 0; in init_state()
668 state->m_qam_if_agc_cfg.min_output_level = 0; in init_state()
669 state->m_qam_if_agc_cfg.max_output_level = 9000; in init_state()
670 state->m_qam_if_agc_cfg.top = 0x0511; in init_state()
671 state->m_qam_if_agc_cfg.cut_off_current = 0; in init_state()
672 state->m_qam_if_agc_cfg.speed = 3; in init_state()
673 state->m_qam_if_agc_cfg.ingain_tgt_max = 5119; in init_state()
674 state->m_qam_if_agc_cfg.fast_clip_ctrl_delay = 50; in init_state()
676 state->m_qam_pga_cfg = 140; in init_state()
677 state->m_qam_pre_saw_cfg.reference = 4; in init_state()
678 state->m_qam_pre_saw_cfg.use_pre_saw = false; in init_state()
680 state->m_operation_mode = OM_NONE; in init_state()
681 state->m_drxk_state = DRXK_UNINITIALIZED; in init_state()
684 state->m_enable_mpeg_output = true; /* If TRUE; enable MPEG output */ in init_state()
685 state->m_insert_rs_byte = false; /* If TRUE; insert RS byte */ in init_state()
686 state->m_invert_data = false; /* If TRUE; invert DATA signals */ in init_state()
687 state->m_invert_err = false; /* If TRUE; invert ERR signal */ in init_state()
688 state->m_invert_str = false; /* If TRUE; invert STR signals */ in init_state()
689 state->m_invert_val = false; /* If TRUE; invert VAL signals */ in init_state()
690 state->m_invert_clk = (ul_invert_ts_clock != 0); /* If TRUE; invert CLK signals */ in init_state()
695 state->m_dvbt_bitrate = ul_dvbt_bitrate; in init_state()
696 state->m_dvbc_bitrate = ul_dvbc_bitrate; in init_state()
698 state->m_ts_data_strength = (ul_ts_data_strength & 0x07); in init_state()
701 state->m_mpeg_ts_static_bitrate = 19392658; in init_state()
702 state->m_disable_te_ihandling = false; in init_state()
705 state->m_insert_rs_byte = true; in init_state()
707 state->m_mpeg_lock_time_out = DEFAULT_DRXK_MPEG_LOCK_TIMEOUT; in init_state()
709 state->m_mpeg_lock_time_out = ul_mpeg_lock_time_out; in init_state()
710 state->m_demod_lock_time_out = DEFAULT_DRXK_DEMOD_LOCK_TIMEOUT; in init_state()
712 state->m_demod_lock_time_out = ul_demod_lock_time_out; in init_state()
715 state->m_constellation = DRX_CONSTELLATION_AUTO; in init_state()
716 state->m_qam_interleave_mode = DRXK_QAM_I12_J17; in init_state()
717 state->m_fec_rs_plen = 204 * 8; /* fecRsPlen annex A */ in init_state()
718 state->m_fec_rs_prescale = 1; in init_state()
720 state->m_sqi_speed = DRXK_DVBT_SQI_SPEED_MEDIUM; in init_state()
721 state->m_agcfast_clip_ctrl_delay = 0; in init_state()
723 state->m_gpio_cfg = ul_gpio_cfg; in init_state()
725 state->m_b_power_down = false; in init_state()
726 state->m_current_power_mode = DRX_POWER_DOWN; in init_state()
728 state->m_rfmirror = (ul_rf_mirror == 0); in init_state()
729 state->m_if_agc_pol = false; in init_state()
797 state->m_osc_clock_freq = 27000; in get_device_capabilities()
801 state->m_osc_clock_freq = 20250; in get_device_capabilities()
805 state->m_osc_clock_freq = 20250; in get_device_capabilities()
809 return -EINVAL; in get_device_capabilities()
824 state->m_device_spin = DRXK_SPIN_A1; in get_device_capabilities()
828 state->m_device_spin = DRXK_SPIN_A2; in get_device_capabilities()
832 state->m_device_spin = DRXK_SPIN_A3; in get_device_capabilities()
836 state->m_device_spin = DRXK_SPIN_UNKNOWN; in get_device_capabilities()
837 status = -EINVAL; in get_device_capabilities()
844 state->m_has_lna = false; in get_device_capabilities()
845 state->m_has_oob = false; in get_device_capabilities()
846 state->m_has_atv = false; in get_device_capabilities()
847 state->m_has_audio = false; in get_device_capabilities()
848 state->m_has_dvbt = true; in get_device_capabilities()
849 state->m_has_dvbc = true; in get_device_capabilities()
850 state->m_has_sawsw = true; in get_device_capabilities()
851 state->m_has_gpio2 = false; in get_device_capabilities()
852 state->m_has_gpio1 = false; in get_device_capabilities()
853 state->m_has_irqn = false; in get_device_capabilities()
857 state->m_has_lna = false; in get_device_capabilities()
858 state->m_has_oob = false; in get_device_capabilities()
859 state->m_has_atv = true; in get_device_capabilities()
860 state->m_has_audio = false; in get_device_capabilities()
861 state->m_has_dvbt = true; in get_device_capabilities()
862 state->m_has_dvbc = false; in get_device_capabilities()
863 state->m_has_sawsw = true; in get_device_capabilities()
864 state->m_has_gpio2 = true; in get_device_capabilities()
865 state->m_has_gpio1 = true; in get_device_capabilities()
866 state->m_has_irqn = false; in get_device_capabilities()
870 state->m_has_lna = false; in get_device_capabilities()
871 state->m_has_oob = false; in get_device_capabilities()
872 state->m_has_atv = true; in get_device_capabilities()
873 state->m_has_audio = false; in get_device_capabilities()
874 state->m_has_dvbt = true; in get_device_capabilities()
875 state->m_has_dvbc = false; in get_device_capabilities()
876 state->m_has_sawsw = true; in get_device_capabilities()
877 state->m_has_gpio2 = true; in get_device_capabilities()
878 state->m_has_gpio1 = true; in get_device_capabilities()
879 state->m_has_irqn = false; in get_device_capabilities()
883 state->m_has_lna = false; in get_device_capabilities()
884 state->m_has_oob = false; in get_device_capabilities()
885 state->m_has_atv = true; in get_device_capabilities()
886 state->m_has_audio = true; in get_device_capabilities()
887 state->m_has_dvbt = true; in get_device_capabilities()
888 state->m_has_dvbc = false; in get_device_capabilities()
889 state->m_has_sawsw = true; in get_device_capabilities()
890 state->m_has_gpio2 = true; in get_device_capabilities()
891 state->m_has_gpio1 = true; in get_device_capabilities()
892 state->m_has_irqn = false; in get_device_capabilities()
896 state->m_has_lna = false; in get_device_capabilities()
897 state->m_has_oob = false; in get_device_capabilities()
898 state->m_has_atv = true; in get_device_capabilities()
899 state->m_has_audio = true; in get_device_capabilities()
900 state->m_has_dvbt = true; in get_device_capabilities()
901 state->m_has_dvbc = true; in get_device_capabilities()
902 state->m_has_sawsw = true; in get_device_capabilities()
903 state->m_has_gpio2 = true; in get_device_capabilities()
904 state->m_has_gpio1 = true; in get_device_capabilities()
905 state->m_has_irqn = false; in get_device_capabilities()
909 state->m_has_lna = false; in get_device_capabilities()
910 state->m_has_oob = false; in get_device_capabilities()
911 state->m_has_atv = true; in get_device_capabilities()
912 state->m_has_audio = true; in get_device_capabilities()
913 state->m_has_dvbt = true; in get_device_capabilities()
914 state->m_has_dvbc = true; in get_device_capabilities()
915 state->m_has_sawsw = true; in get_device_capabilities()
916 state->m_has_gpio2 = true; in get_device_capabilities()
917 state->m_has_gpio1 = true; in get_device_capabilities()
918 state->m_has_irqn = false; in get_device_capabilities()
922 state->m_has_lna = false; in get_device_capabilities()
923 state->m_has_oob = false; in get_device_capabilities()
924 state->m_has_atv = true; in get_device_capabilities()
925 state->m_has_audio = true; in get_device_capabilities()
926 state->m_has_dvbt = true; in get_device_capabilities()
927 state->m_has_dvbc = true; in get_device_capabilities()
928 state->m_has_sawsw = true; in get_device_capabilities()
929 state->m_has_gpio2 = true; in get_device_capabilities()
930 state->m_has_gpio1 = true; in get_device_capabilities()
931 state->m_has_irqn = false; in get_device_capabilities()
935 state->m_has_lna = false; in get_device_capabilities()
936 state->m_has_oob = false; in get_device_capabilities()
937 state->m_has_atv = true; in get_device_capabilities()
938 state->m_has_audio = false; in get_device_capabilities()
939 state->m_has_dvbt = true; in get_device_capabilities()
940 state->m_has_dvbc = true; in get_device_capabilities()
941 state->m_has_sawsw = true; in get_device_capabilities()
942 state->m_has_gpio2 = true; in get_device_capabilities()
943 state->m_has_gpio1 = true; in get_device_capabilities()
944 state->m_has_irqn = false; in get_device_capabilities()
949 status = -EINVAL; in get_device_capabilities()
953 pr_info("detected a drx-39%02xk, spin %s, xtal %d.%03d MHz\n", in get_device_capabilities()
955 state->m_osc_clock_freq / 1000, in get_device_capabilities()
956 state->m_osc_clock_freq % 1000); in get_device_capabilities()
982 ((state->m_hi_cfg_ctrl) & in hi_command()
1013 mutex_lock(&state->mutex); in hi_cfg_command()
1016 state->m_hi_cfg_timeout); in hi_cfg_command()
1020 state->m_hi_cfg_ctrl); in hi_cfg_command()
1024 state->m_hi_cfg_wake_up_key); in hi_cfg_command()
1028 state->m_hi_cfg_bridge_delay); in hi_cfg_command()
1032 state->m_hi_cfg_timing_div); in hi_cfg_command()
1043 state->m_hi_cfg_ctrl &= ~SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in hi_cfg_command()
1045 mutex_unlock(&state->mutex); in hi_cfg_command()
1055 state->m_hi_cfg_wake_up_key = (state->demod_address << 1); in init_hi()
1056 state->m_hi_cfg_timeout = 0x96FF; in init_hi()
1058 state->m_hi_cfg_ctrl = SIO_HI_RA_RAM_PAR_5_CFG_SLV0_SLAVE; in init_hi()
1072 state->m_enable_parallel ? "parallel" : "serial"); in mpegts_configure_pins()
1126 ((state->m_ts_data_strength << in mpegts_configure_pins()
1128 sio_pdr_mclk_cfg = ((state->m_ts_clockk_strength << in mpegts_configure_pins()
1136 if (state->enable_merr_cfg) in mpegts_configure_pins()
1146 if (state->m_enable_parallel) { in mpegts_configure_pins()
1147 /* parallel -> enable MD1 to MD7 */ in mpegts_configure_pins()
1177 sio_pdr_mdx_cfg = ((state->m_ts_data_strength << in mpegts_configure_pins()
1180 /* serial -> disable MD1 to MD7 */ in mpegts_configure_pins()
1237 mutex_lock(&state->mutex); in bl_chain_cmd()
1262 status = -EINVAL; in bl_chain_cmd()
1269 mutex_unlock(&state->mutex); in bl_chain_cmd()
1324 return -EINVAL; in download_microcode()
1371 return -EINVAL; in dvbt_enable_ofdm_token_ring()
1411 #if (SCU_RAM_PARAM_0__A - SCU_RAM_PARAM_15__A) != 15 in scu_command()
1415 int status = -EINVAL; in scu_command()
1430 mutex_lock(&state->mutex); in scu_command()
1435 for (ii = parameter_len - 1; ii >= 0; ii -= 1) { in scu_command()
1443 write_block(state, SCU_RAM_PARAM_0__A - in scu_command()
1444 (parameter_len - 1), cnt, buffer); in scu_command()
1455 status = -EIO; in scu_command()
1463 for (ii = result_len - 1; ii >= 0; ii -= 1) { in scu_command()
1464 status = read16(state, SCU_RAM_PARAM_0__A - ii, in scu_command()
1495 status = -EINVAL; in scu_command()
1503 mutex_unlock(&state->mutex); in scu_command()
1550 return -EINVAL; in ctrl_power_mode()
1570 return -EINVAL; in ctrl_power_mode()
1574 if (state->m_current_power_mode == *mode) in ctrl_power_mode()
1578 if (state->m_current_power_mode != DRX_POWER_UP) { in ctrl_power_mode()
1592 /* Set pins with possible pull-ups connected in ctrl_power_mode()
1599 switch (state->m_operation_mode) { in ctrl_power_mode()
1631 state->m_hi_cfg_ctrl |= in ctrl_power_mode()
1638 state->m_current_power_mode = *mode; in ctrl_power_mode()
1723 if (state->m_operation_mode == o_mode) in setoperation_mode()
1726 switch (state->m_operation_mode) { in setoperation_mode()
1737 state->m_operation_mode = OM_NONE; in setoperation_mode()
1747 state->m_operation_mode = OM_NONE; in setoperation_mode()
1751 status = -EINVAL; in setoperation_mode()
1760 dprintk(1, ": DVB-T\n"); in setoperation_mode()
1761 state->m_operation_mode = o_mode; in setoperation_mode()
1768 dprintk(1, ": DVB-C Annex %c\n", in setoperation_mode()
1769 (state->m_operation_mode == OM_QAM_ITU_A) ? 'A' : 'C'); in setoperation_mode()
1770 state->m_operation_mode = o_mode; in setoperation_mode()
1777 status = -EINVAL; in setoperation_mode()
1788 int status = -EINVAL; in start()
1794 if (state->m_drxk_state != DRXK_STOPPED && in start()
1795 state->m_drxk_state != DRXK_DTV_STARTED) in start()
1798 state->m_b_mirror_freq_spect = (state->props.inversion == INVERSION_ON); in start()
1801 state->m_b_mirror_freq_spect = !state->m_b_mirror_freq_spect; in start()
1802 intermediate_frequency = -intermediate_frequency; in start()
1805 switch (state->m_operation_mode) { in start()
1812 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1825 state->m_drxk_state = DRXK_DTV_STARTED; in start()
1846 int status = -EINVAL; in get_lock_status()
1856 switch (state->m_operation_mode) { in get_lock_status()
1867 state->m_operation_mode, __func__); in get_lock_status()
1963 /* Check insertion of the Reed-Solomon parity bytes */ in mpegts_dto_setup()
1972 if (state->m_insert_rs_byte) { in mpegts_dto_setup()
1983 if (!state->m_enable_parallel) { in mpegts_dto_setup()
1984 /* MPEG data output is serial -> set ipr_mode[0] */ in mpegts_dto_setup()
1990 max_bit_rate = state->m_dvbt_bitrate; in mpegts_dto_setup()
1993 static_clk = state->m_dvbt_static_clk; in mpegts_dto_setup()
1999 max_bit_rate = state->m_dvbc_bitrate; in mpegts_dto_setup()
2000 static_clk = state->m_dvbc_static_clk; in mpegts_dto_setup()
2003 status = -EINVAL; in mpegts_dto_setup()
2014 (avoid intra-packet gaps), in mpegts_dto_setup()
2027 dto_period = (Fsys / bitrate) - 2 in mpegts_dto_setup()
2032 fec_oc_dto_period = (u16) (((state->m_sys_clock_freq) in mpegts_dto_setup()
2037 fec_oc_dto_period -= 2; in mpegts_dto_setup()
2040 /* (commonAttr->static_clk == false) => dynamic mode */ in mpegts_dto_setup()
2096 if (state->m_invert_data) in mpegts_configure_polarity()
2099 if (state->m_invert_err) in mpegts_configure_polarity()
2102 if (state->m_invert_str) in mpegts_configure_polarity()
2105 if (state->m_invert_val) in mpegts_configure_polarity()
2108 if (state->m_invert_clk) in mpegts_configure_polarity()
2119 int status = -EINVAL; in set_agc_rf()
2128 switch (p_agc_cfg->ctrl_mode) { in set_agc_rf()
2146 if (state->m_rf_agc_pol) in set_agc_rf()
2160 data |= (~(p_agc_cfg->speed << in set_agc_rf()
2169 p_if_agc_settings = &state->m_dvbt_if_agc_cfg; in set_agc_rf()
2171 p_if_agc_settings = &state->m_qam_if_agc_cfg; in set_agc_rf()
2173 p_if_agc_settings = &state->m_atv_if_agc_cfg; in set_agc_rf()
2175 status = -EINVAL; in set_agc_rf()
2179 /* Set TOP, only if IF-AGC is in AUTO mode */ in set_agc_rf()
2180 if (p_if_agc_settings->ctrl_mode == DRXK_AGC_CTRL_AUTO) { in set_agc_rf()
2183 p_agc_cfg->top); in set_agc_rf()
2188 /* Cut-Off current */ in set_agc_rf()
2190 p_agc_cfg->cut_off_current); in set_agc_rf()
2196 p_agc_cfg->max_output_level); in set_agc_rf()
2217 if (state->m_rf_agc_pol) in set_agc_rf()
2232 p_agc_cfg->output_level); in set_agc_rf()
2258 status = -EINVAL; in set_agc_rf()
2278 switch (p_agc_cfg->ctrl_mode) { in set_agc_if()
2298 if (state->m_if_agc_pol) in set_agc_if()
2311 data |= (~(p_agc_cfg->speed << in set_agc_if()
2320 p_rf_agc_settings = &state->m_qam_rf_agc_cfg; in set_agc_if()
2322 p_rf_agc_settings = &state->m_atv_rf_agc_cfg; in set_agc_if()
2324 return -1; in set_agc_if()
2327 p_rf_agc_settings->top); in set_agc_if()
2351 if (state->m_if_agc_pol) in set_agc_if()
2361 p_agc_cfg->output_level); in set_agc_if()
2386 } /* switch (agcSettingsIf->ctrl_mode) */ in set_agc_if()
2389 configurations without if-loop */ in set_agc_if()
2390 status = write16(state, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_cfg->top); in set_agc_if()
2415 return -EINVAL; in get_qam_signal_to_noise()
2418 switch (state->props.modulation) { in get_qam_signal_to_noise()
2438 qam_sl_mer = log10times100(qam_sl_sig_power) - in get_qam_signal_to_noise()
2526 => IMER = a + b -c in get_dvbt_signal_to_noise()
2532 /* log(x) x = 9bits * 9bits->18 bits */ in get_dvbt_signal_to_noise()
2535 /* log(x) x = 16bits * 7bits->23 bits */ in get_dvbt_signal_to_noise()
2537 /* log(x) x = (16bits + 16bits) << 15 ->32 bits */ in get_dvbt_signal_to_noise()
2540 i_mer = a + b - c; in get_dvbt_signal_to_noise()
2555 switch (state->m_operation_mode) { in get_signal_to_noise()
2581 108, /* 16-QAM 1/2 */
2582 131, /* 16-QAM 2/3 */
2583 146, /* 16-QAM 3/4 */
2584 156, /* 16-QAM 5/6 */
2585 160, /* 16-QAM 7/8 */
2586 165, /* 64-QAM 1/2 */
2587 187, /* 64-QAM 2/3 */
2588 202, /* 64-QAM 3/4 */
2589 216, /* 64-QAM 5/6 */
2590 225, /* 64-QAM 7/8 */
2620 signal_to_noise_rel = signal_to_noise -
2624 if (signal_to_noise_rel < -70)
2651 switch (state->props.modulation) {
2653 signal_to_noise_rel = signal_to_noise - 200;
2656 signal_to_noise_rel = signal_to_noise - 230;
2659 signal_to_noise_rel = signal_to_noise - 260;
2662 signal_to_noise_rel = signal_to_noise - 290;
2666 signal_to_noise_rel = signal_to_noise - 320;
2670 if (signal_to_noise_rel < -70)
2686 switch (state->m_operation_mode) {
2714 int status = -EINVAL; in ConfigureI2CBridge()
2718 if (state->m_drxk_state == DRXK_UNINITIALIZED) in ConfigureI2CBridge()
2720 if (state->m_drxk_state == DRXK_POWERED_DOWN) in ConfigureI2CBridge()
2723 if (state->no_i2c_bridge) in ConfigureI2CBridge()
2753 int status = -EINVAL; in set_pre_saw()
2758 || (p_pre_saw_cfg->reference > IQM_AF_PDREF__M)) in set_pre_saw()
2761 status = write16(state, IQM_AF_PDREF__A, p_pre_saw_cfg->reference); in set_pre_saw()
2779 mutex_lock(&state->mutex); in bl_direct_cmd()
2807 status = -EINVAL; in bl_direct_cmd()
2814 mutex_unlock(&state->mutex); in bl_direct_cmd()
2894 status = -EINVAL; in adc_synchronization()
2908 bool tuner_mirror = !state->m_b_mirror_freq_spect; in set_frequency_shifter()
2913 u32 sampling_frequency = (u32) (state->m_sys_clock_freq / 3); in set_frequency_shifter()
2924 if ((state->m_operation_mode == OM_QAM_ITU_A) || in set_frequency_shifter()
2925 (state->m_operation_mode == OM_QAM_ITU_C) || in set_frequency_shifter()
2926 (state->m_operation_mode == OM_DVBT)) in set_frequency_shifter()
2937 if_freq_actual = intermediate_freqk_hz - in set_frequency_shifter()
2938 rf_freq_residual - fm_frequency_shift; in set_frequency_shifter()
2941 adc_freq = sampling_frequency - if_freq_actual; in set_frequency_shifter()
2950 image_to_select = state->m_rfmirror ^ tuner_mirror ^ in set_frequency_shifter()
2952 state->m_iqm_fs_rate_ofs = in set_frequency_shifter()
2956 state->m_iqm_fs_rate_ofs = ~state->m_iqm_fs_rate_ofs + 1; in set_frequency_shifter()
2961 state->m_iqm_fs_rate_ofs); in set_frequency_shifter()
2998 pr_err("%s: mode %d is not DVB-C\n", in init_agc()
2999 __func__, state->m_operation_mode); in init_agc()
3000 return -EINVAL; in init_agc()
3007 clp_dir_to = (u16) -9; in init_agc()
3010 sns_dir_to = (u16) -9; in init_agc()
3011 ki_innergain_min = (u16) -1030; in init_agc()
3017 fast_clp_ctrl_delay = state->m_qam_if_agc_cfg.fast_clip_ctrl_delay; in init_agc()
3078 status = write16(state, SCU_RAM_AGC_RF_SNS_DEV_MIN__A, (u16) -1023); in init_agc()
3143 /* Initialize inner-loop KI gain factors */ in init_agc()
3191 status = -EINVAL; in dvbt_sc_command()
3206 /* Write sub-command */ in dvbt_sc_command()
3208 /* All commands using sub-cmd */ in dvbt_sc_command()
3244 status = -EINVAL; in dvbt_sc_command()
3263 status = -EINVAL; in dvbt_sc_command()
3289 status = -EINVAL; in dvbt_sc_command()
3291 } /* switch (cmd->cmd) */ in dvbt_sc_command()
3356 switch (echo_thres->fft_mode) { in dvbt_ctrl_set_echo_threshold()
3359 data |= ((echo_thres->threshold << in dvbt_ctrl_set_echo_threshold()
3365 data |= ((echo_thres->threshold << in dvbt_ctrl_set_echo_threshold()
3370 return -EINVAL; in dvbt_ctrl_set_echo_threshold()
3383 int status = -EINVAL; in dvbt_ctrl_set_sqi_speed()
3436 state->m_dvbt_if_agc_cfg.ingain_tgt_max); in dvbt_activate_presets()
3446 * \brief Initialize channelswitch-independent settings for DVBT.
3451 * the DVB-T taps from the drxk_filters.h are used.
3492 /* synchronize on ofdstate->m_festart */ in set_dvbt_standard()
3500 /* window size for sense pre-SAW detection */ in set_dvbt_standard()
3504 /* sense threshold for sense pre-SAW detection */ in set_dvbt_standard()
3574 status = set_pre_saw(state, &state->m_dvbt_pre_saw_cfg); in set_dvbt_standard()
3578 /* Halt SCU to enable safe non-atomic accesses */ in set_dvbt_standard()
3583 status = set_agc_rf(state, &state->m_dvbt_rf_agc_cfg, true); in set_dvbt_standard()
3586 status = set_agc_if(state, &state->m_dvbt_if_agc_cfg, true); in set_dvbt_standard()
3604 if (!state->m_drxk_a3_rom_code) { in set_dvbt_standard()
3607 state->m_dvbt_if_agc_cfg.fast_clip_ctrl_delay); in set_dvbt_standard()
3718 /* Halt SCU to enable safe non-atomic accesses */ in set_dvbt()
3740 switch (state->props.transmission_mode) { in set_dvbt()
3752 switch (state->props.guard_interval) { in set_dvbt()
3770 switch (state->props.hierarchy) { in set_dvbt()
3787 switch (state->props.modulation) { in set_dvbt()
3803 switch (channel->priority) { in set_dvbt()
3816 status = -EINVAL; in set_dvbt()
3828 switch (state->props.code_rate_HP) { in set_dvbt()
3861 switch (state->props.bandwidth_hz) { in set_dvbt()
3863 state->props.bandwidth_hz = 8000000; in set_dvbt()
3938 status = -EINVAL; in set_dvbt()
3944 (((SysFreq/BandWidth)/2)/2) -1) * 2^23) in set_dvbt()
3946 ((SysFreq / BandWidth) * (2^21)) - (2^23) in set_dvbt()
3956 ((state->m_sys_clock_freq * in set_dvbt()
3962 /* ((SysFreq / BandWidth) * (2^21)) - (2^23) */ in set_dvbt()
3963 iqm_rc_rate_ofs = iqm_rc_rate_ofs - (1 << 23); in set_dvbt()
4018 if (!state->m_drxk_a3_rom_code) in set_dvbt()
4019 status = dvbt_ctrl_set_sqi_speed(state, &state->m_sqi_speed); in set_dvbt()
4108 /* stop all comstate->m_exec */ in power_down_qam()
4177 status = -EINVAL; in set_qam_measurement()
4182 fec_bits_desired /= 1000; /* symbol_rate [Hz] -> symbol_rate [kHz] */ in set_qam_measurement()
4193 status = -EINVAL; in set_qam_measurement()
4387 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -24); in set_qam16()
4390 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -65); in set_qam16()
4393 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -127); in set_qam16()
4580 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16) -8); in set_qam32()
4583 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16) -16); in set_qam32()
4586 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -26); in set_qam32()
4589 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -56); in set_qam32()
4592 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -86); in set_qam32()
4780 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -15); in set_qam64()
4783 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -45); in set_qam64()
4786 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -80); in set_qam64()
4977 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16) -1); in set_qam128()
4980 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16) -12); in set_qam128()
4983 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -23); in set_qam128()
5179 status = write16(state, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16) -8); in set_qam256()
5200 /* Stop QAM comstate->m_exec */ in qam_reset_qam()
5233 adc_frequency = (state->m_sys_clock_freq * 1000) / 3; in qam_set_symbolrate()
5235 if (state->props.symbol_rate <= 1188750) in qam_set_symbolrate()
5237 else if (state->props.symbol_rate <= 2377500) in qam_set_symbolrate()
5239 else if (state->props.symbol_rate <= 4755000) in qam_set_symbolrate()
5246 IqmRcRate = ((Fadc / (symbolrate * (4<<ratesel))) - 1) * (1<<23) in qam_set_symbolrate()
5248 symb_freq = state->props.symbol_rate * (1 << ratesel); in qam_set_symbolrate()
5251 status = -EINVAL; in qam_set_symbolrate()
5255 (Frac28a((adc_frequency % symb_freq), symb_freq) >> 7) - in qam_set_symbolrate()
5260 state->m_iqm_rc_rate = iqm_rc_rate; in qam_set_symbolrate()
5264 symb_freq = state->props.symbol_rate; in qam_set_symbolrate()
5267 status = -EINVAL; in qam_set_symbolrate()
5340 set_param_parameters[0] = state->m_constellation; /* modulation */ in qam_demodulator_command()
5346 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5364 if (state->m_operation_mode == OM_QAM_ITU_C) in qam_demodulator_command()
5382 status = -EINVAL; in qam_demodulator_command()
5396 int qam_demod_param_count = state->qam_demod_parameter_count; in set_qam()
5417 * -set params; resets IQM,QAM,FEC HW; initializes some in set_qam()
5425 switch (state->props.modulation) { in set_qam()
5427 state->m_constellation = DRX_CONSTELLATION_QAM256; in set_qam()
5431 state->m_constellation = DRX_CONSTELLATION_QAM64; in set_qam()
5434 state->m_constellation = DRX_CONSTELLATION_QAM16; in set_qam()
5437 state->m_constellation = DRX_CONSTELLATION_QAM32; in set_qam()
5440 state->m_constellation = DRX_CONSTELLATION_QAM128; in set_qam()
5443 status = -EINVAL; in set_qam()
5449 /* Use the 4-parameter if it's requested or we're probing for in set_qam()
5451 if (state->qam_demod_parameter_count == 4 in set_qam()
5452 || !state->qam_demod_parameter_count) { in set_qam()
5457 /* Use the 2-parameter command if it was requested or if we're in set_qam()
5458 * probing for the correct command and the 4-parameter command in set_qam()
5460 if (state->qam_demod_parameter_count == 2 in set_qam()
5461 || (!state->qam_demod_parameter_count && status < 0)) { in set_qam()
5470 state->qam_demod_parameter_count, in set_qam()
5471 state->microcode_name); in set_qam()
5473 } else if (!state->qam_demod_parameter_count) { in set_qam()
5475 "Auto-probing the QAM command parameters was successful - using %d parameters.\n", in set_qam()
5480 * auto-probe anymore, now that we got the correct command. in set_qam()
5482 state->qam_demod_parameter_count = qam_demod_param_count; in set_qam()
5500 status = set_qam_measurement(state, state->m_constellation, in set_qam()
5501 state->props.symbol_rate); in set_qam()
5573 /* Mirroring, QAM-block starting point not inverted */ in set_qam()
5579 /* Halt SCU to enable safe non-atomic accesses */ in set_qam()
5585 switch (state->props.modulation) { in set_qam()
5603 status = -EINVAL; in set_qam()
5614 /* Re-configure MPEG output, requires knowledge of channel bitrate */ in set_qam()
5615 /* extAttr->currentChannel.modulation = channel->modulation; */ in set_qam()
5616 /* extAttr->currentChannel.symbolrate = channel->symbolrate; */ in set_qam()
5617 status = mpegts_dto_setup(state, state->m_operation_mode); in set_qam()
5643 /*? extAttr->qamInterleaveMode = DRXK_QAM_I12_J17; */ in set_qam()
5666 /* Ensure correct power-up mode */ in set_qam_standard()
5706 status = -EINVAL; in set_qam_standard()
5792 /* Halt SCU to enable safe non-atomic accesses */ in set_qam_standard()
5803 status = set_pre_saw(state, &(state->m_qam_pre_saw_cfg)); in set_qam_standard()
5808 status = set_agc_rf(state, &(state->m_qam_rf_agc_cfg), true); in set_qam_standard()
5811 status = set_agc_if(state, &(state->m_qam_if_agc_cfg), true); in set_qam_standard()
5840 if (state->m_has_sawsw) { in write_gpio()
5841 if (state->uio_mask & 0x0001) { /* UIO-1 */ in write_gpio()
5842 /* write to io pad configuration register - output mode */ in write_gpio()
5844 state->m_gpio_cfg); in write_gpio()
5852 if ((state->m_gpio & 0x0001) == 0) in write_gpio()
5853 value &= 0x7FFF; /* write zero to 15th bit - 1st UIO */ in write_gpio()
5855 value |= 0x8000; /* write one to 15th bit - 1st UIO */ in write_gpio()
5861 if (state->uio_mask & 0x0002) { /* UIO-2 */ in write_gpio()
5862 /* write to io pad configuration register - output mode */ in write_gpio()
5864 state->m_gpio_cfg); in write_gpio()
5872 if ((state->m_gpio & 0x0002) == 0) in write_gpio()
5873 value &= 0xBFFF; /* write zero to 14th bit - 2st UIO */ in write_gpio()
5875 value |= 0x4000; /* write one to 14th bit - 2st UIO */ in write_gpio()
5881 if (state->uio_mask & 0x0004) { /* UIO-3 */ in write_gpio()
5882 /* write to io pad configuration register - output mode */ in write_gpio()
5884 state->m_gpio_cfg); in write_gpio()
5892 if ((state->m_gpio & 0x0004) == 0) in write_gpio()
5893 value &= 0xFFFB; /* write zero to 2nd bit - 3rd UIO */ in write_gpio()
5895 value |= 0x0004; /* write one to 2nd bit - 3rd UIO */ in write_gpio()
5917 if (!state->antenna_gpio) in switch_antenna_to_qam()
5920 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_qam()
5922 if (state->antenna_dvbt ^ gpio_state) { in switch_antenna_to_qam()
5923 /* Antenna is on DVB-T mode. Switch */ in switch_antenna_to_qam()
5924 if (state->antenna_dvbt) in switch_antenna_to_qam()
5925 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_qam()
5927 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_qam()
5942 if (!state->antenna_gpio) in switch_antenna_to_dvbt()
5945 gpio_state = state->m_gpio & state->antenna_gpio; in switch_antenna_to_dvbt()
5947 if (!(state->antenna_dvbt ^ gpio_state)) { in switch_antenna_to_dvbt()
5948 /* Antenna is on DVB-C mode. Switch */ in switch_antenna_to_dvbt()
5949 if (state->antenna_dvbt) in switch_antenna_to_dvbt()
5950 state->m_gpio |= state->antenna_gpio; in switch_antenna_to_dvbt()
5952 state->m_gpio &= ~state->antenna_gpio; in switch_antenna_to_dvbt()
5965 /* Set pins with possible pull-ups connected to them in input mode */ in power_down_device()
5972 if (state->m_b_p_down_open_bridge) { in power_down_device()
5990 state->m_hi_cfg_ctrl |= SIO_HI_RA_RAM_PAR_5_CFG_SLEEP_ZZZ; in power_down_device()
6006 if (state->m_drxk_state == DRXK_UNINITIALIZED) { in init_drxk()
6014 /* Soft reset of OFDM-, sys- and osc-clockdomain */ in init_drxk()
6029 state->m_drxk_a3_patch_code = true; in init_drxk()
6037 state->m_hi_cfg_bridge_delay = in init_drxk()
6038 (u16) ((state->m_osc_clock_freq / 1000) * in init_drxk()
6041 if (state->m_hi_cfg_bridge_delay > in init_drxk()
6043 state->m_hi_cfg_bridge_delay = in init_drxk()
6047 state->m_hi_cfg_bridge_delay += in init_drxk()
6048 state->m_hi_cfg_bridge_delay << in init_drxk()
6056 if (!(state->m_DRXK_A1_ROM_CODE) in init_drxk()
6057 && !(state->m_DRXK_A2_ROM_CODE)) in init_drxk()
6079 /* enable token-ring bus through OFDM block for possible ucode upload */ in init_drxk()
6094 if (state->fw) { in init_drxk()
6095 status = download_microcode(state, state->fw->data, in init_drxk()
6096 state->fw->size); in init_drxk()
6101 /* disable token-ring bus through OFDM block for possible ucode upload */ in init_drxk()
6181 status = mpegts_configure_pins(state, state->m_enable_mpeg_output); in init_drxk()
6189 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6191 if (state->m_b_power_down) { in init_drxk()
6195 state->m_drxk_state = DRXK_POWERED_DOWN; in init_drxk()
6197 state->m_drxk_state = DRXK_STOPPED; in init_drxk()
6201 if (state->m_has_dvbc) { in init_drxk()
6202 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_A; in init_drxk()
6203 state->frontend.ops.delsys[n++] = SYS_DVBC_ANNEX_C; in init_drxk()
6204 strlcat(state->frontend.ops.info.name, " DVB-C", in init_drxk()
6205 sizeof(state->frontend.ops.info.name)); in init_drxk()
6207 if (state->m_has_dvbt) { in init_drxk()
6208 state->frontend.ops.delsys[n++] = SYS_DVBT; in init_drxk()
6209 strlcat(state->frontend.ops.info.name, " DVB-T", in init_drxk()
6210 sizeof(state->frontend.ops.info.name)); in init_drxk()
6216 state->m_drxk_state = DRXK_NO_DEV; in init_drxk()
6232 state->microcode_name); in load_firmware_cb()
6234 state->microcode_name); in load_firmware_cb()
6235 state->microcode_name = NULL; in load_firmware_cb()
6241 * We might also change all DVB callbacks to return -ENODEV in load_firmware_cb()
6243 * As the DRX-K devices have their own internal firmware, in load_firmware_cb()
6248 state->fw = fw; in load_firmware_cb()
6255 struct drxk_state *state = fe->demodulator_priv; in drxk_release()
6258 release_firmware(state->fw); in drxk_release()
6265 struct drxk_state *state = fe->demodulator_priv; in drxk_sleep()
6269 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_sleep()
6270 return -ENODEV; in drxk_sleep()
6271 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_sleep()
6280 struct drxk_state *state = fe->demodulator_priv; in drxk_gate_ctrl()
6284 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_gate_ctrl()
6285 return -ENODEV; in drxk_gate_ctrl()
6292 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drxk_set_parameters()
6293 u32 delsys = p->delivery_system, old_delsys; in drxk_set_parameters()
6294 struct drxk_state *state = fe->demodulator_priv; in drxk_set_parameters()
6299 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_set_parameters()
6300 return -ENODEV; in drxk_set_parameters()
6302 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_set_parameters()
6303 return -EAGAIN; in drxk_set_parameters()
6305 if (!fe->ops.tuner_ops.get_if_frequency) { in drxk_set_parameters()
6307 return -EINVAL; in drxk_set_parameters()
6310 if (fe->ops.i2c_gate_ctrl) in drxk_set_parameters()
6311 fe->ops.i2c_gate_ctrl(fe, 1); in drxk_set_parameters()
6312 if (fe->ops.tuner_ops.set_params) in drxk_set_parameters()
6313 fe->ops.tuner_ops.set_params(fe); in drxk_set_parameters()
6314 if (fe->ops.i2c_gate_ctrl) in drxk_set_parameters()
6315 fe->ops.i2c_gate_ctrl(fe, 0); in drxk_set_parameters()
6317 old_delsys = state->props.delivery_system; in drxk_set_parameters()
6318 state->props = *p; in drxk_set_parameters()
6325 if (!state->m_has_dvbc) in drxk_set_parameters()
6326 return -EINVAL; in drxk_set_parameters()
6327 state->m_itut_annex_c = (delsys == SYS_DVBC_ANNEX_C) ? in drxk_set_parameters()
6329 if (state->m_itut_annex_c) in drxk_set_parameters()
6335 if (!state->m_has_dvbt) in drxk_set_parameters()
6336 return -EINVAL; in drxk_set_parameters()
6340 return -EINVAL; in drxk_set_parameters()
6344 fe->ops.tuner_ops.get_if_frequency(fe, &IF); in drxk_set_parameters()
6348 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drxk_set_parameters()
6349 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6350 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6351 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6352 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6353 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6354 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6355 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_set_parameters()
6378 rf_agc = state->m_dvbt_rf_agc_cfg; in get_strength()
6379 if_agc = state->m_dvbt_if_agc_cfg; in get_strength()
6381 rf_agc = state->m_qam_rf_agc_cfg; in get_strength()
6382 if_agc = state->m_qam_if_agc_cfg; in get_strength()
6384 rf_agc = state->m_atv_rf_agc_cfg; in get_strength()
6385 if_agc = state->m_atv_if_agc_cfg; in get_strength()
6404 /* Take RF gain into account */ in get_strength()
6413 agc_range = (u32) (rf_agc.max_output_level - rf_agc.min_output_level); in get_strength()
6417 ((u32)(rf_agc.output_level - rf_agc.min_output_level)) in get_strength()
6433 /* Take IF gain into account */ in get_strength()
6442 agc_range = (u32)(if_agc.max_output_level - if_agc.min_output_level); in get_strength()
6446 ((u32)(if_agc.output_level - if_agc.min_output_level)) in get_strength()
6465 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in drxk_get_stats()
6466 struct drxk_state *state = fe->demodulator_priv; in drxk_get_stats()
6479 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_stats()
6480 return -ENODEV; in drxk_get_stats()
6481 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_stats()
6482 return -EAGAIN; in drxk_get_stats()
6485 state->fe_status = 0; in drxk_get_stats()
6488 state->fe_status |= 0x1f; in drxk_get_stats()
6490 state->fe_status |= 0x0f; in drxk_get_stats()
6492 state->fe_status |= 0x07; in drxk_get_stats()
6497 get_strength(state, &c->strength.stat[0].uvalue); in drxk_get_stats()
6498 c->strength.stat[0].scale = FE_SCALE_RELATIVE; in drxk_get_stats()
6503 c->cnr.stat[0].svalue = cnr * 100; in drxk_get_stats()
6504 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; in drxk_get_stats()
6506 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6510 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6511 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6512 c->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6513 c->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6514 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6515 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_get_stats()
6540 /* Number of bit-errors */ in drxk_get_stats()
6567 c->block_error.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6568 c->block_error.stat[0].uvalue += pkt_error_count; in drxk_get_stats()
6569 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6570 c->block_count.stat[0].uvalue += pkt_count; in drxk_get_stats()
6572 c->pre_bit_error.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6573 c->pre_bit_error.stat[0].uvalue += pre_bit_err_count; in drxk_get_stats()
6574 c->pre_bit_count.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6575 c->pre_bit_count.stat[0].uvalue += pre_bit_count; in drxk_get_stats()
6577 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6578 c->post_bit_error.stat[0].uvalue += post_bit_err_count; in drxk_get_stats()
6579 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in drxk_get_stats()
6580 c->post_bit_count.stat[0].uvalue += post_bit_count; in drxk_get_stats()
6589 struct drxk_state *state = fe->demodulator_priv; in drxk_read_status()
6598 *status = state->fe_status; in drxk_read_status()
6606 struct drxk_state *state = fe->demodulator_priv; in drxk_read_signal_strength()
6607 struct dtv_frontend_properties *c = &fe->dtv_property_cache; in drxk_read_signal_strength()
6611 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_signal_strength()
6612 return -ENODEV; in drxk_read_signal_strength()
6613 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_signal_strength()
6614 return -EAGAIN; in drxk_read_signal_strength()
6616 *strength = c->strength.stat[0].uvalue; in drxk_read_signal_strength()
6622 struct drxk_state *state = fe->demodulator_priv; in drxk_read_snr()
6627 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_snr()
6628 return -ENODEV; in drxk_read_snr()
6629 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_snr()
6630 return -EAGAIN; in drxk_read_snr()
6643 struct drxk_state *state = fe->demodulator_priv; in drxk_read_ucblocks()
6648 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_read_ucblocks()
6649 return -ENODEV; in drxk_read_ucblocks()
6650 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_read_ucblocks()
6651 return -EAGAIN; in drxk_read_ucblocks()
6661 struct drxk_state *state = fe->demodulator_priv; in drxk_get_tune_settings()
6662 struct dtv_frontend_properties *p = &fe->dtv_property_cache; in drxk_get_tune_settings()
6666 if (state->m_drxk_state == DRXK_NO_DEV) in drxk_get_tune_settings()
6667 return -ENODEV; in drxk_get_tune_settings()
6668 if (state->m_drxk_state == DRXK_UNINITIALIZED) in drxk_get_tune_settings()
6669 return -EAGAIN; in drxk_get_tune_settings()
6671 switch (p->delivery_system) { in drxk_get_tune_settings()
6675 sets->min_delay_ms = 3000; in drxk_get_tune_settings()
6676 sets->max_drift = 0; in drxk_get_tune_settings()
6677 sets->step_size = 0; in drxk_get_tune_settings()
6680 return -EINVAL; in drxk_get_tune_settings()
6690 /* For DVB-C */
6693 /* For DVB-T */
6722 u8 adr = config->adr; in drxk_attach()
6730 state->i2c = i2c; in drxk_attach()
6731 state->demod_address = adr; in drxk_attach()
6732 state->single_master = config->single_master; in drxk_attach()
6733 state->microcode_name = config->microcode_name; in drxk_attach()
6734 state->qam_demod_parameter_count = config->qam_demod_parameter_count; in drxk_attach()
6735 state->no_i2c_bridge = config->no_i2c_bridge; in drxk_attach()
6736 state->antenna_gpio = config->antenna_gpio; in drxk_attach()
6737 state->antenna_dvbt = config->antenna_dvbt; in drxk_attach()
6738 state->m_chunk_size = config->chunk_size; in drxk_attach()
6739 state->enable_merr_cfg = config->enable_merr_cfg; in drxk_attach()
6741 if (config->dynamic_clk) { in drxk_attach()
6742 state->m_dvbt_static_clk = false; in drxk_attach()
6743 state->m_dvbc_static_clk = false; in drxk_attach()
6745 state->m_dvbt_static_clk = true; in drxk_attach()
6746 state->m_dvbc_static_clk = true; in drxk_attach()
6750 if (config->mpeg_out_clk_strength) in drxk_attach()
6751 state->m_ts_clockk_strength = config->mpeg_out_clk_strength & 0x07; in drxk_attach()
6753 state->m_ts_clockk_strength = 0x06; in drxk_attach()
6755 if (config->parallel_ts) in drxk_attach()
6756 state->m_enable_parallel = true; in drxk_attach()
6758 state->m_enable_parallel = false; in drxk_attach()
6761 state->uio_mask = config->antenna_gpio; in drxk_attach()
6763 /* Default gpio to DVB-C */ in drxk_attach()
6764 if (!state->antenna_dvbt && state->antenna_gpio) in drxk_attach()
6765 state->m_gpio |= state->antenna_gpio; in drxk_attach()
6767 state->m_gpio &= ~state->antenna_gpio; in drxk_attach()
6769 mutex_init(&state->mutex); in drxk_attach()
6771 memcpy(&state->frontend.ops, &drxk_ops, sizeof(drxk_ops)); in drxk_attach()
6772 state->frontend.demodulator_priv = state; in drxk_attach()
6776 /* Load firmware and initialize DRX-K */ in drxk_attach()
6777 if (state->microcode_name) { in drxk_attach()
6780 status = request_firmware(&fw, state->microcode_name, in drxk_attach()
6781 state->i2c->dev.parent); in drxk_attach()
6790 p = &state->frontend.dtv_property_cache; in drxk_attach()
6791 p->strength.len = 1; in drxk_attach()
6792 p->cnr.len = 1; in drxk_attach()
6793 p->block_error.len = 1; in drxk_attach()
6794 p->block_count.len = 1; in drxk_attach()
6795 p->pre_bit_error.len = 1; in drxk_attach()
6796 p->pre_bit_count.len = 1; in drxk_attach()
6797 p->post_bit_error.len = 1; in drxk_attach()
6798 p->post_bit_count.len = 1; in drxk_attach()
6800 p->strength.stat[0].scale = FE_SCALE_RELATIVE; in drxk_attach()
6801 p->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6802 p->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6803 p->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6804 p->pre_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6805 p->pre_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6806 p->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6807 p->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in drxk_attach()
6810 return &state->frontend; in drxk_attach()
6819 MODULE_DESCRIPTION("DRX-K driver");