Lines Matching full:rc
613 /* RC setting */
1370 pr_debug("drx3933 i2c operation addr=%x i2c=%p, wc=%x rc=%x\n", in drxbsp_i2c_write_read()
1415 int rc; in drxdap_fasi_read_block() local
1476 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, in drxdap_fasi_read_block()
1478 if (rc == 0) in drxdap_fasi_read_block()
1479 rc = drxbsp_i2c_write_read(NULL, 0, NULL, dev_addr, todo, data); in drxdap_fasi_read_block()
1482 rc = drxbsp_i2c_write_read(dev_addr, bufx, buf, dev_addr, todo, in drxdap_fasi_read_block()
1488 } while (datasize && rc == 0); in drxdap_fasi_read_block()
1490 return rc; in drxdap_fasi_read_block()
1517 int rc; in drxdap_fasi_read_reg16() local
1522 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); in drxdap_fasi_read_reg16()
1524 return rc; in drxdap_fasi_read_reg16()
1550 int rc; in drxdap_fasi_read_reg32() local
1555 rc = drxdap_fasi_read_block(dev_addr, addr, sizeof(*data), buf, flags); in drxdap_fasi_read_reg32()
1559 return rc; in drxdap_fasi_read_reg32()
1758 int rc = -EIO; in drxdap_fasi_read_modify_write_reg16() local
1764 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, DRXDAP_FASI_RMW); in drxdap_fasi_read_modify_write_reg16()
1765 if (rc == 0) in drxdap_fasi_read_modify_write_reg16()
1766 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, 0); in drxdap_fasi_read_modify_write_reg16()
1769 return rc; in drxdap_fasi_read_modify_write_reg16()
1831 int rc; in drxj_dap_rm_write_reg16short() local
1837 rc = drxdap_fasi_write_reg16(dev_addr, in drxj_dap_rm_write_reg16short()
1841 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1843 rc = drxdap_fasi_write_reg16(dev_addr, waddr, wdata, in drxj_dap_rm_write_reg16short()
1846 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1848 rc = drxdap_fasi_read_reg16(dev_addr, raddr, rdata, in drxj_dap_rm_write_reg16short()
1851 if (rc == 0) { in drxj_dap_rm_write_reg16short()
1853 rc = drxdap_fasi_write_reg16(dev_addr, in drxj_dap_rm_write_reg16short()
1858 return rc; in drxj_dap_rm_write_reg16short()
2099 int rc; in drxj_dap_atomic_read_write_block() local
2136 rc = hi_command(dev_addr, &hi_cmd, &dummy); in drxj_dap_atomic_read_write_block()
2137 if (rc != 0) { in drxj_dap_atomic_read_write_block()
2138 pr_err("error %d\n", rc); in drxj_dap_atomic_read_write_block()
2145 rc = drxj_dap_read_reg16(dev_addr, in drxj_dap_atomic_read_write_block()
2148 if (rc) { in drxj_dap_atomic_read_write_block()
2149 pr_err("error %d\n", rc); in drxj_dap_atomic_read_write_block()
2160 return rc; in drxj_dap_atomic_read_write_block()
2176 int rc; in drxj_dap_atomic_read_reg32() local
2182 rc = drxj_dap_atomic_read_write_block(dev_addr, addr, in drxj_dap_atomic_read_reg32()
2185 if (rc < 0) in drxj_dap_atomic_read_reg32()
2198 return rc; in drxj_dap_atomic_read_reg32()
2229 int rc; in hi_cfg_command() local
2241 rc = hi_command(demod->my_i2c_dev_addr, &hi_cmd, &result); in hi_cfg_command()
2242 if (rc != 0) { in hi_cfg_command()
2243 pr_err("error %d\n", rc); in hi_cfg_command()
2253 return rc; in hi_cfg_command()
2273 int rc; in hi_command() local
2280 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_6__A, cmd->param6, 0); in hi_command()
2281 if (rc != 0) { in hi_command()
2282 pr_err("error %d\n", rc); in hi_command()
2285 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_5__A, cmd->param5, 0); in hi_command()
2286 if (rc != 0) { in hi_command()
2287 pr_err("error %d\n", rc); in hi_command()
2290 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_4__A, cmd->param4, 0); in hi_command()
2291 if (rc != 0) { in hi_command()
2292 pr_err("error %d\n", rc); in hi_command()
2295 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_3__A, cmd->param3, 0); in hi_command()
2296 if (rc != 0) { in hi_command()
2297 pr_err("error %d\n", rc); in hi_command()
2302 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_2__A, cmd->param2, 0); in hi_command()
2303 if (rc != 0) { in hi_command()
2304 pr_err("error %d\n", rc); in hi_command()
2307 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_PAR_1__A, cmd->param1, 0); in hi_command()
2308 if (rc != 0) { in hi_command()
2309 pr_err("error %d\n", rc); in hi_command()
2322 rc = drxj_dap_write_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, cmd->cmd, 0); in hi_command()
2323 if (rc != 0) { in hi_command()
2324 pr_err("error %d\n", rc); in hi_command()
2341 rc = -ETIMEDOUT; in hi_command()
2346 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_CMD__A, &wait_cmd, 0); in hi_command()
2347 if (rc != 0) { in hi_command()
2348 pr_err("error %d\n", rc); in hi_command()
2354 rc = drxj_dap_read_reg16(dev_addr, SIO_HI_RA_RAM_RES__A, result, 0); in hi_command()
2355 if (rc != 0) { in hi_command()
2356 pr_err("error %d\n", rc); in hi_command()
2364 return rc; in hi_command()
2385 int rc; in init_hi() local
2392 rc = drxj_dap_write_reg16(dev_addr, 0x4301D7, 0x801, 0); in init_hi()
2393 if (rc != 0) { in init_hi()
2394 pr_err("error %d\n", rc); in init_hi()
2426 rc = hi_cfg_command(demod); in init_hi()
2427 if (rc != 0) { in init_hi()
2428 pr_err("error %d\n", rc); in init_hi()
2435 return rc; in init_hi()
2472 int rc; in get_device_capabilities() local
2478 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in get_device_capabilities()
2479 if (rc != 0) { in get_device_capabilities()
2480 pr_err("error %d\n", rc); in get_device_capabilities()
2483 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_OHW_CFG__A, &sio_pdr_ohw_cfg, 0); in get_device_capabilities()
2484 if (rc != 0) { in get_device_capabilities()
2485 pr_err("error %d\n", rc); in get_device_capabilities()
2488 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); in get_device_capabilities()
2489 if (rc != 0) { in get_device_capabilities()
2490 pr_err("error %d\n", rc); in get_device_capabilities()
2518 rc = drxdap_fasi_read_reg32(dev_addr, SIO_TOP_JTAGID_LO__A, &sio_top_jtagid_lo, 0); in get_device_capabilities()
2519 if (rc != 0) { in get_device_capabilities()
2520 pr_err("error %d\n", rc); in get_device_capabilities()
2527 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in get_device_capabilities()
2528 if (rc != 0) { in get_device_capabilities()
2529 pr_err("error %d\n", rc); in get_device_capabilities()
2532 rc = drxj_dap_read_reg16(dev_addr, SIO_PDR_UIO_IN_HI__A, &bid, 0); in get_device_capabilities()
2533 if (rc != 0) { in get_device_capabilities()
2534 pr_err("error %d\n", rc); in get_device_capabilities()
2538 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY__PRE, 0); in get_device_capabilities()
2539 if (rc != 0) { in get_device_capabilities()
2540 pr_err("error %d\n", rc); in get_device_capabilities()
2651 return rc; in get_device_capabilities()
2724 int rc; in ctrl_set_cfg_mpeg_output() local
2760 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_OCR_INVERT__A, 0, 0); in ctrl_set_cfg_mpeg_output()
2761 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2762 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2767 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, 7, 0); in ctrl_set_cfg_mpeg_output()
2768 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2769 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2772 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2773 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2774 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2777 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2778 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2779 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2782 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2783 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2784 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2787 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, 7, 0); in ctrl_set_cfg_mpeg_output()
2788 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2789 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2792 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 10, 0); in ctrl_set_cfg_mpeg_output()
2793 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2794 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2798 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 3, 0); in ctrl_set_cfg_mpeg_output()
2799 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2800 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2804 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2805 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2806 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2837 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_USAGE__A, FEC_OC_FCT_USAGE__PRE, 0); in ctrl_set_cfg_mpeg_output()
2838 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2839 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2842 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_CTL_UPD_RATE__A, FEC_OC_TMD_CTL_UPD_RATE__PRE, 0); in ctrl_set_cfg_mpeg_output()
2843 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2844 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2847 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_TMD_INT_UPD_RATE__A, 5, 0); in ctrl_set_cfg_mpeg_output()
2848 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2849 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2852 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_A__A, FEC_OC_AVR_PARM_A__PRE, 0); in ctrl_set_cfg_mpeg_output()
2853 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2854 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2857 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_AVR_PARM_B__A, FEC_OC_AVR_PARM_B__PRE, 0); in ctrl_set_cfg_mpeg_output()
2858 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2859 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2863 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, 0xD, 0); in ctrl_set_cfg_mpeg_output()
2864 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2865 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2869 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_RCN_GAIN__A, FEC_OC_RCN_GAIN__PRE, 0); in ctrl_set_cfg_mpeg_output()
2870 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2871 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2875 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_LWM__A, 2, 0); in ctrl_set_cfg_mpeg_output()
2876 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2877 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2880 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_HWM__A, 12, 0); in ctrl_set_cfg_mpeg_output()
2881 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2882 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2891 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); in ctrl_set_cfg_mpeg_output()
2892 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2893 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
2896 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_reg_ipr_mode, 0); in ctrl_set_cfg_mpeg_output()
2897 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
2898 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3053 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_HI__A, (u16)((dto_rate >> 16) & FEC_OC_DTO_RAT… in ctrl_set_cfg_mpeg_output()
3054 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3055 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3058 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_RATE_LO__A, (u16)(dto_rate & FEC_OC_DTO_RATE_LO_RAT… in ctrl_set_cfg_mpeg_output()
3059 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3060 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3063 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M | FEC_OC_DTO_MO… in ctrl_set_cfg_mpeg_output()
3064 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3065 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3068 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, FEC_OC_FCT_MODE_RAT_ENA__M | FEC_OC_FCT_MO… in ctrl_set_cfg_mpeg_output()
3069 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3070 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3073 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_BURST_LEN__A, fec_oc_dto_burst_len, 0); in ctrl_set_cfg_mpeg_output()
3074 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3075 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3080 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_PERIOD__A, fec_oc_dto_period, 0); in ctrl_set_cfg_mpeg_output()
3081 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3082 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3087 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DTO_MODE__A, FEC_OC_DTO_MODE_DYNAMIC__M, 0); in ctrl_set_cfg_mpeg_output()
3088 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3089 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3092 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_FCT_MODE__A, 0, 0); in ctrl_set_cfg_mpeg_output()
3093 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3094 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3099 rc = drxdap_fasi_write_reg32(dev_addr, FEC_OC_RCN_CTL_RATE_LO__A, rcn_rate, 0); in ctrl_set_cfg_mpeg_output()
3100 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3101 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3106 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode, 0); in ctrl_set_cfg_mpeg_output()
3107 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3108 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3111 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_reg_ipr_mode, 0); in ctrl_set_cfg_mpeg_output()
3112 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3113 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3116 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_INVERT__A, fec_oc_reg_ipr_invert, 0); in ctrl_set_cfg_mpeg_output()
3117 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3118 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3124 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_cfg_mpeg_output()
3125 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3126 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3130 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3131 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3132 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3135 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3136 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3137 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3140 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, MPEG_OUTPUT_CLK_DRIVE_STRENGTH << SIO_PDR… in ctrl_set_cfg_mpeg_output()
3141 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3142 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3145 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0013, 0); in ctrl_set_cfg_mpeg_output()
3146 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3147 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3153 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3154 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3155 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3163 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3164 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3165 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3168 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3169 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3170 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3173 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3174 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3175 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3178 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3179 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3180 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3183 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3184 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3185 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3188 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3189 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3190 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3193 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3194 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3195 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3198 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, sio_pdr_md_cfg, 0); in ctrl_set_cfg_mpeg_output()
3199 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3200 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3204 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3205 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3206 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3209 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3210 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3211 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3214 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3215 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3216 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3219 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3220 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3221 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3224 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3225 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3226 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3229 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3230 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3231 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3234 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3235 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3236 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3241 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3242 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3243 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3247 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3248 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3249 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3254 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_cfg_mpeg_output()
3255 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3256 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3260 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MSTRT_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3261 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3262 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3265 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MERR_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3266 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3267 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3270 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MCLK_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3271 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3272 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3275 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MVAL_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3276 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3277 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3280 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD0_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3281 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3282 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3285 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD1_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3286 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3287 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3290 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD2_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3291 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3292 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3295 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD3_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3296 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3297 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3300 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD4_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3301 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3302 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3305 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD5_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3306 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3307 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3310 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD6_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3311 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3312 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3315 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MD7_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3316 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3317 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3321 rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_MON_CFG__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3322 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3323 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3327 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_cfg_mpeg_output()
3328 if (rc != 0) { in ctrl_set_cfg_mpeg_output()
3329 pr_err("error %d\n", rc); in ctrl_set_cfg_mpeg_output()
3339 return rc; in ctrl_set_cfg_mpeg_output()
3366 int rc; in set_mpegtei_handling() local
3374 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_DPR_MODE__A, &fec_oc_dpr_mode, 0); in set_mpegtei_handling()
3375 if (rc != 0) { in set_mpegtei_handling()
3376 pr_err("error %d\n", rc); in set_mpegtei_handling()
3379 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); in set_mpegtei_handling()
3380 if (rc != 0) { in set_mpegtei_handling()
3381 pr_err("error %d\n", rc); in set_mpegtei_handling()
3384 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_EMS_MODE__A, &fec_oc_ems_mode, 0); in set_mpegtei_handling()
3385 if (rc != 0) { in set_mpegtei_handling()
3386 pr_err("error %d\n", rc); in set_mpegtei_handling()
3404 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_DPR_MODE__A, fec_oc_dpr_mode, 0); in set_mpegtei_handling()
3405 if (rc != 0) { in set_mpegtei_handling()
3406 pr_err("error %d\n", rc); in set_mpegtei_handling()
3409 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode, 0); in set_mpegtei_handling()
3410 if (rc != 0) { in set_mpegtei_handling()
3411 pr_err("error %d\n", rc); in set_mpegtei_handling()
3414 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_EMS_MODE__A, fec_oc_ems_mode, 0); in set_mpegtei_handling()
3415 if (rc != 0) { in set_mpegtei_handling()
3416 pr_err("error %d\n", rc); in set_mpegtei_handling()
3422 return rc; in set_mpegtei_handling()
3439 int rc; in bit_reverse_mpeg_output() local
3445 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_IPR_MODE__A, &fec_oc_ipr_mode, 0); in bit_reverse_mpeg_output()
3446 if (rc != 0) { in bit_reverse_mpeg_output()
3447 pr_err("error %d\n", rc); in bit_reverse_mpeg_output()
3457 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_IPR_MODE__A, fec_oc_ipr_mode, 0); in bit_reverse_mpeg_output()
3458 if (rc != 0) { in bit_reverse_mpeg_output()
3459 pr_err("error %d\n", rc); in bit_reverse_mpeg_output()
3465 return rc; in bit_reverse_mpeg_output()
3483 int rc; in set_mpeg_start_width() local
3492 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_COMM_MB__A, &fec_oc_comm_mb, 0); in set_mpeg_start_width()
3493 if (rc != 0) { in set_mpeg_start_width()
3494 pr_err("error %d\n", rc); in set_mpeg_start_width()
3500 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_COMM_MB__A, fec_oc_comm_mb, 0); in set_mpeg_start_width()
3501 if (rc != 0) { in set_mpeg_start_width()
3502 pr_err("error %d\n", rc); in set_mpeg_start_width()
3509 return rc; in set_mpeg_start_width()
3529 int rc; in ctrl_set_uio_cfg() local
3537 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_set_uio_cfg()
3538 if (rc != 0) { in ctrl_set_uio_cfg()
3539 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3557 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3558 if (rc != 0) { in ctrl_set_uio_cfg()
3559 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3580 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3581 if (rc != 0) { in ctrl_set_uio_cfg()
3582 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3603 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3604 if (rc != 0) { in ctrl_set_uio_cfg()
3605 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3624 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, 0, 0); in ctrl_set_uio_cfg()
3625 if (rc != 0) { in ctrl_set_uio_cfg()
3626 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3642 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_uio_cfg()
3643 if (rc != 0) { in ctrl_set_uio_cfg()
3644 pr_err("error %d\n", rc); in ctrl_set_uio_cfg()
3650 return rc; in ctrl_set_uio_cfg()
3664 int rc; in ctrl_uio_write() local
3674 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in ctrl_uio_write()
3675 if (rc != 0) { in ctrl_uio_write()
3676 pr_err("error %d\n", rc); in ctrl_uio_write()
3696 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3697 if (rc != 0) { in ctrl_uio_write()
3698 pr_err("error %d\n", rc); in ctrl_uio_write()
3703 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3704 if (rc != 0) { in ctrl_uio_write()
3705 pr_err("error %d\n", rc); in ctrl_uio_write()
3714 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3715 if (rc != 0) { in ctrl_uio_write()
3716 pr_err("error %d\n", rc); in ctrl_uio_write()
3735 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_RX_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3736 if (rc != 0) { in ctrl_uio_write()
3737 pr_err("error %d\n", rc); in ctrl_uio_write()
3742 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3743 if (rc != 0) { in ctrl_uio_write()
3744 pr_err("error %d\n", rc); in ctrl_uio_write()
3753 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3754 if (rc != 0) { in ctrl_uio_write()
3755 pr_err("error %d\n", rc); in ctrl_uio_write()
3774 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_GPIO_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3775 if (rc != 0) { in ctrl_uio_write()
3776 pr_err("error %d\n", rc); in ctrl_uio_write()
3781 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, &value, 0); in ctrl_uio_write()
3782 if (rc != 0) { in ctrl_uio_write()
3783 pr_err("error %d\n", rc); in ctrl_uio_write()
3792 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_HI__A, value, 0); in ctrl_uio_write()
3793 if (rc != 0) { in ctrl_uio_write()
3794 pr_err("error %d\n", rc); in ctrl_uio_write()
3814 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_IRQN_CFG__A, pin_cfg_value, 0); in ctrl_uio_write()
3815 if (rc != 0) { in ctrl_uio_write()
3816 pr_err("error %d\n", rc); in ctrl_uio_write()
3821 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, &value, 0); in ctrl_uio_write()
3822 if (rc != 0) { in ctrl_uio_write()
3823 pr_err("error %d\n", rc); in ctrl_uio_write()
3832 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_UIO_OUT_LO__A, value, 0); in ctrl_uio_write()
3833 if (rc != 0) { in ctrl_uio_write()
3834 pr_err("error %d\n", rc); in ctrl_uio_write()
3844 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_uio_write()
3845 if (rc != 0) { in ctrl_uio_write()
3846 pr_err("error %d\n", rc); in ctrl_uio_write()
3852 return rc; in ctrl_uio_write()
3909 int rc; in smart_ant_init() local
3916 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, SIO_TOP_COMM_KEY_KEY, 0); in smart_ant_init()
3917 if (rc != 0) { in smart_ant_init()
3918 pr_err("error %d\n", rc); in smart_ant_init()
3922 rc = drxj_dap_read_reg16(dev_addr, SIO_SA_TX_COMMAND__A, &data, 0); in smart_ant_init()
3923 if (rc != 0) { in smart_ant_init()
3924 pr_err("error %d\n", rc); in smart_ant_init()
3928 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data | SIO_SA_TX_COMMAND_TX_INVERT__M) … in smart_ant_init()
3929 if (rc != 0) { in smart_ant_init()
3930 pr_err("error %d\n", rc); in smart_ant_init()
3934 …rc = drxj_dap_write_reg16(dev_addr, SIO_SA_TX_COMMAND__A, (data & (~SIO_SA_TX_COMMAND_TX_INVERT__M… in smart_ant_init()
3935 if (rc != 0) { in smart_ant_init()
3936 pr_err("error %d\n", rc); in smart_ant_init()
3942 rc = ctrl_set_uio_cfg(demod, &uio_cfg); in smart_ant_init()
3943 if (rc != 0) { in smart_ant_init()
3944 pr_err("error %d\n", rc); in smart_ant_init()
3947 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_CFG__A, 0x13, 0); in smart_ant_init()
3948 if (rc != 0) { in smart_ant_init()
3949 pr_err("error %d\n", rc); in smart_ant_init()
3952 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_PDR_SMA_TX_GPIO_FNC__A, 0x03, 0); in smart_ant_init()
3953 if (rc != 0) { in smart_ant_init()
3954 pr_err("error %d\n", rc); in smart_ant_init()
3959 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in smart_ant_init()
3960 if (rc != 0) { in smart_ant_init()
3961 pr_err("error %d\n", rc); in smart_ant_init()
3967 return rc; in smart_ant_init()
3972 int rc; in scu_command() local
3981 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); in scu_command()
3982 if (rc != 0) { in scu_command()
3983 pr_err("error %d\n", rc); in scu_command()
3991 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_4__A, *(cmd->parameter + 4), 0); in scu_command()
3992 if (rc != 0) { in scu_command()
3993 pr_err("error %d\n", rc); in scu_command()
3998 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_3__A, *(cmd->parameter + 3), 0); in scu_command()
3999 if (rc != 0) { in scu_command()
4000 pr_err("error %d\n", rc); in scu_command()
4005 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_2__A, *(cmd->parameter + 2), 0); in scu_command()
4006 if (rc != 0) { in scu_command()
4007 pr_err("error %d\n", rc); in scu_command()
4012 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_1__A, *(cmd->parameter + 1), 0); in scu_command()
4013 if (rc != 0) { in scu_command()
4014 pr_err("error %d\n", rc); in scu_command()
4019 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_PARAM_0__A, *(cmd->parameter + 0), 0); in scu_command()
4020 if (rc != 0) { in scu_command()
4021 pr_err("error %d\n", rc); in scu_command()
4032 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_COMMAND__A, cmd->command, 0); in scu_command()
4033 if (rc != 0) { in scu_command()
4034 pr_err("error %d\n", rc); in scu_command()
4041 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_COMMAND__A, &cur_cmd, 0); in scu_command()
4042 if (rc != 0) { in scu_command()
4043 pr_err("error %d\n", rc); in scu_command()
4060 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_3__A, cmd->result + 3, 0); in scu_command()
4061 if (rc != 0) { in scu_command()
4062 pr_err("error %d\n", rc); in scu_command()
4067 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_2__A, cmd->result + 2, 0); in scu_command()
4068 if (rc != 0) { in scu_command()
4069 pr_err("error %d\n", rc); in scu_command()
4074 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_1__A, cmd->result + 1, 0); in scu_command()
4075 if (rc != 0) { in scu_command()
4076 pr_err("error %d\n", rc); in scu_command()
4081 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_PARAM_0__A, cmd->result + 0, 0); in scu_command()
4082 if (rc != 0) { in scu_command()
4083 pr_err("error %d\n", rc); in scu_command()
4116 return rc; in scu_command()
4137 int rc; in drxj_dap_scu_atomic_read_write_block() local
4167 rc = scu_command(dev_addr, &scu_cmd); in drxj_dap_scu_atomic_read_write_block()
4168 if (rc != 0) { in drxj_dap_scu_atomic_read_write_block()
4169 pr_err("error %d\n", rc); in drxj_dap_scu_atomic_read_write_block()
4185 return rc; in drxj_dap_scu_atomic_read_write_block()
4201 int rc; in drxj_dap_scu_atomic_read_reg16() local
4207 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, true); in drxj_dap_scu_atomic_read_reg16()
4208 if (rc < 0) in drxj_dap_scu_atomic_read_reg16()
4209 return rc; in drxj_dap_scu_atomic_read_reg16()
4215 return rc; in drxj_dap_scu_atomic_read_reg16()
4229 int rc; in drxj_dap_scu_atomic_write_reg16() local
4234 rc = drxj_dap_scu_atomic_read_write_block(dev_addr, addr, 2, buf, false); in drxj_dap_scu_atomic_write_reg16()
4236 return rc; in drxj_dap_scu_atomic_write_reg16()
4252 int rc; in adc_sync_measurement() local
4258 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_COMM_EXEC__A, IQM_AF_COMM_EXEC_ACTIVE, 0); in adc_sync_measurement()
4259 if (rc != 0) { in adc_sync_measurement()
4260 pr_err("error %d\n", rc); in adc_sync_measurement()
4263 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_START_LOCK__A, 1, 0); in adc_sync_measurement()
4264 if (rc != 0) { in adc_sync_measurement()
4265 pr_err("error %d\n", rc); in adc_sync_measurement()
4273 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE0__A, &data, 0); in adc_sync_measurement()
4274 if (rc != 0) { in adc_sync_measurement()
4275 pr_err("error %d\n", rc); in adc_sync_measurement()
4280 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE1__A, &data, 0); in adc_sync_measurement()
4281 if (rc != 0) { in adc_sync_measurement()
4282 pr_err("error %d\n", rc); in adc_sync_measurement()
4287 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_PHASE2__A, &data, 0); in adc_sync_measurement()
4288 if (rc != 0) { in adc_sync_measurement()
4289 pr_err("error %d\n", rc); in adc_sync_measurement()
4297 return rc; in adc_sync_measurement()
4315 int rc; in adc_synchronization() local
4320 rc = adc_sync_measurement(demod, &count); in adc_synchronization()
4321 if (rc != 0) { in adc_synchronization()
4322 pr_err("error %d\n", rc); in adc_synchronization()
4330 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_CLKNEG__A, &clk_neg, 0); in adc_synchronization()
4331 if (rc != 0) { in adc_synchronization()
4332 pr_err("error %d\n", rc); in adc_synchronization()
4337 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLKNEG__A, clk_neg, 0); in adc_synchronization()
4338 if (rc != 0) { in adc_synchronization()
4339 pr_err("error %d\n", rc); in adc_synchronization()
4343 rc = adc_sync_measurement(demod, &count); in adc_synchronization()
4344 if (rc != 0) { in adc_synchronization()
4345 pr_err("error %d\n", rc); in adc_synchronization()
4356 return rc; in adc_synchronization()
4382 int rc; in init_agc() local
4416 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); in init_agc()
4417 if (rc != 0) { in init_agc()
4418 pr_err("error %d\n", rc); in init_agc()
4421 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); in init_agc()
4422 if (rc != 0) { in init_agc()
4423 pr_err("error %d\n", rc); in init_agc()
4426 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); in init_agc()
4427 if (rc != 0) { in init_agc()
4428 pr_err("error %d\n", rc); in init_agc()
4431 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); in init_agc()
4432 if (rc != 0) { in init_agc()
4433 pr_err("error %d\n", rc); in init_agc()
4436 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); in init_agc()
4437 if (rc != 0) { in init_agc()
4438 pr_err("error %d\n", rc); in init_agc()
4441 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); in init_agc()
4442 if (rc != 0) { in init_agc()
4443 pr_err("error %d\n", rc); in init_agc()
4446 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); in init_agc()
4447 if (rc != 0) { in init_agc()
4448 pr_err("error %d\n", rc); in init_agc()
4451 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); in init_agc()
4452 if (rc != 0) { in init_agc()
4453 pr_err("error %d\n", rc); in init_agc()
4456 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); in init_agc()
4457 if (rc != 0) { in init_agc()
4458 pr_err("error %d\n", rc); in init_agc()
4461 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); in init_agc()
4462 if (rc != 0) { in init_agc()
4463 pr_err("error %d\n", rc); in init_agc()
4466 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, 1024, 0); in init_agc()
4467 if (rc != 0) { in init_agc()
4468 pr_err("error %d\n", rc); in init_agc()
4471 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_VSB_AGC_POW_TGT__A, 22600, 0); in init_agc()
4472 if (rc != 0) { in init_agc()
4473 pr_err("error %d\n", rc); in init_agc()
4476 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, 13200, 0); in init_agc()
4477 if (rc != 0) { in init_agc()
4478 pr_err("error %d\n", rc); in init_agc()
4499 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MINGAIN__A, 0x7fff, 0); in init_agc()
4500 if (rc != 0) { in init_agc()
4501 pr_err("error %d\n", rc); in init_agc()
4504 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXGAIN__A, 0x0, 0); in init_agc()
4505 if (rc != 0) { in init_agc()
4506 pr_err("error %d\n", rc); in init_agc()
4509 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM__A, 0, 0); in init_agc()
4510 if (rc != 0) { in init_agc()
4511 pr_err("error %d\n", rc); in init_agc()
4514 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCCNT__A, 0, 0); in init_agc()
4515 if (rc != 0) { in init_agc()
4516 pr_err("error %d\n", rc); in init_agc()
4519 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_WD__A, 0, 0); in init_agc()
4520 if (rc != 0) { in init_agc()
4521 pr_err("error %d\n", rc); in init_agc()
4524 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_STP__A, 1, 0); in init_agc()
4525 if (rc != 0) { in init_agc()
4526 pr_err("error %d\n", rc); in init_agc()
4529 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM__A, 0, 0); in init_agc()
4530 if (rc != 0) { in init_agc()
4531 pr_err("error %d\n", rc); in init_agc()
4534 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCCNT__A, 0, 0); in init_agc()
4535 if (rc != 0) { in init_agc()
4536 pr_err("error %d\n", rc); in init_agc()
4539 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_WD__A, 0, 0); in init_agc()
4540 if (rc != 0) { in init_agc()
4541 pr_err("error %d\n", rc); in init_agc()
4544 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_STP__A, 1, 0); in init_agc()
4545 if (rc != 0) { in init_agc()
4546 pr_err("error %d\n", rc); in init_agc()
4551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT__A, p_agc_if_settings->top, 0); in init_agc()
4552 if (rc != 0) { in init_agc()
4553 pr_err("error %d\n", rc); in init_agc()
4557 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &agc_ki, 0); in init_agc()
4558 if (rc != 0) { in init_agc()
4559 pr_err("error %d\n", rc); in init_agc()
4563 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, agc_ki, 0); in init_agc()
4564 if (rc != 0) { in init_agc()
4565 pr_err("error %d\n", rc); in init_agc()
4575 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, p_agc_if_settings->top, 0); in init_agc()
4576 if (rc != 0) { in init_agc()
4577 pr_err("error %d\n", rc); in init_agc()
4580 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN__A, p_agc_if_settings->top, 0); in init_agc()
4581 if (rc != 0) { in init_agc()
4582 pr_err("error %d\n", rc); in init_agc()
4585 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_INGAIN_TGT_MAX__A, ingain_tgt_max, 0); in init_agc()
4586 if (rc != 0) { in init_agc()
4587 pr_err("error %d\n", rc); in init_agc()
4590 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MIN__A, if_iaccu_hi_tgt_min, 0); in init_agc()
4591 if (rc != 0) { in init_agc()
4592 pr_err("error %d\n", rc); in init_agc()
4595 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_HI__A, 0, 0); in init_agc()
4596 if (rc != 0) { in init_agc()
4597 pr_err("error %d\n", rc); in init_agc()
4600 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_IF_IACCU_LO__A, 0, 0); in init_agc()
4601 if (rc != 0) { in init_agc()
4602 pr_err("error %d\n", rc); in init_agc()
4605 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, 0, 0); in init_agc()
4606 if (rc != 0) { in init_agc()
4607 pr_err("error %d\n", rc); in init_agc()
4610 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_IACCU_LO__A, 0, 0); in init_agc()
4611 if (rc != 0) { in init_agc()
4612 pr_err("error %d\n", rc); in init_agc()
4615 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_RF_MAX__A, 32767, 0); in init_agc()
4616 if (rc != 0) { in init_agc()
4617 pr_err("error %d\n", rc); in init_agc()
4620 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MAX__A, clp_sum_max, 0); in init_agc()
4621 if (rc != 0) { in init_agc()
4622 pr_err("error %d\n", rc); in init_agc()
4625 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MAX__A, sns_sum_max, 0); in init_agc()
4626 if (rc != 0) { in init_agc()
4627 pr_err("error %d\n", rc); in init_agc()
4630 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_INNERGAIN_MIN__A, ki_innergain_min, 0); in init_agc()
4631 if (rc != 0) { in init_agc()
4632 pr_err("error %d\n", rc); in init_agc()
4635 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_SNS_CTRL_DELAY__A, 50, 0); in init_agc()
4636 if (rc != 0) { in init_agc()
4637 pr_err("error %d\n", rc); in init_agc()
4640 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_CYCLEN__A, 500, 0); in init_agc()
4641 if (rc != 0) { in init_agc()
4642 pr_err("error %d\n", rc); in init_agc()
4645 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_CYCLEN__A, 500, 0); in init_agc()
4646 if (rc != 0) { in init_agc()
4647 pr_err("error %d\n", rc); in init_agc()
4650 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAXMINGAIN_TH__A, 20, 0); in init_agc()
4651 if (rc != 0) { in init_agc()
4652 pr_err("error %d\n", rc); in init_agc()
4655 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MIN__A, ki_min, 0); in init_agc()
4656 if (rc != 0) { in init_agc()
4657 pr_err("error %d\n", rc); in init_agc()
4660 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_MAX__A, ki_max, 0); in init_agc()
4661 if (rc != 0) { in init_agc()
4662 pr_err("error %d\n", rc); in init_agc()
4665 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI_RED__A, 0, 0); in init_agc()
4666 if (rc != 0) { in init_agc()
4667 pr_err("error %d\n", rc); in init_agc()
4670 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_SUM_MIN__A, 8, 0); in init_agc()
4671 if (rc != 0) { in init_agc()
4672 pr_err("error %d\n", rc); in init_agc()
4675 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CYCLEN__A, 500, 0); in init_agc()
4676 if (rc != 0) { in init_agc()
4677 pr_err("error %d\n", rc); in init_agc()
4680 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_DIR_TO__A, clp_dir_to, 0); in init_agc()
4681 if (rc != 0) { in init_agc()
4682 pr_err("error %d\n", rc); in init_agc()
4685 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_SUM_MIN__A, 8, 0); in init_agc()
4686 if (rc != 0) { in init_agc()
4687 pr_err("error %d\n", rc); in init_agc()
4690 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_SNS_DIR_TO__A, sns_dir_to, 0); in init_agc()
4691 if (rc != 0) { in init_agc()
4692 pr_err("error %d\n", rc); in init_agc()
4695 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_FAST_CLP_CTRL_DELAY__A, 50, 0); in init_agc()
4696 if (rc != 0) { in init_agc()
4697 pr_err("error %d\n", rc); in init_agc()
4700 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_CLP_CTRL_MODE__A, clp_ctrl_mode, 0); in init_agc()
4701 if (rc != 0) { in init_agc()
4702 pr_err("error %d\n", rc); in init_agc()
4714 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_RF__A, agc_rf, 0); in init_agc()
4715 if (rc != 0) { in init_agc()
4716 pr_err("error %d\n", rc); in init_agc()
4719 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AGC_IF__A, agc_if, 0); in init_agc()
4720 if (rc != 0) { in init_agc()
4721 pr_err("error %d\n", rc); in init_agc()
4726 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in init_agc()
4727 if (rc != 0) { in init_agc()
4728 pr_err("error %d\n", rc); in init_agc()
4733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in init_agc()
4734 if (rc != 0) { in init_agc()
4735 pr_err("error %d\n", rc); in init_agc()
4741 return rc; in init_agc()
4758 int rc; in set_frequency() local
4829 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); in set_frequency()
4830 if (rc != 0) { in set_frequency()
4831 pr_err("error %d\n", rc); in set_frequency()
4839 return rc; in set_frequency()
4855 int rc; in get_acc_pkt_err() local
4865 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, &data, 0); in get_acc_pkt_err()
4866 if (rc != 0) { in get_acc_pkt_err()
4867 pr_err("error %d\n", rc); in get_acc_pkt_err()
4887 return rc; in get_acc_pkt_err()
4908 int rc; in set_agc_rf() local
4936 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
4937 if (rc != 0) { in set_agc_rf()
4938 pr_err("error %d\n", rc); in set_agc_rf()
4942 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
4943 if (rc != 0) { in set_agc_rf()
4944 pr_err("error %d\n", rc); in set_agc_rf()
4949 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
4950 if (rc != 0) { in set_agc_rf()
4951 pr_err("error %d\n", rc); in set_agc_rf()
4966 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
4967 if (rc != 0) { in set_agc_rf()
4968 pr_err("error %d\n", rc); in set_agc_rf()
4973 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); in set_agc_rf()
4974 if (rc != 0) { in set_agc_rf()
4975 pr_err("error %d\n", rc); in set_agc_rf()
4979 …rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_RAG… in set_agc_rf()
4980 if (rc != 0) { in set_agc_rf()
4981 pr_err("error %d\n", rc); in set_agc_rf()
4996 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->top, 0); in set_agc_rf()
4997 if (rc != 0) { in set_agc_rf()
4998 pr_err("error %d\n", rc); in set_agc_rf()
5001 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, agc_settings->top, 0); in set_agc_rf()
5002 if (rc != 0) { in set_agc_rf()
5003 pr_err("error %d\n", rc); in set_agc_rf()
5009 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI_CO__A, agc_settings->cut_off_current, 0); in set_agc_rf()
5010 if (rc != 0) { in set_agc_rf()
5011 pr_err("error %d\n", rc); in set_agc_rf()
5018 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
5019 if (rc != 0) { in set_agc_rf()
5020 pr_err("error %d\n", rc); in set_agc_rf()
5024 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
5025 if (rc != 0) { in set_agc_rf()
5026 pr_err("error %d\n", rc); in set_agc_rf()
5031 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
5032 if (rc != 0) { in set_agc_rf()
5033 pr_err("error %d\n", rc); in set_agc_rf()
5041 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
5042 if (rc != 0) { in set_agc_rf()
5043 pr_err("error %d\n", rc); in set_agc_rf()
5048 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_RF_IACCU_HI__A, agc_settings->output_level, 0); in set_agc_rf()
5049 if (rc != 0) { in set_agc_rf()
5050 pr_err("error %d\n", rc); in set_agc_rf()
5057 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_rf()
5058 if (rc != 0) { in set_agc_rf()
5059 pr_err("error %d\n", rc); in set_agc_rf()
5063 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_rf()
5064 if (rc != 0) { in set_agc_rf()
5065 pr_err("error %d\n", rc); in set_agc_rf()
5070 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_rf()
5071 if (rc != 0) { in set_agc_rf()
5072 pr_err("error %d\n", rc); in set_agc_rf()
5076 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_rf()
5077 if (rc != 0) { in set_agc_rf()
5078 pr_err("error %d\n", rc); in set_agc_rf()
5105 return rc; in set_agc_rf()
5124 int rc; in set_agc_if() local
5149 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5150 if (rc != 0) { in set_agc_if()
5151 pr_err("error %d\n", rc); in set_agc_if()
5155 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5156 if (rc != 0) { in set_agc_if()
5157 pr_err("error %d\n", rc); in set_agc_if()
5162 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5163 if (rc != 0) { in set_agc_if()
5164 pr_err("error %d\n", rc); in set_agc_if()
5180 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5181 if (rc != 0) { in set_agc_if()
5182 pr_err("error %d\n", rc); in set_agc_if()
5187 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI_RED__A, &data, 0); in set_agc_if()
5188 if (rc != 0) { in set_agc_if()
5189 pr_err("error %d\n", rc); in set_agc_if()
5193 …rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_KI_RED__A, (~(agc_settings->speed << SCU_RAM_AGC_KI_RED_IA… in set_agc_if()
5194 if (rc != 0) { in set_agc_if()
5195 pr_err("error %d\n", rc); in set_agc_if()
5210 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, p_agc_settings->top, 0); in set_agc_if()
5211 if (rc != 0) { in set_agc_if()
5212 pr_err("error %d\n", rc); in set_agc_if()
5215 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, p_agc_settings->top, 0); in set_agc_if()
5216 if (rc != 0) { in set_agc_if()
5217 pr_err("error %d\n", rc); in set_agc_if()
5221 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, 0, 0); in set_agc_if()
5222 if (rc != 0) { in set_agc_if()
5223 pr_err("error %d\n", rc); in set_agc_if()
5226 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT__A, 0, 0); in set_agc_if()
5227 if (rc != 0) { in set_agc_if()
5228 pr_err("error %d\n", rc); in set_agc_if()
5237 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5238 if (rc != 0) { in set_agc_if()
5239 pr_err("error %d\n", rc); in set_agc_if()
5243 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5244 if (rc != 0) { in set_agc_if()
5245 pr_err("error %d\n", rc); in set_agc_if()
5250 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5251 if (rc != 0) { in set_agc_if()
5252 pr_err("error %d\n", rc); in set_agc_if()
5261 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5262 if (rc != 0) { in set_agc_if()
5263 pr_err("error %d\n", rc); in set_agc_if()
5268 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_IF_IACCU_HI_TGT_MAX__A, agc_settings->output_level, 0); in set_agc_if()
5269 if (rc != 0) { in set_agc_if()
5270 pr_err("error %d\n", rc); in set_agc_if()
5278 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_agc_if()
5279 if (rc != 0) { in set_agc_if()
5280 pr_err("error %d\n", rc); in set_agc_if()
5284 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_agc_if()
5285 if (rc != 0) { in set_agc_if()
5286 pr_err("error %d\n", rc); in set_agc_if()
5291 rc = (*scu_rr16)(dev_addr, SCU_RAM_AGC_KI__A, &data, 0); in set_agc_if()
5292 if (rc != 0) { in set_agc_if()
5293 pr_err("error %d\n", rc); in set_agc_if()
5298 rc = (*scu_wr16)(dev_addr, SCU_RAM_AGC_KI__A, data, 0); in set_agc_if()
5299 if (rc != 0) { in set_agc_if()
5300 pr_err("error %d\n", rc); in set_agc_if()
5309 rc = (*scu_wr16) (dev_addr, SCU_RAM_AGC_INGAIN_TGT_MIN__A, agc_settings->top, 0); in set_agc_if()
5310 if (rc != 0) { in set_agc_if()
5311 pr_err("error %d\n", rc); in set_agc_if()
5334 return rc; in set_agc_if()
5348 int rc; in set_iqm_af() local
5353 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_STDBY__A, &data, 0); in set_iqm_af()
5354 if (rc != 0) { in set_iqm_af()
5355 pr_err("error %d\n", rc); in set_iqm_af()
5362 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, data, 0); in set_iqm_af()
5363 if (rc != 0) { in set_iqm_af()
5364 pr_err("error %d\n", rc); in set_iqm_af()
5370 return rc; in set_iqm_af()
5400 int rc; in power_down_vsb() local
5413 rc = scu_command(dev_addr, &cmd_scu); in power_down_vsb()
5414 if (rc != 0) { in power_down_vsb()
5415 pr_err("error %d\n", rc); in power_down_vsb()
5420 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in power_down_vsb()
5421 if (rc != 0) { in power_down_vsb()
5422 pr_err("error %d\n", rc); in power_down_vsb()
5425 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); in power_down_vsb()
5426 if (rc != 0) { in power_down_vsb()
5427 pr_err("error %d\n", rc); in power_down_vsb()
5431 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_vsb()
5432 if (rc != 0) { in power_down_vsb()
5433 pr_err("error %d\n", rc); in power_down_vsb()
5436 rc = set_iqm_af(demod, false); in power_down_vsb()
5437 if (rc != 0) { in power_down_vsb()
5438 pr_err("error %d\n", rc); in power_down_vsb()
5442 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_vsb()
5443 if (rc != 0) { in power_down_vsb()
5444 pr_err("error %d\n", rc); in power_down_vsb()
5447 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_vsb()
5448 if (rc != 0) { in power_down_vsb()
5449 pr_err("error %d\n", rc); in power_down_vsb()
5452 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_vsb()
5453 if (rc != 0) { in power_down_vsb()
5454 pr_err("error %d\n", rc); in power_down_vsb()
5457 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_vsb()
5458 if (rc != 0) { in power_down_vsb()
5459 pr_err("error %d\n", rc); in power_down_vsb()
5462 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_vsb()
5463 if (rc != 0) { in power_down_vsb()
5464 pr_err("error %d\n", rc); in power_down_vsb()
5470 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in power_down_vsb()
5471 if (rc != 0) { in power_down_vsb()
5472 pr_err("error %d\n", rc); in power_down_vsb()
5478 return rc; in power_down_vsb()
5490 int rc; in set_vsb_leak_n_gain() local
5681 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM0_FFETRAINLKRATIO1__A, sizeof(vsb_ffe_leak_g… in set_vsb_leak_n_gain()
5682 if (rc != 0) { in set_vsb_leak_n_gain()
5683 pr_err("error %d\n", rc); in set_vsb_leak_n_gain()
5686 …rc = drxdap_fasi_write_block(dev_addr, VSB_SYSCTRL_RAM1_FIRRCA1GAIN9__A, sizeof(vsb_ffe_leak_gain_… in set_vsb_leak_n_gain()
5687 if (rc != 0) { in set_vsb_leak_n_gain()
5688 pr_err("error %d\n", rc); in set_vsb_leak_n_gain()
5694 return rc; in set_vsb_leak_n_gain()
5707 int rc; in set_vsb() local
5749 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in set_vsb()
5750 if (rc != 0) { in set_vsb()
5751 pr_err("error %d\n", rc); in set_vsb()
5754 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_STOP, 0); in set_vsb()
5755 if (rc != 0) { in set_vsb()
5756 pr_err("error %d\n", rc); in set_vsb()
5759 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in set_vsb()
5760 if (rc != 0) { in set_vsb()
5761 pr_err("error %d\n", rc); in set_vsb()
5764 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in set_vsb()
5765 if (rc != 0) { in set_vsb()
5766 pr_err("error %d\n", rc); in set_vsb()
5769 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in set_vsb()
5770 if (rc != 0) { in set_vsb()
5771 pr_err("error %d\n", rc); in set_vsb()
5774 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in set_vsb()
5775 if (rc != 0) { in set_vsb()
5776 pr_err("error %d\n", rc); in set_vsb()
5779 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in set_vsb()
5780 if (rc != 0) { in set_vsb()
5781 pr_err("error %d\n", rc); in set_vsb()
5792 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
5793 if (rc != 0) { in set_vsb()
5794 pr_err("error %d\n", rc); in set_vsb()
5798 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_DCF_BYPASS__A, 1, 0); in set_vsb()
5799 if (rc != 0) { in set_vsb()
5800 pr_err("error %d\n", rc); in set_vsb()
5803 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, IQM_FS_ADJ_SEL_B_VSB, 0); in set_vsb()
5804 if (rc != 0) { in set_vsb()
5805 pr_err("error %d\n", rc); in set_vsb()
5808 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, IQM_RC_ADJ_SEL_B_VSB, 0); in set_vsb()
5809 if (rc != 0) { in set_vsb()
5810 pr_err("error %d\n", rc); in set_vsb()
5814 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, ext_attr->iqm_rc_rate_ofs, 0); in set_vsb()
5815 if (rc != 0) { in set_vsb()
5816 pr_err("error %d\n", rc); in set_vsb()
5819 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CFAGC_GAINSHIFT__A, 4, 0); in set_vsb()
5820 if (rc != 0) { in set_vsb()
5821 pr_err("error %d\n", rc); in set_vsb()
5824 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 1, 0); in set_vsb()
5825 if (rc != 0) { in set_vsb()
5826 pr_err("error %d\n", rc); in set_vsb()
5830 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_CROUT_ENA__A, 1, 0); in set_vsb()
5831 if (rc != 0) { in set_vsb()
5832 pr_err("error %d\n", rc); in set_vsb()
5835 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, 28, 0); in set_vsb()
5836 if (rc != 0) { in set_vsb()
5837 pr_err("error %d\n", rc); in set_vsb()
5840 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_ACTIVE__A, 0, 0); in set_vsb()
5841 if (rc != 0) { in set_vsb()
5842 pr_err("error %d\n", rc); in set_vsb()
5845 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); in set_vsb()
5846 if (rc != 0) { in set_vsb()
5847 pr_err("error %d\n", rc); in set_vsb()
5850 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); in set_vsb()
5851 if (rc != 0) { in set_vsb()
5852 pr_err("error %d\n", rc); in set_vsb()
5855 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_VSB__M, 0); in set_vsb()
5856 if (rc != 0) { in set_vsb()
5857 pr_err("error %d\n", rc); in set_vsb()
5860 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE__A, 1393, 0); in set_vsb()
5861 if (rc != 0) { in set_vsb()
5862 pr_err("error %d\n", rc); in set_vsb()
5865 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); in set_vsb()
5866 if (rc != 0) { in set_vsb()
5867 pr_err("error %d\n", rc); in set_vsb()
5870 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); in set_vsb()
5871 if (rc != 0) { in set_vsb()
5872 pr_err("error %d\n", rc); in set_vsb()
5876 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)… in set_vsb()
5877 if (rc != 0) { in set_vsb()
5878 pr_err("error %d\n", rc); in set_vsb()
5881 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(vsb_taps_re), ((u8 *)vsb_taps_re)… in set_vsb()
5882 if (rc != 0) { in set_vsb()
5883 pr_err("error %d\n", rc); in set_vsb()
5887 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BNTHRESH__A, 330, 0); in set_vsb()
5888 if (rc != 0) { in set_vsb()
5889 pr_err("error %d\n", rc); in set_vsb()
5892 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CLPLASTNUM__A, 90, 0); in set_vsb()
5893 if (rc != 0) { in set_vsb()
5894 pr_err("error %d\n", rc); in set_vsb()
5897 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA1__A, 0x0042, 0); in set_vsb()
5898 if (rc != 0) { in set_vsb()
5899 pr_err("error %d\n", rc); in set_vsb()
5902 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_RCA2__A, 0x0053, 0); in set_vsb()
5903 if (rc != 0) { in set_vsb()
5904 pr_err("error %d\n", rc); in set_vsb()
5907 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_EQCTRL__A, 0x1, 0); in set_vsb()
5908 if (rc != 0) { in set_vsb()
5909 pr_err("error %d\n", rc); in set_vsb()
5912 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); in set_vsb()
5913 if (rc != 0) { in set_vsb()
5914 pr_err("error %d\n", rc); in set_vsb()
5919 rc = drxj_dap_write_reg16(dev_addr, FEC_TOP_ANNEX__A, FEC_TOP_ANNEX_D, 0); in set_vsb()
5920 if (rc != 0) { in set_vsb()
5921 pr_err("error %d\n", rc); in set_vsb()
5926 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_MODE__A, &fec_oc_snc_mode, 0); in set_vsb()
5927 if (rc != 0) { in set_vsb()
5928 pr_err("error %d\n", rc); in set_vsb()
5932 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_MODE__A, fec_oc_snc_mode | FEC_OC_SNC_MODE_UNLOCK_E… in set_vsb()
5933 if (rc != 0) { in set_vsb()
5934 pr_err("error %d\n", rc); in set_vsb()
5940 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); in set_vsb()
5941 if (rc != 0) { in set_vsb()
5942 pr_err("error %d\n", rc); in set_vsb()
5945 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 470, 0); in set_vsb()
5946 if (rc != 0) { in set_vsb()
5947 pr_err("error %d\n", rc); in set_vsb()
5950 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); in set_vsb()
5951 if (rc != 0) { in set_vsb()
5952 pr_err("error %d\n", rc); in set_vsb()
5955 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0xD4, 0); in set_vsb()
5956 if (rc != 0) { in set_vsb()
5957 pr_err("error %d\n", rc); in set_vsb()
5963 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_MODE__A, &fec_oc_reg_mode, 0); in set_vsb()
5964 if (rc != 0) { in set_vsb()
5965 pr_err("error %d\n", rc); in set_vsb()
5968 …rc = drxj_dap_write_reg16(dev_addr, FEC_OC_MODE__A, fec_oc_reg_mode & (~(FEC_OC_MODE_TRANSPARENT__… in set_vsb()
5969 if (rc != 0) { in set_vsb()
5970 pr_err("error %d\n", rc); in set_vsb()
5975 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_LO__A, 0, 0); in set_vsb()
5976 if (rc != 0) { in set_vsb()
5977 pr_err("error %d\n", rc); in set_vsb()
5980 rc = drxj_dap_write_reg16(dev_addr, FEC_DI_TIMEOUT_HI__A, 3, 0); in set_vsb()
5981 if (rc != 0) { in set_vsb()
5982 pr_err("error %d\n", rc); in set_vsb()
5985 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MODE__A, 0, 0); in set_vsb()
5986 if (rc != 0) { in set_vsb()
5987 pr_err("error %d\n", rc); in set_vsb()
5991 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, FEC_RS_MEASUREMENT_PERIOD, 0); in set_vsb()
5992 if (rc != 0) { in set_vsb()
5993 pr_err("error %d\n", rc); in set_vsb()
5996 …rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, FEC_RS_MEASUREMENT_PRESCALE, 0… in set_vsb()
5997 if (rc != 0) { in set_vsb()
5998 pr_err("error %d\n", rc); in set_vsb()
6003 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_MEASUREMENT_PERIOD__A, VSB_TOP_MEASUREMENT_PERIOD, 0); in set_vsb()
6004 if (rc != 0) { in set_vsb()
6005 pr_err("error %d\n", rc); in set_vsb()
6008 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); in set_vsb()
6009 if (rc != 0) { in set_vsb()
6010 pr_err("error %d\n", rc); in set_vsb()
6013 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); in set_vsb()
6014 if (rc != 0) { in set_vsb()
6015 pr_err("error %d\n", rc); in set_vsb()
6018 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); in set_vsb()
6019 if (rc != 0) { in set_vsb()
6020 pr_err("error %d\n", rc); in set_vsb()
6024 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CKGN1TRK__A, 128, 0); in set_vsb()
6025 if (rc != 0) { in set_vsb()
6026 pr_err("error %d\n", rc); in set_vsb()
6031 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); in set_vsb()
6032 if (rc != 0) { in set_vsb()
6033 pr_err("error %d\n", rc); in set_vsb()
6039 rc = set_iqm_af(demod, true); in set_vsb()
6040 if (rc != 0) { in set_vsb()
6041 pr_err("error %d\n", rc); in set_vsb()
6044 rc = adc_synchronization(demod); in set_vsb()
6045 if (rc != 0) { in set_vsb()
6046 pr_err("error %d\n", rc); in set_vsb()
6050 rc = init_agc(demod); in set_vsb()
6051 if (rc != 0) { in set_vsb()
6052 pr_err("error %d\n", rc); in set_vsb()
6055 rc = set_agc_if(demod, &(ext_attr->vsb_if_agc_cfg), false); in set_vsb()
6056 if (rc != 0) { in set_vsb()
6057 pr_err("error %d\n", rc); in set_vsb()
6060 rc = set_agc_rf(demod, &(ext_attr->vsb_rf_agc_cfg), false); in set_vsb()
6061 if (rc != 0) { in set_vsb()
6062 pr_err("error %d\n", rc); in set_vsb()
6071 rc = ctrl_set_cfg_afe_gain(demod, &vsb_pga_cfg); in set_vsb()
6072 if (rc != 0) { in set_vsb()
6073 pr_err("error %d\n", rc); in set_vsb()
6077 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->vsb_pre_saw_cfg)); in set_vsb()
6078 if (rc != 0) { in set_vsb()
6079 pr_err("error %d\n", rc); in set_vsb()
6084 rc = set_mpegtei_handling(demod); in set_vsb()
6085 if (rc != 0) { in set_vsb()
6086 pr_err("error %d\n", rc); in set_vsb()
6089 rc = bit_reverse_mpeg_output(demod); in set_vsb()
6090 if (rc != 0) { in set_vsb()
6091 pr_err("error %d\n", rc); in set_vsb()
6094 rc = set_mpeg_start_width(demod); in set_vsb()
6095 if (rc != 0) { in set_vsb()
6096 pr_err("error %d\n", rc); in set_vsb()
6107 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in set_vsb()
6108 if (rc != 0) { in set_vsb()
6109 pr_err("error %d\n", rc); in set_vsb()
6122 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
6123 if (rc != 0) { in set_vsb()
6124 pr_err("error %d\n", rc); in set_vsb()
6128 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEAGC_GAINSHIFT__A, 0x0004, 0); in set_vsb()
6129 if (rc != 0) { in set_vsb()
6130 pr_err("error %d\n", rc); in set_vsb()
6133 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SNRTH_PT__A, 0x00D2, 0); in set_vsb()
6134 if (rc != 0) { in set_vsb()
6135 pr_err("error %d\n", rc); in set_vsb()
6138 …rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_SYSSMTRNCTRL__A, VSB_TOP_SYSSMTRNCTRL__PRE | VSB_TOP_S… in set_vsb()
6139 if (rc != 0) { in set_vsb()
6140 pr_err("error %d\n", rc); in set_vsb()
6143 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_BEDETCTRL__A, 0x142, 0); in set_vsb()
6144 if (rc != 0) { in set_vsb()
6145 pr_err("error %d\n", rc); in set_vsb()
6148 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_LBAGCREFLVL__A, 640, 0); in set_vsb()
6149 if (rc != 0) { in set_vsb()
6150 pr_err("error %d\n", rc); in set_vsb()
6153 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1ACQ__A, 4, 0); in set_vsb()
6154 if (rc != 0) { in set_vsb()
6155 pr_err("error %d\n", rc); in set_vsb()
6158 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN1TRK__A, 2, 0); in set_vsb()
6159 if (rc != 0) { in set_vsb()
6160 pr_err("error %d\n", rc); in set_vsb()
6163 rc = drxj_dap_write_reg16(dev_addr, VSB_TOP_CYGN2TRK__A, 3, 0); in set_vsb()
6164 if (rc != 0) { in set_vsb()
6165 pr_err("error %d\n", rc); in set_vsb()
6176 rc = scu_command(dev_addr, &cmd_scu); in set_vsb()
6177 if (rc != 0) { in set_vsb()
6178 pr_err("error %d\n", rc); in set_vsb()
6182 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); in set_vsb()
6183 if (rc != 0) { in set_vsb()
6184 pr_err("error %d\n", rc); in set_vsb()
6187 rc = drxj_dap_write_reg16(dev_addr, VSB_COMM_EXEC__A, VSB_COMM_EXEC_ACTIVE, 0); in set_vsb()
6188 if (rc != 0) { in set_vsb()
6189 pr_err("error %d\n", rc); in set_vsb()
6192 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); in set_vsb()
6193 if (rc != 0) { in set_vsb()
6194 pr_err("error %d\n", rc); in set_vsb()
6200 return rc; in set_vsb()
6211 int rc; in get_vsb_post_rs_pck_err() local
6218 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &data, 0); in get_vsb_post_rs_pck_err()
6219 if (rc != 0) { in get_vsb_post_rs_pck_err()
6220 pr_err("error %d\n", rc); in get_vsb_post_rs_pck_err()
6239 return rc; in get_vsb_post_rs_pck_err()
6250 int rc; in get_vs_bpost_viterbi_ber() local
6257 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &data, 0); in get_vs_bpost_viterbi_ber()
6258 if (rc != 0) { in get_vs_bpost_viterbi_ber()
6259 pr_err("error %d\n", rc); in get_vs_bpost_viterbi_ber()
6284 return rc; in get_vs_bpost_viterbi_ber()
6296 int rc; in get_vs_bpre_viterbi_ber() local
6298 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_NR_SYM_ERRS__A, &data, 0); in get_vs_bpre_viterbi_ber()
6299 if (rc != 0) { in get_vs_bpre_viterbi_ber()
6300 pr_err("error %d\n", rc); in get_vs_bpre_viterbi_ber()
6316 int rc; in get_vsbmer() local
6319 rc = drxj_dap_read_reg16(dev_addr, VSB_TOP_ERR_ENERGY_H__A, &data_hi, 0); in get_vsbmer()
6320 if (rc != 0) { in get_vsbmer()
6321 pr_err("error %d\n", rc); in get_vsbmer()
6329 return rc; in get_vsbmer()
6358 int rc; in power_down_qam() local
6369 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in power_down_qam()
6370 if (rc != 0) { in power_down_qam()
6371 pr_err("error %d\n", rc); in power_down_qam()
6374 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); in power_down_qam()
6375 if (rc != 0) { in power_down_qam()
6376 pr_err("error %d\n", rc); in power_down_qam()
6386 rc = scu_command(dev_addr, &cmd_scu); in power_down_qam()
6387 if (rc != 0) { in power_down_qam()
6388 pr_err("error %d\n", rc); in power_down_qam()
6393 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_qam()
6394 if (rc != 0) { in power_down_qam()
6395 pr_err("error %d\n", rc); in power_down_qam()
6398 rc = set_iqm_af(demod, false); in power_down_qam()
6399 if (rc != 0) { in power_down_qam()
6400 pr_err("error %d\n", rc); in power_down_qam()
6404 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_qam()
6405 if (rc != 0) { in power_down_qam()
6406 pr_err("error %d\n", rc); in power_down_qam()
6409 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_qam()
6410 if (rc != 0) { in power_down_qam()
6411 pr_err("error %d\n", rc); in power_down_qam()
6414 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_qam()
6415 if (rc != 0) { in power_down_qam()
6416 pr_err("error %d\n", rc); in power_down_qam()
6419 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_qam()
6420 if (rc != 0) { in power_down_qam()
6421 pr_err("error %d\n", rc); in power_down_qam()
6424 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_qam()
6425 if (rc != 0) { in power_down_qam()
6426 pr_err("error %d\n", rc); in power_down_qam()
6434 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in power_down_qam()
6435 if (rc != 0) { in power_down_qam()
6436 pr_err("error %d\n", rc); in power_down_qam()
6442 return rc; in power_down_qam()
6470 int rc; in set_qam_measurement() local
6564 rc = drxj_dap_write_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, (u16)fec_oc_snc_fail_period, 0); in set_qam_measurement()
6565 if (rc != 0) { in set_qam_measurement()
6566 pr_err("error %d\n", rc); in set_qam_measurement()
6569 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PERIOD__A, (u16)fec_rs_period, 0); in set_qam_measurement()
6570 if (rc != 0) { in set_qam_measurement()
6571 pr_err("error %d\n", rc); in set_qam_measurement()
6574 rc = drxj_dap_write_reg16(dev_addr, FEC_RS_MEASUREMENT_PRESCALE__A, fec_rs_prescale, 0); in set_qam_measurement()
6575 if (rc != 0) { in set_qam_measurement()
6576 pr_err("error %d\n", rc); in set_qam_measurement()
6581 rc = drxdap_fasi_write_reg32(dev_addr, SCU_RAM_FEC_ACCUM_CW_CORRECTED_LO__A, 0, 0); in set_qam_measurement()
6582 if (rc != 0) { in set_qam_measurement()
6583 pr_err("error %d\n", rc); in set_qam_measurement()
6586 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_MEAS_COUNT__A, 0, 0); in set_qam_measurement()
6587 if (rc != 0) { in set_qam_measurement()
6588 pr_err("error %d\n", rc); in set_qam_measurement()
6591 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_FEC_ACCUM_PKT_FAILURES__A, 0, 0); in set_qam_measurement()
6592 if (rc != 0) { in set_qam_measurement()
6593 pr_err("error %d\n", rc); in set_qam_measurement()
6638 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PERIOD__A, (u16)qam_vd_period, 0); in set_qam_measurement()
6639 if (rc != 0) { in set_qam_measurement()
6640 pr_err("error %d\n", rc); in set_qam_measurement()
6643 rc = drxj_dap_write_reg16(dev_addr, QAM_VD_MEASUREMENT_PRESCALE__A, qam_vd_prescale, 0); in set_qam_measurement()
6644 if (rc != 0) { in set_qam_measurement()
6645 pr_err("error %d\n", rc); in set_qam_measurement()
6654 return rc; in set_qam_measurement()
6668 int rc; in set_qam16() local
6686 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam16()
6687 if (rc != 0) { in set_qam16()
6688 pr_err("error %d\n", rc); in set_qam16()
6691 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam16()
6692 if (rc != 0) { in set_qam16()
6693 pr_err("error %d\n", rc); in set_qam16()
6697 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 140, 0); in set_qam16()
6698 if (rc != 0) { in set_qam16()
6699 pr_err("error %d\n", rc); in set_qam16()
6702 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); in set_qam16()
6703 if (rc != 0) { in set_qam16()
6704 pr_err("error %d\n", rc); in set_qam16()
6707 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 120, 0); in set_qam16()
6708 if (rc != 0) { in set_qam16()
6709 pr_err("error %d\n", rc); in set_qam16()
6712 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 230, 0); in set_qam16()
6713 if (rc != 0) { in set_qam16()
6714 pr_err("error %d\n", rc); in set_qam16()
6717 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 95, 0); in set_qam16()
6718 if (rc != 0) { in set_qam16()
6719 pr_err("error %d\n", rc); in set_qam16()
6722 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 105, 0); in set_qam16()
6723 if (rc != 0) { in set_qam16()
6724 pr_err("error %d\n", rc); in set_qam16()
6728 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam16()
6729 if (rc != 0) { in set_qam16()
6730 pr_err("error %d\n", rc); in set_qam16()
6733 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); in set_qam16()
6734 if (rc != 0) { in set_qam16()
6735 pr_err("error %d\n", rc); in set_qam16()
6738 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam16()
6739 if (rc != 0) { in set_qam16()
6740 pr_err("error %d\n", rc); in set_qam16()
6744 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 16, 0); in set_qam16()
6745 if (rc != 0) { in set_qam16()
6746 pr_err("error %d\n", rc); in set_qam16()
6749 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 220, 0); in set_qam16()
6750 if (rc != 0) { in set_qam16()
6751 pr_err("error %d\n", rc); in set_qam16()
6754 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 25, 0); in set_qam16()
6755 if (rc != 0) { in set_qam16()
6756 pr_err("error %d\n", rc); in set_qam16()
6759 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 6, 0); in set_qam16()
6760 if (rc != 0) { in set_qam16()
6761 pr_err("error %d\n", rc); in set_qam16()
6764 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-24), 0); in set_qam16()
6765 if (rc != 0) { in set_qam16()
6766 pr_err("error %d\n", rc); in set_qam16()
6769 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-65), 0); in set_qam16()
6770 if (rc != 0) { in set_qam16()
6771 pr_err("error %d\n", rc); in set_qam16()
6774 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-127), 0); in set_qam16()
6775 if (rc != 0) { in set_qam16()
6776 pr_err("error %d\n", rc); in set_qam16()
6780 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam16()
6781 if (rc != 0) { in set_qam16()
6782 pr_err("error %d\n", rc); in set_qam16()
6785 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam16()
6786 if (rc != 0) { in set_qam16()
6787 pr_err("error %d\n", rc); in set_qam16()
6790 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam16()
6791 if (rc != 0) { in set_qam16()
6792 pr_err("error %d\n", rc); in set_qam16()
6795 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); in set_qam16()
6796 if (rc != 0) { in set_qam16()
6797 pr_err("error %d\n", rc); in set_qam16()
6800 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam16()
6801 if (rc != 0) { in set_qam16()
6802 pr_err("error %d\n", rc); in set_qam16()
6805 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam16()
6806 if (rc != 0) { in set_qam16()
6807 pr_err("error %d\n", rc); in set_qam16()
6810 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); in set_qam16()
6811 if (rc != 0) { in set_qam16()
6812 pr_err("error %d\n", rc); in set_qam16()
6815 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); in set_qam16()
6816 if (rc != 0) { in set_qam16()
6817 pr_err("error %d\n", rc); in set_qam16()
6820 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam16()
6821 if (rc != 0) { in set_qam16()
6822 pr_err("error %d\n", rc); in set_qam16()
6825 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam16()
6826 if (rc != 0) { in set_qam16()
6827 pr_err("error %d\n", rc); in set_qam16()
6830 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam16()
6831 if (rc != 0) { in set_qam16()
6832 pr_err("error %d\n", rc); in set_qam16()
6835 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam16()
6836 if (rc != 0) { in set_qam16()
6837 pr_err("error %d\n", rc); in set_qam16()
6840 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam16()
6841 if (rc != 0) { in set_qam16()
6842 pr_err("error %d\n", rc); in set_qam16()
6845 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam16()
6846 if (rc != 0) { in set_qam16()
6847 pr_err("error %d\n", rc); in set_qam16()
6850 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam16()
6851 if (rc != 0) { in set_qam16()
6852 pr_err("error %d\n", rc); in set_qam16()
6855 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam16()
6856 if (rc != 0) { in set_qam16()
6857 pr_err("error %d\n", rc); in set_qam16()
6860 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 240, 0); in set_qam16()
6861 if (rc != 0) { in set_qam16()
6862 pr_err("error %d\n", rc); in set_qam16()
6865 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam16()
6866 if (rc != 0) { in set_qam16()
6867 pr_err("error %d\n", rc); in set_qam16()
6870 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam16()
6871 if (rc != 0) { in set_qam16()
6872 pr_err("error %d\n", rc); in set_qam16()
6875 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); in set_qam16()
6876 if (rc != 0) { in set_qam16()
6877 pr_err("error %d\n", rc); in set_qam16()
6881 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 40960, 0); in set_qam16()
6882 if (rc != 0) { in set_qam16()
6883 pr_err("error %d\n", rc); in set_qam16()
6889 return rc; in set_qam16()
6903 int rc; in set_qam32() local
6921 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam32()
6922 if (rc != 0) { in set_qam32()
6923 pr_err("error %d\n", rc); in set_qam32()
6926 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam32()
6927 if (rc != 0) { in set_qam32()
6928 pr_err("error %d\n", rc); in set_qam32()
6932 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 90, 0); in set_qam32()
6933 if (rc != 0) { in set_qam32()
6934 pr_err("error %d\n", rc); in set_qam32()
6937 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 50, 0); in set_qam32()
6938 if (rc != 0) { in set_qam32()
6939 pr_err("error %d\n", rc); in set_qam32()
6942 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam32()
6943 if (rc != 0) { in set_qam32()
6944 pr_err("error %d\n", rc); in set_qam32()
6947 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 170, 0); in set_qam32()
6948 if (rc != 0) { in set_qam32()
6949 pr_err("error %d\n", rc); in set_qam32()
6952 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam32()
6953 if (rc != 0) { in set_qam32()
6954 pr_err("error %d\n", rc); in set_qam32()
6957 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); in set_qam32()
6958 if (rc != 0) { in set_qam32()
6959 pr_err("error %d\n", rc); in set_qam32()
6963 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam32()
6964 if (rc != 0) { in set_qam32()
6965 pr_err("error %d\n", rc); in set_qam32()
6968 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 56, 0); in set_qam32()
6969 if (rc != 0) { in set_qam32()
6970 pr_err("error %d\n", rc); in set_qam32()
6973 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam32()
6974 if (rc != 0) { in set_qam32()
6975 pr_err("error %d\n", rc); in set_qam32()
6979 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); in set_qam32()
6980 if (rc != 0) { in set_qam32()
6981 pr_err("error %d\n", rc); in set_qam32()
6984 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 140, 0); in set_qam32()
6985 if (rc != 0) { in set_qam32()
6986 pr_err("error %d\n", rc); in set_qam32()
6989 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, (u16)(-8), 0); in set_qam32()
6990 if (rc != 0) { in set_qam32()
6991 pr_err("error %d\n", rc); in set_qam32()
6994 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, (u16)(-16), 0); in set_qam32()
6995 if (rc != 0) { in set_qam32()
6996 pr_err("error %d\n", rc); in set_qam32()
6999 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-26), 0); in set_qam32()
7000 if (rc != 0) { in set_qam32()
7001 pr_err("error %d\n", rc); in set_qam32()
7004 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-56), 0); in set_qam32()
7005 if (rc != 0) { in set_qam32()
7006 pr_err("error %d\n", rc); in set_qam32()
7009 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-86), 0); in set_qam32()
7010 if (rc != 0) { in set_qam32()
7011 pr_err("error %d\n", rc); in set_qam32()
7015 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam32()
7016 if (rc != 0) { in set_qam32()
7017 pr_err("error %d\n", rc); in set_qam32()
7020 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam32()
7021 if (rc != 0) { in set_qam32()
7022 pr_err("error %d\n", rc); in set_qam32()
7025 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam32()
7026 if (rc != 0) { in set_qam32()
7027 pr_err("error %d\n", rc); in set_qam32()
7030 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 20, 0); in set_qam32()
7031 if (rc != 0) { in set_qam32()
7032 pr_err("error %d\n", rc); in set_qam32()
7035 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam32()
7036 if (rc != 0) { in set_qam32()
7037 pr_err("error %d\n", rc); in set_qam32()
7040 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam32()
7041 if (rc != 0) { in set_qam32()
7042 pr_err("error %d\n", rc); in set_qam32()
7045 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 10, 0); in set_qam32()
7046 if (rc != 0) { in set_qam32()
7047 pr_err("error %d\n", rc); in set_qam32()
7050 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 50, 0); in set_qam32()
7051 if (rc != 0) { in set_qam32()
7052 pr_err("error %d\n", rc); in set_qam32()
7055 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam32()
7056 if (rc != 0) { in set_qam32()
7057 pr_err("error %d\n", rc); in set_qam32()
7060 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam32()
7061 if (rc != 0) { in set_qam32()
7062 pr_err("error %d\n", rc); in set_qam32()
7065 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam32()
7066 if (rc != 0) { in set_qam32()
7067 pr_err("error %d\n", rc); in set_qam32()
7070 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam32()
7071 if (rc != 0) { in set_qam32()
7072 pr_err("error %d\n", rc); in set_qam32()
7075 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam32()
7076 if (rc != 0) { in set_qam32()
7077 pr_err("error %d\n", rc); in set_qam32()
7080 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam32()
7081 if (rc != 0) { in set_qam32()
7082 pr_err("error %d\n", rc); in set_qam32()
7085 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam32()
7086 if (rc != 0) { in set_qam32()
7087 pr_err("error %d\n", rc); in set_qam32()
7090 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam32()
7091 if (rc != 0) { in set_qam32()
7092 pr_err("error %d\n", rc); in set_qam32()
7095 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 176, 0); in set_qam32()
7096 if (rc != 0) { in set_qam32()
7097 pr_err("error %d\n", rc); in set_qam32()
7100 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam32()
7101 if (rc != 0) { in set_qam32()
7102 pr_err("error %d\n", rc); in set_qam32()
7105 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam32()
7106 if (rc != 0) { in set_qam32()
7107 pr_err("error %d\n", rc); in set_qam32()
7110 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 8, 0); in set_qam32()
7111 if (rc != 0) { in set_qam32()
7112 pr_err("error %d\n", rc); in set_qam32()
7116 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20480, 0); in set_qam32()
7117 if (rc != 0) { in set_qam32()
7118 pr_err("error %d\n", rc); in set_qam32()
7124 return rc; in set_qam32()
7138 int rc; in set_qam64() local
7157 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam64()
7158 if (rc != 0) { in set_qam64()
7159 pr_err("error %d\n", rc); in set_qam64()
7162 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam64()
7163 if (rc != 0) { in set_qam64()
7164 pr_err("error %d\n", rc); in set_qam64()
7168 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 105, 0); in set_qam64()
7169 if (rc != 0) { in set_qam64()
7170 pr_err("error %d\n", rc); in set_qam64()
7173 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam64()
7174 if (rc != 0) { in set_qam64()
7175 pr_err("error %d\n", rc); in set_qam64()
7178 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam64()
7179 if (rc != 0) { in set_qam64()
7180 pr_err("error %d\n", rc); in set_qam64()
7183 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 195, 0); in set_qam64()
7184 if (rc != 0) { in set_qam64()
7185 pr_err("error %d\n", rc); in set_qam64()
7188 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam64()
7189 if (rc != 0) { in set_qam64()
7190 pr_err("error %d\n", rc); in set_qam64()
7193 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 84, 0); in set_qam64()
7194 if (rc != 0) { in set_qam64()
7195 pr_err("error %d\n", rc); in set_qam64()
7199 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam64()
7200 if (rc != 0) { in set_qam64()
7201 pr_err("error %d\n", rc); in set_qam64()
7204 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); in set_qam64()
7205 if (rc != 0) { in set_qam64()
7206 pr_err("error %d\n", rc); in set_qam64()
7209 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam64()
7210 if (rc != 0) { in set_qam64()
7211 pr_err("error %d\n", rc); in set_qam64()
7215 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 12, 0); in set_qam64()
7216 if (rc != 0) { in set_qam64()
7217 pr_err("error %d\n", rc); in set_qam64()
7220 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 141, 0); in set_qam64()
7221 if (rc != 0) { in set_qam64()
7222 pr_err("error %d\n", rc); in set_qam64()
7225 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 7, 0); in set_qam64()
7226 if (rc != 0) { in set_qam64()
7227 pr_err("error %d\n", rc); in set_qam64()
7230 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 0, 0); in set_qam64()
7231 if (rc != 0) { in set_qam64()
7232 pr_err("error %d\n", rc); in set_qam64()
7235 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-15), 0); in set_qam64()
7236 if (rc != 0) { in set_qam64()
7237 pr_err("error %d\n", rc); in set_qam64()
7240 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, (u16)(-45), 0); in set_qam64()
7241 if (rc != 0) { in set_qam64()
7242 pr_err("error %d\n", rc); in set_qam64()
7245 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-80), 0); in set_qam64()
7246 if (rc != 0) { in set_qam64()
7247 pr_err("error %d\n", rc); in set_qam64()
7251 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam64()
7252 if (rc != 0) { in set_qam64()
7253 pr_err("error %d\n", rc); in set_qam64()
7256 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam64()
7257 if (rc != 0) { in set_qam64()
7258 pr_err("error %d\n", rc); in set_qam64()
7261 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam64()
7262 if (rc != 0) { in set_qam64()
7263 pr_err("error %d\n", rc); in set_qam64()
7266 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 30, 0); in set_qam64()
7267 if (rc != 0) { in set_qam64()
7268 pr_err("error %d\n", rc); in set_qam64()
7271 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam64()
7272 if (rc != 0) { in set_qam64()
7273 pr_err("error %d\n", rc); in set_qam64()
7276 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam64()
7277 if (rc != 0) { in set_qam64()
7278 pr_err("error %d\n", rc); in set_qam64()
7281 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 15, 0); in set_qam64()
7282 if (rc != 0) { in set_qam64()
7283 pr_err("error %d\n", rc); in set_qam64()
7286 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam64()
7287 if (rc != 0) { in set_qam64()
7288 pr_err("error %d\n", rc); in set_qam64()
7291 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam64()
7292 if (rc != 0) { in set_qam64()
7293 pr_err("error %d\n", rc); in set_qam64()
7296 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam64()
7297 if (rc != 0) { in set_qam64()
7298 pr_err("error %d\n", rc); in set_qam64()
7301 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam64()
7302 if (rc != 0) { in set_qam64()
7303 pr_err("error %d\n", rc); in set_qam64()
7306 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam64()
7307 if (rc != 0) { in set_qam64()
7308 pr_err("error %d\n", rc); in set_qam64()
7311 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam64()
7312 if (rc != 0) { in set_qam64()
7313 pr_err("error %d\n", rc); in set_qam64()
7316 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam64()
7317 if (rc != 0) { in set_qam64()
7318 pr_err("error %d\n", rc); in set_qam64()
7321 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam64()
7322 if (rc != 0) { in set_qam64()
7323 pr_err("error %d\n", rc); in set_qam64()
7326 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); in set_qam64()
7327 if (rc != 0) { in set_qam64()
7328 pr_err("error %d\n", rc); in set_qam64()
7331 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 160, 0); in set_qam64()
7332 if (rc != 0) { in set_qam64()
7333 pr_err("error %d\n", rc); in set_qam64()
7336 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam64()
7337 if (rc != 0) { in set_qam64()
7338 pr_err("error %d\n", rc); in set_qam64()
7341 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam64()
7342 if (rc != 0) { in set_qam64()
7343 pr_err("error %d\n", rc); in set_qam64()
7346 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 32, 0); in set_qam64()
7347 if (rc != 0) { in set_qam64()
7348 pr_err("error %d\n", rc); in set_qam64()
7352 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43008, 0); in set_qam64()
7353 if (rc != 0) { in set_qam64()
7354 pr_err("error %d\n", rc); in set_qam64()
7360 return rc; in set_qam64()
7374 int rc; in set_qam128() local
7392 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam128()
7393 if (rc != 0) { in set_qam128()
7394 pr_err("error %d\n", rc); in set_qam128()
7397 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam128()
7398 if (rc != 0) { in set_qam128()
7399 pr_err("error %d\n", rc); in set_qam128()
7403 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); in set_qam128()
7404 if (rc != 0) { in set_qam128()
7405 pr_err("error %d\n", rc); in set_qam128()
7408 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam128()
7409 if (rc != 0) { in set_qam128()
7410 pr_err("error %d\n", rc); in set_qam128()
7413 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam128()
7414 if (rc != 0) { in set_qam128()
7415 pr_err("error %d\n", rc); in set_qam128()
7418 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 140, 0); in set_qam128()
7419 if (rc != 0) { in set_qam128()
7420 pr_err("error %d\n", rc); in set_qam128()
7423 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam128()
7424 if (rc != 0) { in set_qam128()
7425 pr_err("error %d\n", rc); in set_qam128()
7428 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 100, 0); in set_qam128()
7429 if (rc != 0) { in set_qam128()
7430 pr_err("error %d\n", rc); in set_qam128()
7434 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam128()
7435 if (rc != 0) { in set_qam128()
7436 pr_err("error %d\n", rc); in set_qam128()
7439 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 32, 0); in set_qam128()
7440 if (rc != 0) { in set_qam128()
7441 pr_err("error %d\n", rc); in set_qam128()
7444 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam128()
7445 if (rc != 0) { in set_qam128()
7446 pr_err("error %d\n", rc); in set_qam128()
7450 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); in set_qam128()
7451 if (rc != 0) { in set_qam128()
7452 pr_err("error %d\n", rc); in set_qam128()
7455 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 65, 0); in set_qam128()
7456 if (rc != 0) { in set_qam128()
7457 pr_err("error %d\n", rc); in set_qam128()
7460 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 5, 0); in set_qam128()
7461 if (rc != 0) { in set_qam128()
7462 pr_err("error %d\n", rc); in set_qam128()
7465 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 3, 0); in set_qam128()
7466 if (rc != 0) { in set_qam128()
7467 pr_err("error %d\n", rc); in set_qam128()
7470 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, (u16)(-1), 0); in set_qam128()
7471 if (rc != 0) { in set_qam128()
7472 pr_err("error %d\n", rc); in set_qam128()
7475 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 12, 0); in set_qam128()
7476 if (rc != 0) { in set_qam128()
7477 pr_err("error %d\n", rc); in set_qam128()
7480 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-23), 0); in set_qam128()
7481 if (rc != 0) { in set_qam128()
7482 pr_err("error %d\n", rc); in set_qam128()
7486 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam128()
7487 if (rc != 0) { in set_qam128()
7488 pr_err("error %d\n", rc); in set_qam128()
7491 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam128()
7492 if (rc != 0) { in set_qam128()
7493 pr_err("error %d\n", rc); in set_qam128()
7496 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam128()
7497 if (rc != 0) { in set_qam128()
7498 pr_err("error %d\n", rc); in set_qam128()
7501 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 40, 0); in set_qam128()
7502 if (rc != 0) { in set_qam128()
7503 pr_err("error %d\n", rc); in set_qam128()
7506 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam128()
7507 if (rc != 0) { in set_qam128()
7508 pr_err("error %d\n", rc); in set_qam128()
7511 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam128()
7512 if (rc != 0) { in set_qam128()
7513 pr_err("error %d\n", rc); in set_qam128()
7516 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 20, 0); in set_qam128()
7517 if (rc != 0) { in set_qam128()
7518 pr_err("error %d\n", rc); in set_qam128()
7521 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam128()
7522 if (rc != 0) { in set_qam128()
7523 pr_err("error %d\n", rc); in set_qam128()
7526 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam128()
7527 if (rc != 0) { in set_qam128()
7528 pr_err("error %d\n", rc); in set_qam128()
7531 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam128()
7532 if (rc != 0) { in set_qam128()
7533 pr_err("error %d\n", rc); in set_qam128()
7536 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam128()
7537 if (rc != 0) { in set_qam128()
7538 pr_err("error %d\n", rc); in set_qam128()
7541 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam128()
7542 if (rc != 0) { in set_qam128()
7543 pr_err("error %d\n", rc); in set_qam128()
7546 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam128()
7547 if (rc != 0) { in set_qam128()
7548 pr_err("error %d\n", rc); in set_qam128()
7551 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam128()
7552 if (rc != 0) { in set_qam128()
7553 pr_err("error %d\n", rc); in set_qam128()
7556 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam128()
7557 if (rc != 0) { in set_qam128()
7558 pr_err("error %d\n", rc); in set_qam128()
7561 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 32, 0); in set_qam128()
7562 if (rc != 0) { in set_qam128()
7563 pr_err("error %d\n", rc); in set_qam128()
7566 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 144, 0); in set_qam128()
7567 if (rc != 0) { in set_qam128()
7568 pr_err("error %d\n", rc); in set_qam128()
7571 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam128()
7572 if (rc != 0) { in set_qam128()
7573 pr_err("error %d\n", rc); in set_qam128()
7576 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam128()
7577 if (rc != 0) { in set_qam128()
7578 pr_err("error %d\n", rc); in set_qam128()
7581 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); in set_qam128()
7582 if (rc != 0) { in set_qam128()
7583 pr_err("error %d\n", rc); in set_qam128()
7587 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 20992, 0); in set_qam128()
7588 if (rc != 0) { in set_qam128()
7589 pr_err("error %d\n", rc); in set_qam128()
7595 return rc; in set_qam128()
7609 int rc; in set_qam256() local
7627 …rc = drxdap_fasi_write_block(dev_addr, QAM_DQ_QUAL_FUN0__A, sizeof(qam_dq_qual_fun), ((u8 *)qam_dq… in set_qam256()
7628 if (rc != 0) { in set_qam256()
7629 pr_err("error %d\n", rc); in set_qam256()
7632 …rc = drxdap_fasi_write_block(dev_addr, SCU_RAM_QAM_EQ_CMA_RAD0__A, sizeof(qam_eq_cma_rad), ((u8 *)… in set_qam256()
7633 if (rc != 0) { in set_qam256()
7634 pr_err("error %d\n", rc); in set_qam256()
7638 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RTH__A, 50, 0); in set_qam256()
7639 if (rc != 0) { in set_qam256()
7640 pr_err("error %d\n", rc); in set_qam256()
7643 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FTH__A, 60, 0); in set_qam256()
7644 if (rc != 0) { in set_qam256()
7645 pr_err("error %d\n", rc); in set_qam256()
7648 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_PTH__A, 100, 0); in set_qam256()
7649 if (rc != 0) { in set_qam256()
7650 pr_err("error %d\n", rc); in set_qam256()
7653 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_QTH__A, 150, 0); in set_qam256()
7654 if (rc != 0) { in set_qam256()
7655 pr_err("error %d\n", rc); in set_qam256()
7658 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_CTH__A, 80, 0); in set_qam256()
7659 if (rc != 0) { in set_qam256()
7660 pr_err("error %d\n", rc); in set_qam256()
7663 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MTH__A, 110, 0); in set_qam256()
7664 if (rc != 0) { in set_qam256()
7665 pr_err("error %d\n", rc); in set_qam256()
7669 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RATE_LIM__A, 40, 0); in set_qam256()
7670 if (rc != 0) { in set_qam256()
7671 pr_err("error %d\n", rc); in set_qam256()
7674 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_FREQ_LIM__A, 16, 0); in set_qam256()
7675 if (rc != 0) { in set_qam256()
7676 pr_err("error %d\n", rc); in set_qam256()
7679 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_COUNT_LIM__A, 3, 0); in set_qam256()
7680 if (rc != 0) { in set_qam256()
7681 pr_err("error %d\n", rc); in set_qam256()
7685 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_MEDIAN_AV_MULT__A, 8, 0); in set_qam256()
7686 if (rc != 0) { in set_qam256()
7687 pr_err("error %d\n", rc); in set_qam256()
7690 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_RADIUS_AV_LIMIT__A, 74, 0); in set_qam256()
7691 if (rc != 0) { in set_qam256()
7692 pr_err("error %d\n", rc); in set_qam256()
7695 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET1__A, 18, 0); in set_qam256()
7696 if (rc != 0) { in set_qam256()
7697 pr_err("error %d\n", rc); in set_qam256()
7700 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET2__A, 13, 0); in set_qam256()
7701 if (rc != 0) { in set_qam256()
7702 pr_err("error %d\n", rc); in set_qam256()
7705 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET3__A, 7, 0); in set_qam256()
7706 if (rc != 0) { in set_qam256()
7707 pr_err("error %d\n", rc); in set_qam256()
7710 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET4__A, 0, 0); in set_qam256()
7711 if (rc != 0) { in set_qam256()
7712 pr_err("error %d\n", rc); in set_qam256()
7715 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_LCAVG_OFFSET5__A, (u16)(-8), 0); in set_qam256()
7716 if (rc != 0) { in set_qam256()
7717 pr_err("error %d\n", rc); in set_qam256()
7721 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_FINE__A, 15, 0); in set_qam256()
7722 if (rc != 0) { in set_qam256()
7723 pr_err("error %d\n", rc); in set_qam256()
7726 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CA_COARSE__A, 40, 0); in set_qam256()
7727 if (rc != 0) { in set_qam256()
7728 pr_err("error %d\n", rc); in set_qam256()
7731 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_FINE__A, 2, 0); in set_qam256()
7732 if (rc != 0) { in set_qam256()
7733 pr_err("error %d\n", rc); in set_qam256()
7736 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_MEDIUM__A, 50, 0); in set_qam256()
7737 if (rc != 0) { in set_qam256()
7738 pr_err("error %d\n", rc); in set_qam256()
7741 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CP_COARSE__A, 255, 0); in set_qam256()
7742 if (rc != 0) { in set_qam256()
7743 pr_err("error %d\n", rc); in set_qam256()
7746 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_FINE__A, 2, 0); in set_qam256()
7747 if (rc != 0) { in set_qam256()
7748 pr_err("error %d\n", rc); in set_qam256()
7751 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_MEDIUM__A, 25, 0); in set_qam256()
7752 if (rc != 0) { in set_qam256()
7753 pr_err("error %d\n", rc); in set_qam256()
7756 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CI_COARSE__A, 80, 0); in set_qam256()
7757 if (rc != 0) { in set_qam256()
7758 pr_err("error %d\n", rc); in set_qam256()
7761 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_FINE__A, 12, 0); in set_qam256()
7762 if (rc != 0) { in set_qam256()
7763 pr_err("error %d\n", rc); in set_qam256()
7766 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_MEDIUM__A, 24, 0); in set_qam256()
7767 if (rc != 0) { in set_qam256()
7768 pr_err("error %d\n", rc); in set_qam256()
7771 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EP_COARSE__A, 24, 0); in set_qam256()
7772 if (rc != 0) { in set_qam256()
7773 pr_err("error %d\n", rc); in set_qam256()
7776 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_FINE__A, 12, 0); in set_qam256()
7777 if (rc != 0) { in set_qam256()
7778 pr_err("error %d\n", rc); in set_qam256()
7781 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_MEDIUM__A, 16, 0); in set_qam256()
7782 if (rc != 0) { in set_qam256()
7783 pr_err("error %d\n", rc); in set_qam256()
7786 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_EI_COARSE__A, 16, 0); in set_qam256()
7787 if (rc != 0) { in set_qam256()
7788 pr_err("error %d\n", rc); in set_qam256()
7791 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_FINE__A, 16, 0); in set_qam256()
7792 if (rc != 0) { in set_qam256()
7793 pr_err("error %d\n", rc); in set_qam256()
7796 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_MEDIUM__A, 48, 0); in set_qam256()
7797 if (rc != 0) { in set_qam256()
7798 pr_err("error %d\n", rc); in set_qam256()
7801 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF_COARSE__A, 80, 0); in set_qam256()
7802 if (rc != 0) { in set_qam256()
7803 pr_err("error %d\n", rc); in set_qam256()
7806 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_FINE__A, 5, 0); in set_qam256()
7807 if (rc != 0) { in set_qam256()
7808 pr_err("error %d\n", rc); in set_qam256()
7811 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_MEDIUM__A, 15, 0); in set_qam256()
7812 if (rc != 0) { in set_qam256()
7813 pr_err("error %d\n", rc); in set_qam256()
7816 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_LC_CF1_COARSE__A, 16, 0); in set_qam256()
7817 if (rc != 0) { in set_qam256()
7818 pr_err("error %d\n", rc); in set_qam256()
7822 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_SL_SIG_POWER__A, 43520, 0); in set_qam256()
7823 if (rc != 0) { in set_qam256()
7824 pr_err("error %d\n", rc); in set_qam256()
7830 return rc; in set_qam256()
7852 int rc; in set_qam() local
8056 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_STOP, 0); in set_qam()
8057 if (rc != 0) { in set_qam()
8058 pr_err("error %d\n", rc); in set_qam()
8061 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_STOP, 0); in set_qam()
8062 if (rc != 0) { in set_qam()
8063 pr_err("error %d\n", rc); in set_qam()
8066 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in set_qam()
8067 if (rc != 0) { in set_qam()
8068 pr_err("error %d\n", rc); in set_qam()
8071 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in set_qam()
8072 if (rc != 0) { in set_qam()
8073 pr_err("error %d\n", rc); in set_qam()
8076 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in set_qam()
8077 if (rc != 0) { in set_qam()
8078 pr_err("error %d\n", rc); in set_qam()
8081 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in set_qam()
8082 if (rc != 0) { in set_qam()
8083 pr_err("error %d\n", rc); in set_qam()
8086 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in set_qam()
8087 if (rc != 0) { in set_qam()
8088 pr_err("error %d\n", rc); in set_qam()
8098 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8099 if (rc != 0) { in set_qam()
8100 pr_err("error %d\n", rc); in set_qam()
8117 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8118 if (rc != 0) { in set_qam()
8119 pr_err("error %d\n", rc); in set_qam()
8129 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8130 if (rc != 0) { in set_qam()
8131 pr_err("error %d\n", rc); in set_qam()
8135 rc = drxdap_fasi_write_reg32(dev_addr, IQM_RC_RATE_OFS_LO__A, iqm_rc_rate, 0); in set_qam()
8136 if (rc != 0) { in set_qam()
8137 pr_err("error %d\n", rc); in set_qam()
8141 rc = set_qam_measurement(demod, channel->constellation, channel->symbolrate); in set_qam()
8142 if (rc != 0) { in set_qam()
8143 pr_err("error %d\n", rc); in set_qam()
8152 rc = set_frequency(demod, channel, tuner_freq_offset); in set_qam()
8153 if (rc != 0) { in set_qam()
8154 pr_err("error %d\n", rc); in set_qam()
8161 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_SYMBOL_FREQ__A, lc_symbol_freq, 0); in set_qam()
8162 if (rc != 0) { in set_qam()
8163 pr_err("error %d\n", rc); in set_qam()
8166 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_STRETCH__A, iqm_rc_stretch, 0); in set_qam()
8167 if (rc != 0) { in set_qam()
8168 pr_err("error %d\n", rc); in set_qam()
8175 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_AMUX__A, 0x02, 0); in set_qam()
8176 if (rc != 0) { in set_qam()
8177 pr_err("error %d\n", rc); in set_qam()
8181 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SYMMETRIC__A, 0, 0); in set_qam()
8182 if (rc != 0) { in set_qam()
8183 pr_err("error %d\n", rc); in set_qam()
8186 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_MIDTAP__A, 3, 0); in set_qam()
8187 if (rc != 0) { in set_qam()
8188 pr_err("error %d\n", rc); in set_qam()
8191 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_OUT_ENA__A, IQM_CF_OUT_ENA_QAM__M, 0); in set_qam()
8192 if (rc != 0) { in set_qam()
8193 pr_err("error %d\n", rc); in set_qam()
8197 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_WR_RSV_0__A, 0x5f, 0); in set_qam()
8198 if (rc != 0) { in set_qam()
8199 pr_err("error %d\n", rc); in set_qam()
8203 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SYNC_SEL__A, 3, 0); in set_qam()
8204 if (rc != 0) { in set_qam()
8205 pr_err("error %d\n", rc); in set_qam()
8208 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_LEN__A, 0, 0); in set_qam()
8209 if (rc != 0) { in set_qam()
8210 pr_err("error %d\n", rc); in set_qam()
8213 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_CLP_TH__A, 448, 0); in set_qam()
8214 if (rc != 0) { in set_qam()
8215 pr_err("error %d\n", rc); in set_qam()
8218 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_SNS_LEN__A, 0, 0); in set_qam()
8219 if (rc != 0) { in set_qam()
8220 pr_err("error %d\n", rc); in set_qam()
8223 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, 4, 0); in set_qam()
8224 if (rc != 0) { in set_qam()
8225 pr_err("error %d\n", rc); in set_qam()
8228 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_STDBY__A, 0x10, 0); in set_qam()
8229 if (rc != 0) { in set_qam()
8230 pr_err("error %d\n", rc); in set_qam()
8233 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, 11, 0); in set_qam()
8234 if (rc != 0) { in set_qam()
8235 pr_err("error %d\n", rc); in set_qam()
8239 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 1, 0); in set_qam()
8240 if (rc != 0) { in set_qam()
8241 pr_err("error %d\n", rc); in set_qam()
8244 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, IQM_CF_SCALE_SH__PRE, 0); in set_qam()
8245 if (rc != 0) { in set_qam()
8246 pr_err("error %d\n", rc); in set_qam()
8250 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_TIMEOUT__A, QAM_SY_TIMEOUT__PRE, 0); in set_qam()
8251 if (rc != 0) { in set_qam()
8252 pr_err("error %d\n", rc); in set_qam()
8256 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, QAM_SY_SYNC_LWM__PRE, 0); in set_qam()
8257 if (rc != 0) { in set_qam()
8258 pr_err("error %d\n", rc); in set_qam()
8261 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, QAM_SY_SYNC_AWM__PRE, 0); in set_qam()
8262 if (rc != 0) { in set_qam()
8263 pr_err("error %d\n", rc); in set_qam()
8266 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); in set_qam()
8267 if (rc != 0) { in set_qam()
8268 pr_err("error %d\n", rc); in set_qam()
8276 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); in set_qam()
8277 if (rc != 0) { in set_qam()
8278 pr_err("error %d\n", rc); in set_qam()
8281 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x04, 0); in set_qam()
8282 if (rc != 0) { in set_qam()
8283 pr_err("error %d\n", rc); in set_qam()
8286 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, QAM_SY_SYNC_HWM__PRE, 0); in set_qam()
8287 if (rc != 0) { in set_qam()
8288 pr_err("error %d\n", rc); in set_qam()
8294 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_LWM__A, 0x03, 0); in set_qam()
8295 if (rc != 0) { in set_qam()
8296 pr_err("error %d\n", rc); in set_qam()
8299 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_AWM__A, 0x05, 0); in set_qam()
8300 if (rc != 0) { in set_qam()
8301 pr_err("error %d\n", rc); in set_qam()
8304 rc = drxj_dap_write_reg16(dev_addr, QAM_SY_SYNC_HWM__A, 0x06, 0); in set_qam()
8305 if (rc != 0) { in set_qam()
8306 pr_err("error %d\n", rc); in set_qam()
8315 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, QAM_LC_MODE__PRE, 0); in set_qam()
8316 if (rc != 0) { in set_qam()
8317 pr_err("error %d\n", rc); in set_qam()
8320 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_RATE_LIMIT__A, 3, 0); in set_qam()
8321 if (rc != 0) { in set_qam()
8322 pr_err("error %d\n", rc); in set_qam()
8325 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORP__A, 4, 0); in set_qam()
8326 if (rc != 0) { in set_qam()
8327 pr_err("error %d\n", rc); in set_qam()
8330 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_LPF_FACTORI__A, 4, 0); in set_qam()
8331 if (rc != 0) { in set_qam()
8332 pr_err("error %d\n", rc); in set_qam()
8335 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_MODE__A, 7, 0); in set_qam()
8336 if (rc != 0) { in set_qam()
8337 pr_err("error %d\n", rc); in set_qam()
8340 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB0__A, 1, 0); in set_qam()
8341 if (rc != 0) { in set_qam()
8342 pr_err("error %d\n", rc); in set_qam()
8345 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB1__A, 1, 0); in set_qam()
8346 if (rc != 0) { in set_qam()
8347 pr_err("error %d\n", rc); in set_qam()
8350 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB2__A, 1, 0); in set_qam()
8351 if (rc != 0) { in set_qam()
8352 pr_err("error %d\n", rc); in set_qam()
8355 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB3__A, 1, 0); in set_qam()
8356 if (rc != 0) { in set_qam()
8357 pr_err("error %d\n", rc); in set_qam()
8360 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB4__A, 2, 0); in set_qam()
8361 if (rc != 0) { in set_qam()
8362 pr_err("error %d\n", rc); in set_qam()
8365 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB5__A, 2, 0); in set_qam()
8366 if (rc != 0) { in set_qam()
8367 pr_err("error %d\n", rc); in set_qam()
8370 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB6__A, 2, 0); in set_qam()
8371 if (rc != 0) { in set_qam()
8372 pr_err("error %d\n", rc); in set_qam()
8375 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB8__A, 2, 0); in set_qam()
8376 if (rc != 0) { in set_qam()
8377 pr_err("error %d\n", rc); in set_qam()
8380 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB9__A, 2, 0); in set_qam()
8381 if (rc != 0) { in set_qam()
8382 pr_err("error %d\n", rc); in set_qam()
8385 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB10__A, 2, 0); in set_qam()
8386 if (rc != 0) { in set_qam()
8387 pr_err("error %d\n", rc); in set_qam()
8390 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB12__A, 2, 0); in set_qam()
8391 if (rc != 0) { in set_qam()
8392 pr_err("error %d\n", rc); in set_qam()
8395 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB15__A, 3, 0); in set_qam()
8396 if (rc != 0) { in set_qam()
8397 pr_err("error %d\n", rc); in set_qam()
8400 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB16__A, 3, 0); in set_qam()
8401 if (rc != 0) { in set_qam()
8402 pr_err("error %d\n", rc); in set_qam()
8405 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB20__A, 4, 0); in set_qam()
8406 if (rc != 0) { in set_qam()
8407 pr_err("error %d\n", rc); in set_qam()
8410 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_QUAL_TAB25__A, 4, 0); in set_qam()
8411 if (rc != 0) { in set_qam()
8412 pr_err("error %d\n", rc); in set_qam()
8416 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_ADJ_SEL__A, 1, 0); in set_qam()
8417 if (rc != 0) { in set_qam()
8418 pr_err("error %d\n", rc); in set_qam()
8421 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_ADJ_SEL__A, 1, 0); in set_qam()
8422 if (rc != 0) { in set_qam()
8423 pr_err("error %d\n", rc); in set_qam()
8426 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_ADJ_SEL__A, 1, 0); in set_qam()
8427 if (rc != 0) { in set_qam()
8428 pr_err("error %d\n", rc); in set_qam()
8431 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_POW_MEAS_LEN__A, 0, 0); in set_qam()
8432 if (rc != 0) { in set_qam()
8433 pr_err("error %d\n", rc); in set_qam()
8436 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_GPIO__A, 0, 0); in set_qam()
8437 if (rc != 0) { in set_qam()
8438 pr_err("error %d\n", rc); in set_qam()
8445 rc = set_iqm_af(demod, true); in set_qam()
8446 if (rc != 0) { in set_qam()
8447 pr_err("error %d\n", rc); in set_qam()
8450 rc = adc_synchronization(demod); in set_qam()
8451 if (rc != 0) { in set_qam()
8452 pr_err("error %d\n", rc); in set_qam()
8456 rc = init_agc(demod); in set_qam()
8457 if (rc != 0) { in set_qam()
8458 pr_err("error %d\n", rc); in set_qam()
8461 rc = set_agc_if(demod, &(ext_attr->qam_if_agc_cfg), false); in set_qam()
8462 if (rc != 0) { in set_qam()
8463 pr_err("error %d\n", rc); in set_qam()
8466 rc = set_agc_rf(demod, &(ext_attr->qam_rf_agc_cfg), false); in set_qam()
8467 if (rc != 0) { in set_qam()
8468 pr_err("error %d\n", rc); in set_qam()
8477 rc = ctrl_set_cfg_afe_gain(demod, &qam_pga_cfg); in set_qam()
8478 if (rc != 0) { in set_qam()
8479 pr_err("error %d\n", rc); in set_qam()
8483 rc = ctrl_set_cfg_pre_saw(demod, &(ext_attr->qam_pre_saw_cfg)); in set_qam()
8484 if (rc != 0) { in set_qam()
8485 pr_err("error %d\n", rc); in set_qam()
8492 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), … in set_qam()
8493 if (rc != 0) { in set_qam()
8494 pr_err("error %d\n", rc); in set_qam()
8497 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_a_taps), ((u8 *)qam_a_taps), … in set_qam()
8498 if (rc != 0) { in set_qam()
8499 pr_err("error %d\n", rc); in set_qam()
8505 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap… in set_qam()
8506 if (rc != 0) { in set_qam()
8507 pr_err("error %d\n", rc); in set_qam()
8510 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b64_taps), ((u8 *)qam_b64_tap… in set_qam()
8511 if (rc != 0) { in set_qam()
8512 pr_err("error %d\n", rc); in set_qam()
8517 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t… in set_qam()
8518 if (rc != 0) { in set_qam()
8519 pr_err("error %d\n", rc); in set_qam()
8522 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_b256_taps), ((u8 *)qam_b256_t… in set_qam()
8523 if (rc != 0) { in set_qam()
8524 pr_err("error %d\n", rc); in set_qam()
8532 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_RE0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), … in set_qam()
8533 if (rc != 0) { in set_qam()
8534 pr_err("error %d\n", rc); in set_qam()
8537 …rc = drxdap_fasi_write_block(dev_addr, IQM_CF_TAP_IM0__A, sizeof(qam_c_taps), ((u8 *)qam_c_taps), … in set_qam()
8538 if (rc != 0) { in set_qam()
8539 pr_err("error %d\n", rc); in set_qam()
8547 rc = set_qam16(demod); in set_qam()
8548 if (rc != 0) { in set_qam()
8549 pr_err("error %d\n", rc); in set_qam()
8554 rc = set_qam32(demod); in set_qam()
8555 if (rc != 0) { in set_qam()
8556 pr_err("error %d\n", rc); in set_qam()
8561 rc = set_qam64(demod); in set_qam()
8562 if (rc != 0) { in set_qam()
8563 pr_err("error %d\n", rc); in set_qam()
8568 rc = set_qam128(demod); in set_qam()
8569 if (rc != 0) { in set_qam()
8570 pr_err("error %d\n", rc); in set_qam()
8575 rc = set_qam256(demod); in set_qam()
8576 if (rc != 0) { in set_qam()
8577 pr_err("error %d\n", rc); in set_qam()
8587 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_SCALE_SH__A, 0, 0); in set_qam()
8588 if (rc != 0) { in set_qam()
8589 pr_err("error %d\n", rc); in set_qam()
8594 rc = set_mpegtei_handling(demod); in set_qam()
8595 if (rc != 0) { in set_qam()
8596 pr_err("error %d\n", rc); in set_qam()
8599 rc = bit_reverse_mpeg_output(demod); in set_qam()
8600 if (rc != 0) { in set_qam()
8601 pr_err("error %d\n", rc); in set_qam()
8604 rc = set_mpeg_start_width(demod); in set_qam()
8605 if (rc != 0) { in set_qam()
8606 pr_err("error %d\n", rc); in set_qam()
8617 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in set_qam()
8618 if (rc != 0) { in set_qam()
8619 pr_err("error %d\n", rc); in set_qam()
8634 rc = scu_command(dev_addr, &cmd_scu); in set_qam()
8635 if (rc != 0) { in set_qam()
8636 pr_err("error %d\n", rc); in set_qam()
8641 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_ACTIVE, 0); in set_qam()
8642 if (rc != 0) { in set_qam()
8643 pr_err("error %d\n", rc); in set_qam()
8646 rc = drxj_dap_write_reg16(dev_addr, QAM_COMM_EXEC__A, QAM_COMM_EXEC_ACTIVE, 0); in set_qam()
8647 if (rc != 0) { in set_qam()
8648 pr_err("error %d\n", rc); in set_qam()
8651 rc = drxj_dap_write_reg16(dev_addr, FEC_COMM_EXEC__A, FEC_COMM_EXEC_ACTIVE, 0); in set_qam()
8652 if (rc != 0) { in set_qam()
8653 pr_err("error %d\n", rc); in set_qam()
8659 return rc; in set_qam()
8669 int rc; in qam_flip_spec() local
8680 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, &qam_ctl_ena, 0); in qam_flip_spec()
8681 if (rc != 0) { in qam_flip_spec()
8682 pr_err("error %d\n", rc); in qam_flip_spec()
8685 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, qam_ctl_ena & ~(SCU_RAM_QAM_CTL_ENA_AC… in qam_flip_spec()
8686 if (rc != 0) { in qam_flip_spec()
8687 pr_err("error %d\n", rc); in qam_flip_spec()
8692 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF__A, 0, 0); in qam_flip_spec()
8693 if (rc != 0) { in qam_flip_spec()
8694 pr_err("error %d\n", rc); in qam_flip_spec()
8697 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CF1__A, 0, 0); in qam_flip_spec()
8698 if (rc != 0) { in qam_flip_spec()
8699 pr_err("error %d\n", rc); in qam_flip_spec()
8703 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, &iqm_fs_rate_ofs, 0); in qam_flip_spec()
8704 if (rc != 0) { in qam_flip_spec()
8705 pr_err("error %d\n", rc); in qam_flip_spec()
8708 rc = drxj_dap_atomic_read_reg32(dev_addr, IQM_FS_RATE_LO__A, &iqm_fs_rate_lo, 0); in qam_flip_spec()
8709 if (rc != 0) { in qam_flip_spec()
8710 pr_err("error %d\n", rc); in qam_flip_spec()
8718 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); in qam_flip_spec()
8719 if (rc != 0) { in qam_flip_spec()
8720 pr_err("error %d\n", rc); in qam_flip_spec()
8724 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8725 if (rc != 0) { in qam_flip_spec()
8726 pr_err("error %d\n", rc); in qam_flip_spec()
8729 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8730 if (rc != 0) { in qam_flip_spec()
8731 pr_err("error %d\n", rc); in qam_flip_spec()
8736 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_CI__A, 0, 0); in qam_flip_spec()
8737 if (rc != 0) { in qam_flip_spec()
8738 pr_err("error %d\n", rc); in qam_flip_spec()
8741 rc = drxj_dap_write_reg16(dev_addr, QAM_LC_EP__A, 0, 0); in qam_flip_spec()
8742 if (rc != 0) { in qam_flip_spec()
8743 pr_err("error %d\n", rc); in qam_flip_spec()
8746 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_LA_FACTOR__A, 0, 0); in qam_flip_spec()
8747 if (rc != 0) { in qam_flip_spec()
8748 pr_err("error %d\n", rc); in qam_flip_spec()
8753 rc = drxdap_fasi_write_reg32(dev_addr, IQM_FS_RATE_OFS_LO__A, iqm_fs_rate_ofs, 0); in qam_flip_spec()
8754 if (rc != 0) { in qam_flip_spec()
8755 pr_err("error %d\n", rc); in qam_flip_spec()
8762 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_MODE__A, &data, 0); in qam_flip_spec()
8763 if (rc != 0) { in qam_flip_spec()
8764 pr_err("error %d\n", rc); in qam_flip_spec()
8769 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8770 if (rc != 0) { in qam_flip_spec()
8771 pr_err("error %d\n", rc); in qam_flip_spec()
8774 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8775 if (rc != 0) { in qam_flip_spec()
8776 pr_err("error %d\n", rc); in qam_flip_spec()
8781 rc = drxj_dap_read_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), &data, 0); in qam_flip_spec()
8782 if (rc != 0) { in qam_flip_spec()
8783 pr_err("error %d\n", rc); in qam_flip_spec()
8786 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8787 if (rc != 0) { in qam_flip_spec()
8788 pr_err("error %d\n", rc); in qam_flip_spec()
8794 rc = drxj_dap_read_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), &data, 0); in qam_flip_spec()
8795 if (rc != 0) { in qam_flip_spec()
8796 pr_err("error %d\n", rc); in qam_flip_spec()
8799 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_TAP_IM_EL0__A + (2 * i), -data, 0); in qam_flip_spec()
8800 if (rc != 0) { in qam_flip_spec()
8801 pr_err("error %d\n", rc); in qam_flip_spec()
8807 rc = drxj_dap_write_reg16(dev_addr, QAM_DQ_MODE__A, data, 0); in qam_flip_spec()
8808 if (rc != 0) { in qam_flip_spec()
8809 pr_err("error %d\n", rc); in qam_flip_spec()
8812 rc = drxj_dap_write_reg16(dev_addr, QAM_FQ_MODE__A, data, 0); in qam_flip_spec()
8813 if (rc != 0) { in qam_flip_spec()
8814 pr_err("error %d\n", rc); in qam_flip_spec()
8818 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE_TGT__A, 4, 0); in qam_flip_spec()
8819 if (rc != 0) { in qam_flip_spec()
8820 pr_err("error %d\n", rc); in qam_flip_spec()
8826 rc = drxj_dap_read_reg16(dev_addr, SCU_RAM_QAM_FSM_STATE__A, &fsm_state, 0); in qam_flip_spec()
8827 if (rc != 0) { in qam_flip_spec()
8828 pr_err("error %d\n", rc); in qam_flip_spec()
8832 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_QAM_CTL_ENA__A, (qam_ctl_ena | 0x0016), 0); in qam_flip_spec()
8833 if (rc != 0) { in qam_flip_spec()
8834 pr_err("error %d\n", rc); in qam_flip_spec()
8840 return rc; in qam_flip_spec()
8866 int rc; in qam64auto() local
8878 rc = ctrl_lock_status(demod, lock_status); in qam64auto()
8879 if (rc != 0) { in qam64auto()
8880 pr_err("error %d\n", rc); in qam64auto()
8887 rc = ctrl_get_qam_sig_quality(demod); in qam64auto()
8888 if (rc != 0) { in qam64auto()
8889 pr_err("error %d\n", rc); in qam64auto()
8904 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8905 if (rc != 0) { in qam64auto()
8906 pr_err("error %d\n", rc); in qam64auto()
8909 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8910 if (rc != 0) { in qam64auto()
8911 pr_err("error %d\n", rc); in qam64auto()
8922 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8923 if (rc != 0) { in qam64auto()
8924 pr_err("error %d\n", rc); in qam64auto()
8927 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data & 0xFFFE, 0); in qam64auto()
8928 if (rc != 0) { in qam64auto()
8929 pr_err("error %d\n", rc); in qam64auto()
8934 rc = qam_flip_spec(demod, channel); in qam64auto()
8935 if (rc != 0) { in qam64auto()
8936 pr_err("error %d\n", rc); in qam64auto()
8956 rc = ctrl_get_qam_sig_quality(demod); in qam64auto()
8957 if (rc != 0) { in qam64auto()
8958 pr_err("error %d\n", rc); in qam64auto()
8962 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, &data, 0); in qam64auto()
8963 if (rc != 0) { in qam64auto()
8964 pr_err("error %d\n", rc); in qam64auto()
8967 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, QAM_SY_TIMEOUT__A, data | 0x1, 0); in qam64auto()
8968 if (rc != 0) { in qam64auto()
8969 pr_err("error %d\n", rc); in qam64auto()
8993 return rc; in qam64auto()
9014 int rc; in qam256auto() local
9025 rc = ctrl_lock_status(demod, lock_status); in qam256auto()
9026 if (rc != 0) { in qam256auto()
9027 pr_err("error %d\n", rc); in qam256auto()
9033 rc = ctrl_get_qam_sig_quality(demod); in qam256auto()
9034 if (rc != 0) { in qam256auto()
9035 pr_err("error %d\n", rc); in qam256auto()
9051 rc = qam_flip_spec(demod, channel); in qam256auto()
9052 if (rc != 0) { in qam256auto()
9053 pr_err("error %d\n", rc); in qam256auto()
9077 return rc; in qam256auto()
9092 int rc; in set_qam_channel() local
9116 rc = set_qam(demod, channel, tuner_freq_offset, QAM_SET_OP_ALL); in set_qam_channel()
9117 if (rc != 0) { in set_qam_channel()
9118 pr_err("error %d\n", rc); in set_qam_channel()
9123 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9126 rc = qam256auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9128 if (rc != 0) { in set_qam_channel()
9129 pr_err("error %d\n", rc); in set_qam_channel()
9146 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9148 if (rc != 0) { in set_qam_channel()
9149 pr_err("error %d\n", rc); in set_qam_channel()
9152 rc = qam256auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9154 if (rc != 0) { in set_qam_channel()
9155 pr_err("error %d\n", rc); in set_qam_channel()
9172 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9175 if (rc != 0) { in set_qam_channel()
9176 pr_err("error %d\n", rc); in set_qam_channel()
9179 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9182 if (rc != 0) { in set_qam_channel()
9183 pr_err("error %d\n", rc); in set_qam_channel()
9186 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9189 if (rc != 0) { in set_qam_channel()
9190 pr_err("error %d\n", rc); in set_qam_channel()
9194 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9196 if (rc != 0) { in set_qam_channel()
9197 pr_err("error %d\n", rc); in set_qam_channel()
9200 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9203 if (rc != 0) { in set_qam_channel()
9204 pr_err("error %d\n", rc); in set_qam_channel()
9208 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9210 if (rc != 0) { in set_qam_channel()
9211 pr_err("error %d\n", rc); in set_qam_channel()
9227 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9230 if (rc != 0) { in set_qam_channel()
9231 pr_err("error %d\n", rc); in set_qam_channel()
9234 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9237 if (rc != 0) { in set_qam_channel()
9238 pr_err("error %d\n", rc); in set_qam_channel()
9241 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9244 if (rc != 0) { in set_qam_channel()
9245 pr_err("error %d\n", rc); in set_qam_channel()
9249 rc = set_qam(demod, channel, tuner_freq_offset, in set_qam_channel()
9251 if (rc != 0) { in set_qam_channel()
9252 pr_err("error %d\n", rc); in set_qam_channel()
9255 rc = drxj_dap_write_reg16(demod->my_i2c_dev_addr, in set_qam_channel()
9258 if (rc != 0) { in set_qam_channel()
9259 pr_err("error %d\n", rc); in set_qam_channel()
9262 rc = qam64auto(demod, channel, tuner_freq_offset, in set_qam_channel()
9264 if (rc != 0) { in set_qam_channel()
9265 pr_err("error %d\n", rc); in set_qam_channel()
9282 return rc; in set_qam_channel()
9299 int rc; in get_qamrs_err_count() local
9311 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_BIT_ERRORS__A, &nr_bit_errors, 0); in get_qamrs_err_count()
9312 if (rc != 0) { in get_qamrs_err_count()
9313 pr_err("error %d\n", rc); in get_qamrs_err_count()
9317 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_SYMBOL_ERRORS__A, &nr_symbol_errors, 0); in get_qamrs_err_count()
9318 if (rc != 0) { in get_qamrs_err_count()
9319 pr_err("error %d\n", rc); in get_qamrs_err_count()
9323 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_PACKET_ERRORS__A, &nr_packet_errors, 0); in get_qamrs_err_count()
9324 if (rc != 0) { in get_qamrs_err_count()
9325 pr_err("error %d\n", rc); in get_qamrs_err_count()
9329 rc = drxj_dap_read_reg16(dev_addr, FEC_RS_NR_FAILURES__A, &nr_failures, 0); in get_qamrs_err_count()
9330 if (rc != 0) { in get_qamrs_err_count()
9331 pr_err("error %d\n", rc); in get_qamrs_err_count()
9335 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_COUNT__A, &nr_snc_par_fail_count, 0); in get_qamrs_err_count()
9336 if (rc != 0) { in get_qamrs_err_count()
9337 pr_err("error %d\n", rc); in get_qamrs_err_count()
9353 return rc; in get_qamrs_err_count()
9376 int rc; in get_sig_strength() local
9384 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_IF__A, &if_gain, 0); in get_sig_strength()
9385 if (rc != 0) { in get_sig_strength()
9386 pr_err("error %d\n", rc); in get_sig_strength()
9390 rc = drxj_dap_read_reg16(dev_addr, IQM_AF_AGC_RF__A, &rf_gain, 0); in get_sig_strength()
9391 if (rc != 0) { in get_sig_strength()
9392 pr_err("error %d\n", rc); in get_sig_strength()
9435 return rc; in get_sig_strength()
9459 int rc; in ctrl_get_qam_sig_quality() local
9489 rc = get_qamrs_err_count(dev_addr, &measuredrs_errors); in ctrl_get_qam_sig_quality()
9490 if (rc != 0) { in ctrl_get_qam_sig_quality()
9491 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9495 rc = drxj_dap_read_reg16(dev_addr, QAM_SL_ERR_POWER__A, &qam_sl_err_power, 0); in ctrl_get_qam_sig_quality()
9496 if (rc != 0) { in ctrl_get_qam_sig_quality()
9497 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9501 rc = drxj_dap_read_reg16(dev_addr, FEC_OC_SNC_FAIL_PERIOD__A, &fec_oc_period, 0); in ctrl_get_qam_sig_quality()
9502 if (rc != 0) { in ctrl_get_qam_sig_quality()
9503 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9533 rc = -EIO; in ctrl_get_qam_sig_quality()
9555 rc = drxj_dap_read_reg16(dev_addr, QAM_VD_NR_QSYM_ERRORS__A, &qsym_err_vd, 0); in ctrl_get_qam_sig_quality()
9556 if (rc != 0) { in ctrl_get_qam_sig_quality()
9557 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9638 rc = get_acc_pkt_err(demod, &sig_quality->packet_error); in ctrl_get_qam_sig_quality()
9639 if (rc != 0) { in ctrl_get_qam_sig_quality()
9640 pr_err("error %d\n", rc); in ctrl_get_qam_sig_quality()
9654 return rc; in ctrl_get_qam_sig_quality()
9746 int rc; in power_down_atv() local
9758 rc = scu_command(dev_addr, &cmd_scu); in power_down_atv()
9759 if (rc != 0) { in power_down_atv()
9760 pr_err("error %d\n", rc); in power_down_atv()
9764 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (ATV_TOP_STDBY_SIF_STDBY_STANDBY & (~ATV_TOP… in power_down_atv()
9765 if (rc != 0) { in power_down_atv()
9766 pr_err("error %d\n", rc); in power_down_atv()
9770 rc = drxj_dap_write_reg16(dev_addr, ATV_COMM_EXEC__A, ATV_COMM_EXEC_STOP, 0); in power_down_atv()
9771 if (rc != 0) { in power_down_atv()
9772 pr_err("error %d\n", rc); in power_down_atv()
9776 rc = drxj_dap_write_reg16(dev_addr, IQM_COMM_EXEC__A, IQM_COMM_EXEC_STOP, 0); in power_down_atv()
9777 if (rc != 0) { in power_down_atv()
9778 pr_err("error %d\n", rc); in power_down_atv()
9781 rc = set_iqm_af(demod, false); in power_down_atv()
9782 if (rc != 0) { in power_down_atv()
9783 pr_err("error %d\n", rc); in power_down_atv()
9787 rc = drxj_dap_write_reg16(dev_addr, IQM_FS_COMM_EXEC__A, IQM_FS_COMM_EXEC_STOP, 0); in power_down_atv()
9788 if (rc != 0) { in power_down_atv()
9789 pr_err("error %d\n", rc); in power_down_atv()
9792 rc = drxj_dap_write_reg16(dev_addr, IQM_FD_COMM_EXEC__A, IQM_FD_COMM_EXEC_STOP, 0); in power_down_atv()
9793 if (rc != 0) { in power_down_atv()
9794 pr_err("error %d\n", rc); in power_down_atv()
9797 rc = drxj_dap_write_reg16(dev_addr, IQM_RC_COMM_EXEC__A, IQM_RC_COMM_EXEC_STOP, 0); in power_down_atv()
9798 if (rc != 0) { in power_down_atv()
9799 pr_err("error %d\n", rc); in power_down_atv()
9802 rc = drxj_dap_write_reg16(dev_addr, IQM_RT_COMM_EXEC__A, IQM_RT_COMM_EXEC_STOP, 0); in power_down_atv()
9803 if (rc != 0) { in power_down_atv()
9804 pr_err("error %d\n", rc); in power_down_atv()
9807 rc = drxj_dap_write_reg16(dev_addr, IQM_CF_COMM_EXEC__A, IQM_CF_COMM_EXEC_STOP, 0); in power_down_atv()
9808 if (rc != 0) { in power_down_atv()
9809 pr_err("error %d\n", rc); in power_down_atv()
9813 rc = power_down_aud(demod); in power_down_atv()
9814 if (rc != 0) { in power_down_atv()
9815 pr_err("error %d\n", rc); in power_down_atv()
9821 return rc; in power_down_atv()
9836 int rc; in power_down_aud() local
9841 rc = drxj_dap_write_reg16(dev_addr, AUD_COMM_EXEC__A, AUD_COMM_EXEC_STOP, 0); in power_down_aud()
9842 if (rc != 0) { in power_down_aud()
9843 pr_err("error %d\n", rc); in power_down_aud()
9851 return rc; in power_down_aud()
9864 int rc; in set_orx_nsu_aox() local
9868 rc = drxj_dap_read_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, &data, 0); in set_orx_nsu_aox()
9869 if (rc != 0) { in set_orx_nsu_aox()
9870 pr_err("error %d\n", rc); in set_orx_nsu_aox()
9877 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STDBY_W__A, data, 0); in set_orx_nsu_aox()
9878 if (rc != 0) { in set_orx_nsu_aox()
9879 pr_err("error %d\n", rc); in set_orx_nsu_aox()
9885 return rc; in set_orx_nsu_aox()
9914 int rc; in ctrl_set_oob() local
9951 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
9952 if (rc != 0) { in ctrl_set_oob()
9953 pr_err("error %d\n", rc); in ctrl_set_oob()
9956 rc = set_orx_nsu_aox(demod, false); in ctrl_set_oob()
9957 if (rc != 0) { in ctrl_set_oob()
9958 pr_err("error %d\n", rc); in ctrl_set_oob()
9961 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); in ctrl_set_oob()
9962 if (rc != 0) { in ctrl_set_oob()
9963 pr_err("error %d\n", rc); in ctrl_set_oob()
9993 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_STOP, 0); in ctrl_set_oob()
9994 if (rc != 0) { in ctrl_set_oob()
9995 pr_err("error %d\n", rc); in ctrl_set_oob()
10003 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10004 if (rc != 0) { in ctrl_set_oob()
10005 pr_err("error %d\n", rc); in ctrl_set_oob()
10016 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10017 if (rc != 0) { in ctrl_set_oob()
10018 pr_err("error %d\n", rc); in ctrl_set_oob()
10092 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10093 if (rc != 0) { in ctrl_set_oob()
10094 pr_err("error %d\n", rc); in ctrl_set_oob()
10098 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0xFABA, 0); in ctrl_set_oob()
10099 if (rc != 0) { in ctrl_set_oob()
10100 pr_err("error %d\n", rc); in ctrl_set_oob()
10103 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_CRX_CFG__A, OOB_CRX_DRIVE_STRENGTH << SIO_PDR_OOB_… in ctrl_set_oob()
10104 if (rc != 0) { in ctrl_set_oob()
10105 pr_err("error %d\n", rc); in ctrl_set_oob()
10108 …rc = drxj_dap_write_reg16(dev_addr, SIO_PDR_OOB_DRX_CFG__A, OOB_DRX_DRIVE_STRENGTH << SIO_PDR_OOB_… in ctrl_set_oob()
10109 if (rc != 0) { in ctrl_set_oob()
10110 pr_err("error %d\n", rc); in ctrl_set_oob()
10113 rc = drxj_dap_write_reg16(dev_addr, SIO_TOP_COMM_KEY__A, 0x0000, 0); in ctrl_set_oob()
10114 if (rc != 0) { in ctrl_set_oob()
10115 pr_err("error %d\n", rc); in ctrl_set_oob()
10119 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_COMM_KEY__A, 0, 0); in ctrl_set_oob()
10120 if (rc != 0) { in ctrl_set_oob()
10121 pr_err("error %d\n", rc); in ctrl_set_oob()
10124 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_LEN_W__A, 16000, 0); in ctrl_set_oob()
10125 if (rc != 0) { in ctrl_set_oob()
10126 pr_err("error %d\n", rc); in ctrl_set_oob()
10129 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_AAG_THR_W__A, 40, 0); in ctrl_set_oob()
10130 if (rc != 0) { in ctrl_set_oob()
10131 pr_err("error %d\n", rc); in ctrl_set_oob()
10136 rc = drxj_dap_write_reg16(dev_addr, ORX_DDC_OFO_SET_W__A, ORX_DDC_OFO_SET_W__PRE, 0); in ctrl_set_oob()
10137 if (rc != 0) { in ctrl_set_oob()
10138 pr_err("error %d\n", rc); in ctrl_set_oob()
10143 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_LOPOW_W__A, ext_attr->oob_lo_pow, 0); in ctrl_set_oob()
10144 if (rc != 0) { in ctrl_set_oob()
10145 pr_err("error %d\n", rc); in ctrl_set_oob()
10150 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TARGET_MODE__A, SCU_RAM_ORX_TARGET_MODE_2048KBPS_S… in ctrl_set_oob()
10151 if (rc != 0) { in ctrl_set_oob()
10152 pr_err("error %d\n", rc); in ctrl_set_oob()
10155 …rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FREQ_GAIN_CORR__A, SCU_RAM_ORX_FREQ_GAIN_CORR_2048… in ctrl_set_oob()
10156 if (rc != 0) { in ctrl_set_oob()
10157 pr_err("error %d\n", rc); in ctrl_set_oob()
10162 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CPH__A, 0x0001, 0); in ctrl_set_oob()
10163 if (rc != 0) { in ctrl_set_oob()
10164 pr_err("error %d\n", rc); in ctrl_set_oob()
10167 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_CTI__A, 0x0002, 0); in ctrl_set_oob()
10168 if (rc != 0) { in ctrl_set_oob()
10169 pr_err("error %d\n", rc); in ctrl_set_oob()
10172 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRN__A, 0x0004, 0); in ctrl_set_oob()
10173 if (rc != 0) { in ctrl_set_oob()
10174 pr_err("error %d\n", rc); in ctrl_set_oob()
10177 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_RST_KRP__A, 0x0008, 0); in ctrl_set_oob()
10178 if (rc != 0) { in ctrl_set_oob()
10179 pr_err("error %d\n", rc); in ctrl_set_oob()
10184 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TH__A, 2048 >> 3, 0); in ctrl_set_oob()
10185 if (rc != 0) { in ctrl_set_oob()
10186 pr_err("error %d\n", rc); in ctrl_set_oob()
10189 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10190 if (rc != 0) { in ctrl_set_oob()
10191 pr_err("error %d\n", rc); in ctrl_set_oob()
10194 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10195 if (rc != 0) { in ctrl_set_oob()
10196 pr_err("error %d\n", rc); in ctrl_set_oob()
10199 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10200 if (rc != 0) { in ctrl_set_oob()
10201 pr_err("error %d\n", rc); in ctrl_set_oob()
10204 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_AGN_LOCK_MASK__A, 1, 0); in ctrl_set_oob()
10205 if (rc != 0) { in ctrl_set_oob()
10206 pr_err("error %d\n", rc); in ctrl_set_oob()
10211 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TH__A, 10, 0); in ctrl_set_oob()
10212 if (rc != 0) { in ctrl_set_oob()
10213 pr_err("error %d\n", rc); in ctrl_set_oob()
10216 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10217 if (rc != 0) { in ctrl_set_oob()
10218 pr_err("error %d\n", rc); in ctrl_set_oob()
10221 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10222 if (rc != 0) { in ctrl_set_oob()
10223 pr_err("error %d\n", rc); in ctrl_set_oob()
10226 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10227 if (rc != 0) { in ctrl_set_oob()
10228 pr_err("error %d\n", rc); in ctrl_set_oob()
10231 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_DGN_LOCK_MASK__A, 1 << 1, 0); in ctrl_set_oob()
10232 if (rc != 0) { in ctrl_set_oob()
10233 pr_err("error %d\n", rc); in ctrl_set_oob()
10238 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TH__A, 17, 0); in ctrl_set_oob()
10239 if (rc != 0) { in ctrl_set_oob()
10240 pr_err("error %d\n", rc); in ctrl_set_oob()
10243 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10244 if (rc != 0) { in ctrl_set_oob()
10245 pr_err("error %d\n", rc); in ctrl_set_oob()
10248 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10249 if (rc != 0) { in ctrl_set_oob()
10250 pr_err("error %d\n", rc); in ctrl_set_oob()
10253 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10254 if (rc != 0) { in ctrl_set_oob()
10255 pr_err("error %d\n", rc); in ctrl_set_oob()
10258 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_FRQ_LOCK_MASK__A, 1 << 2, 0); in ctrl_set_oob()
10259 if (rc != 0) { in ctrl_set_oob()
10260 pr_err("error %d\n", rc); in ctrl_set_oob()
10265 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TH__A, 3000, 0); in ctrl_set_oob()
10266 if (rc != 0) { in ctrl_set_oob()
10267 pr_err("error %d\n", rc); in ctrl_set_oob()
10270 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10271 if (rc != 0) { in ctrl_set_oob()
10272 pr_err("error %d\n", rc); in ctrl_set_oob()
10275 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10276 if (rc != 0) { in ctrl_set_oob()
10277 pr_err("error %d\n", rc); in ctrl_set_oob()
10280 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10281 if (rc != 0) { in ctrl_set_oob()
10282 pr_err("error %d\n", rc); in ctrl_set_oob()
10285 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_PHA_LOCK_MASK__A, 1 << 3, 0); in ctrl_set_oob()
10286 if (rc != 0) { in ctrl_set_oob()
10287 pr_err("error %d\n", rc); in ctrl_set_oob()
10292 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TH__A, 400, 0); in ctrl_set_oob()
10293 if (rc != 0) { in ctrl_set_oob()
10294 pr_err("error %d\n", rc); in ctrl_set_oob()
10297 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10298 if (rc != 0) { in ctrl_set_oob()
10299 pr_err("error %d\n", rc); in ctrl_set_oob()
10302 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_ONLOCK_TTH__A, 8, 0); in ctrl_set_oob()
10303 if (rc != 0) { in ctrl_set_oob()
10304 pr_err("error %d\n", rc); in ctrl_set_oob()
10307 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_UNLOCK_TTH__A, (u16)(-8), 0); in ctrl_set_oob()
10308 if (rc != 0) { in ctrl_set_oob()
10309 pr_err("error %d\n", rc); in ctrl_set_oob()
10312 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_TIM_LOCK_MASK__A, 1 << 4, 0); in ctrl_set_oob()
10313 if (rc != 0) { in ctrl_set_oob()
10314 pr_err("error %d\n", rc); in ctrl_set_oob()
10319 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TH__A, 20, 0); in ctrl_set_oob()
10320 if (rc != 0) { in ctrl_set_oob()
10321 pr_err("error %d\n", rc); in ctrl_set_oob()
10324 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_TOTH__A, (u16)(-2048), 0); in ctrl_set_oob()
10325 if (rc != 0) { in ctrl_set_oob()
10326 pr_err("error %d\n", rc); in ctrl_set_oob()
10329 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_ONLOCK_TTH__A, 4, 0); in ctrl_set_oob()
10330 if (rc != 0) { in ctrl_set_oob()
10331 pr_err("error %d\n", rc); in ctrl_set_oob()
10334 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_UNLOCK_TTH__A, (u16)(-4), 0); in ctrl_set_oob()
10335 if (rc != 0) { in ctrl_set_oob()
10336 pr_err("error %d\n", rc); in ctrl_set_oob()
10339 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_ORX_EQU_LOCK_MASK__A, 1 << 5, 0); in ctrl_set_oob()
10340 if (rc != 0) { in ctrl_set_oob()
10341 pr_err("error %d\n", rc); in ctrl_set_oob()
10346 …rc = drxdap_fasi_write_block(dev_addr, ORX_FWP_PFI_A_W__A, sizeof(pfi_coeffs[mode_index]), ((u8 *)… in ctrl_set_oob()
10347 if (rc != 0) { in ctrl_set_oob()
10348 pr_err("error %d\n", rc); in ctrl_set_oob()
10351 rc = drxj_dap_write_reg16(dev_addr, ORX_TOP_MDE_W__A, mode_index, 0); in ctrl_set_oob()
10352 if (rc != 0) { in ctrl_set_oob()
10353 pr_err("error %d\n", rc); in ctrl_set_oob()
10359 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, i, 0); in ctrl_set_oob()
10360 if (rc != 0) { in ctrl_set_oob()
10361 pr_err("error %d\n", rc); in ctrl_set_oob()
10364 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_COF_RW__A, nyquist_coeffs[mode_index][i], 0); in ctrl_set_oob()
10365 if (rc != 0) { in ctrl_set_oob()
10366 pr_err("error %d\n", rc); in ctrl_set_oob()
10370 rc = drxj_dap_write_reg16(dev_addr, ORX_FWP_NYQ_ADR_W__A, 31, 0); in ctrl_set_oob()
10371 if (rc != 0) { in ctrl_set_oob()
10372 pr_err("error %d\n", rc); in ctrl_set_oob()
10375 rc = drxj_dap_write_reg16(dev_addr, ORX_COMM_EXEC__A, ORX_COMM_EXEC_ACTIVE, 0); in ctrl_set_oob()
10376 if (rc != 0) { in ctrl_set_oob()
10377 pr_err("error %d\n", rc); in ctrl_set_oob()
10388 rc = scu_command(dev_addr, &scu_cmd); in ctrl_set_oob()
10389 if (rc != 0) { in ctrl_set_oob()
10390 pr_err("error %d\n", rc); in ctrl_set_oob()
10394 rc = set_orx_nsu_aox(demod, true); in ctrl_set_oob()
10395 if (rc != 0) { in ctrl_set_oob()
10396 pr_err("error %d\n", rc); in ctrl_set_oob()
10399 rc = drxj_dap_write_reg16(dev_addr, ORX_NSU_AOX_STHR_W__A, ext_attr->oob_pre_saw, 0); in ctrl_set_oob()
10400 if (rc != 0) { in ctrl_set_oob()
10401 pr_err("error %d\n", rc); in ctrl_set_oob()
10409 return rc; in ctrl_set_oob()
10437 int rc; in ctrl_set_channel() local
10500 rc = ctrl_set_uio_cfg(demod, &uio_cfg); in ctrl_set_channel()
10501 if (rc != 0) { in ctrl_set_channel()
10502 pr_err("error %d\n", rc); in ctrl_set_channel()
10595 rc = ctrl_uio_write(demod, &uio1); in ctrl_set_channel()
10596 if (rc != 0) { in ctrl_set_channel()
10597 pr_err("error %d\n", rc); in ctrl_set_channel()
10602 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in ctrl_set_channel()
10603 if (rc != 0) { in ctrl_set_channel()
10604 pr_err("error %d\n", rc); in ctrl_set_channel()
10617 rc = set_vsb(demod); in ctrl_set_channel()
10618 if (rc != 0) { in ctrl_set_channel()
10619 pr_err("error %d\n", rc); in ctrl_set_channel()
10622 rc = set_frequency(demod, channel, tuner_freq_offset); in ctrl_set_channel()
10623 if (rc != 0) { in ctrl_set_channel()
10624 pr_err("error %d\n", rc); in ctrl_set_channel()
10632 rc = set_qam_channel(demod, channel, tuner_freq_offset); in ctrl_set_channel()
10633 if (rc != 0) { in ctrl_set_channel()
10634 pr_err("error %d\n", rc); in ctrl_set_channel()
10649 return rc; in ctrl_set_channel()
10676 int rc; in ctrl_sig_quality() local
10680 rc = get_sig_strength(demod, &strength); in ctrl_sig_quality()
10681 if (rc < 0) { in ctrl_sig_quality()
10682 pr_err("error getting signal strength %d\n", rc); in ctrl_sig_quality()
10692 rc = get_acc_pkt_err(demod, &pkt); in ctrl_sig_quality()
10693 if (rc != 0) { in ctrl_sig_quality()
10694 pr_err("error %d\n", rc); in ctrl_sig_quality()
10707 rc = get_vsb_post_rs_pck_err(dev_addr, &err, &pkt); in ctrl_sig_quality()
10708 if (rc != 0) { in ctrl_sig_quality()
10709 pr_err("error %d getting UCB\n", rc); in ctrl_sig_quality()
10719 rc = get_vs_bpre_viterbi_ber(dev_addr, &ber, &cnt); in ctrl_sig_quality()
10720 if (rc != 0) { in ctrl_sig_quality()
10721 pr_err("error %d getting pre-ber\n", rc); in ctrl_sig_quality()
10730 rc = get_vs_bpost_viterbi_ber(dev_addr, &ber, &cnt); in ctrl_sig_quality()
10731 if (rc != 0) { in ctrl_sig_quality()
10732 pr_err("error %d getting post-ber\n", rc); in ctrl_sig_quality()
10740 rc = get_vsbmer(dev_addr, &mer); in ctrl_sig_quality()
10741 if (rc != 0) { in ctrl_sig_quality()
10742 pr_err("error %d getting MER\n", rc); in ctrl_sig_quality()
10754 rc = ctrl_get_qam_sig_quality(demod); in ctrl_sig_quality()
10755 if (rc != 0) { in ctrl_sig_quality()
10756 pr_err("error %d\n", rc); in ctrl_sig_quality()
10767 return rc; in ctrl_sig_quality()
10792 int rc; in ctrl_lock_status() local
10831 rc = scu_command(dev_addr, &cmd_scu); in ctrl_lock_status()
10832 if (rc != 0) { in ctrl_lock_status()
10833 pr_err("error %d\n", rc); in ctrl_lock_status()
10855 return rc; in ctrl_lock_status()
10874 int rc; in ctrl_set_standard() local
10892 rc = power_down_qam(demod, false); in ctrl_set_standard()
10893 if (rc != 0) { in ctrl_set_standard()
10894 pr_err("error %d\n", rc); in ctrl_set_standard()
10900 rc = power_down_vsb(demod, false); in ctrl_set_standard()
10901 if (rc != 0) { in ctrl_set_standard()
10902 pr_err("error %d\n", rc); in ctrl_set_standard()
10911 rc = -EINVAL; in ctrl_set_standard()
10928 rc = drxj_dap_read_reg16(demod->my_i2c_dev_addr, SCU_RAM_VERSION_HI__A, &dummy, 0); in ctrl_set_standard()
10929 if (rc != 0) { in ctrl_set_standard()
10930 pr_err("error %d\n", rc); in ctrl_set_standard()
10937 rc = set_vsb_leak_n_gain(demod); in ctrl_set_standard()
10938 if (rc != 0) { in ctrl_set_standard()
10939 pr_err("error %d\n", rc); in ctrl_set_standard()
10952 return rc; in ctrl_set_standard()
11034 int rc; in ctrl_power_mode() local
11070 rc = power_up_device(demod); in ctrl_power_mode()
11071 if (rc != 0) { in ctrl_power_mode()
11072 pr_err("error %d\n", rc); in ctrl_power_mode()
11098 rc = power_down_qam(demod, true); in ctrl_power_mode()
11099 if (rc != 0) { in ctrl_power_mode()
11100 pr_err("error %d\n", rc); in ctrl_power_mode()
11105 rc = power_down_vsb(demod, true); in ctrl_power_mode()
11106 if (rc != 0) { in ctrl_power_mode()
11107 pr_err("error %d\n", rc); in ctrl_power_mode()
11118 rc = power_down_atv(demod, ext_attr->standard, true); in ctrl_power_mode()
11119 if (rc != 0) { in ctrl_power_mode()
11120 pr_err("error %d\n", rc); in ctrl_power_mode()
11135 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_PWD_MODE__A, sio_cc_pwd_mode, 0); in ctrl_power_mode()
11136 if (rc != 0) { in ctrl_power_mode()
11137 pr_err("error %d\n", rc); in ctrl_power_mode()
11140 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); in ctrl_power_mode()
11141 if (rc != 0) { in ctrl_power_mode()
11142 pr_err("error %d\n", rc); in ctrl_power_mode()
11148 rc = init_hi(demod); in ctrl_power_mode()
11149 if (rc != 0) { in ctrl_power_mode()
11150 pr_err("error %d\n", rc); in ctrl_power_mode()
11155 rc = hi_cfg_command(demod); in ctrl_power_mode()
11156 if (rc != 0) { in ctrl_power_mode()
11157 pr_err("error %d\n", rc); in ctrl_power_mode()
11167 return rc; in ctrl_power_mode()
11190 int rc; in ctrl_set_cfg_pre_saw() local
11207 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PDREF__A, pre_saw->reference, 0); in ctrl_set_cfg_pre_saw()
11208 if (rc != 0) { in ctrl_set_cfg_pre_saw()
11209 pr_err("error %d\n", rc); in ctrl_set_cfg_pre_saw()
11232 return rc; in ctrl_set_cfg_pre_saw()
11253 int rc; in ctrl_set_cfg_afe_gain() local
11288 rc = drxj_dap_write_reg16(dev_addr, IQM_AF_PGA_GAIN__A, gain, 0); in ctrl_set_cfg_afe_gain()
11289 if (rc != 0) { in ctrl_set_cfg_afe_gain()
11290 pr_err("error %d\n", rc); in ctrl_set_cfg_afe_gain()
11313 return rc; in ctrl_set_cfg_afe_gain()
11346 int rc; in drxj_open() local
11365 rc = ctrl_power_mode(demod, &power_mode); in drxj_open()
11366 if (rc != 0) { in drxj_open()
11367 pr_err("error %d\n", rc); in drxj_open()
11371 rc = -EINVAL; in drxj_open()
11377 rc = get_device_capabilities(demod); in drxj_open()
11378 if (rc != 0) { in drxj_open()
11379 pr_err("error %d\n", rc); in drxj_open()
11391 …rc = drxj_dap_write_reg16(dev_addr, SIO_CC_SOFT_RST__A, (0x04 | SIO_CC_SOFT_RST_SYS__M | SIO_CC_SO… in drxj_open()
11392 if (rc != 0) { in drxj_open()
11393 pr_err("error %d\n", rc); in drxj_open()
11396 rc = drxj_dap_write_reg16(dev_addr, SIO_CC_UPDATE__A, SIO_CC_UPDATE_KEY, 0); in drxj_open()
11397 if (rc != 0) { in drxj_open()
11398 pr_err("error %d\n", rc); in drxj_open()
11405 …rc = drxj_dap_write_reg16(dev_addr, ATV_TOP_STDBY__A, (~ATV_TOP_STDBY_CVBS_STDBY_A2_ACTIVE) | ATV_… in drxj_open()
11406 if (rc != 0) { in drxj_open()
11407 pr_err("error %d\n", rc); in drxj_open()
11411 rc = set_iqm_af(demod, false); in drxj_open()
11412 if (rc != 0) { in drxj_open()
11413 pr_err("error %d\n", rc); in drxj_open()
11416 rc = set_orx_nsu_aox(demod, false); in drxj_open()
11417 if (rc != 0) { in drxj_open()
11418 pr_err("error %d\n", rc); in drxj_open()
11422 rc = init_hi(demod); in drxj_open()
11423 if (rc != 0) { in drxj_open()
11424 pr_err("error %d\n", rc); in drxj_open()
11432 rc = ctrl_set_cfg_mpeg_output(demod, &cfg_mpeg_output); in drxj_open()
11433 if (rc != 0) { in drxj_open()
11434 pr_err("error %d\n", rc); in drxj_open()
11438 rc = power_down_aud(demod); in drxj_open()
11439 if (rc != 0) { in drxj_open()
11440 pr_err("error %d\n", rc); in drxj_open()
11444 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_STOP, 0); in drxj_open()
11445 if (rc != 0) { in drxj_open()
11446 pr_err("error %d\n", rc); in drxj_open()
11459 rc = -EINVAL; in drxj_open()
11463 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_UPLOAD); in drxj_open()
11464 if (rc != 0) { in drxj_open()
11465 pr_err("error %d while uploading the firmware\n", rc); in drxj_open()
11469 rc = drx_ctrl_u_code(demod, &ucode_info, UCODE_VERIFY); in drxj_open()
11470 if (rc != 0) { in drxj_open()
11472 rc); in drxj_open()
11480 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in drxj_open()
11481 if (rc != 0) { in drxj_open()
11482 pr_err("error %d\n", rc); in drxj_open()
11493 rc = smart_ant_init(demod); in drxj_open()
11494 if (rc != 0) { in drxj_open()
11495 pr_err("error %d\n", rc); in drxj_open()
11518 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_HI__A, (u16)(driver_version >> 16), 0); in drxj_open()
11519 if (rc != 0) { in drxj_open()
11520 pr_err("error %d\n", rc); in drxj_open()
11523 rc = drxj_dap_write_reg16(dev_addr, SCU_RAM_DRIVER_VER_LO__A, (u16)(driver_version & 0xFFFF), 0); in drxj_open()
11524 if (rc != 0) { in drxj_open()
11525 pr_err("error %d\n", rc); in drxj_open()
11529 rc = ctrl_set_oob(demod, NULL); in drxj_open()
11530 if (rc != 0) { in drxj_open()
11531 pr_err("error %d\n", rc); in drxj_open()
11543 return rc; in drxj_open()
11556 int rc; in drxj_close() local
11567 rc = ctrl_power_mode(demod, &power_mode); in drxj_close()
11568 if (rc != 0) { in drxj_close()
11569 pr_err("error %d\n", rc); in drxj_close()
11573 rc = drxj_dap_write_reg16(dev_addr, SCU_COMM_EXEC__A, SCU_COMM_EXEC_ACTIVE, 0); in drxj_close()
11574 if (rc != 0) { in drxj_close()
11575 pr_err("error %d\n", rc); in drxj_close()
11579 rc = ctrl_power_mode(demod, &power_mode); in drxj_close()
11580 if (rc != 0) { in drxj_close()
11581 pr_err("error %d\n", rc); in drxj_close()
11591 return rc; in drxj_close()
11736 int rc; in drx_ctrl_u_code() local
11752 rc = request_firmware(&fw, mc_file, demod->i2c->dev.parent); in drx_ctrl_u_code()
11753 if (rc < 0) { in drx_ctrl_u_code()
11755 return rc; in drx_ctrl_u_code()
11759 rc = -EINVAL; in drx_ctrl_u_code()
11777 rc = -EINVAL; in drx_ctrl_u_code()
11783 rc = drx_check_firmware(demod, (u8 *)mc_data_init, size); in drx_ctrl_u_code()
11784 if (rc) in drx_ctrl_u_code()
11819 rc = -EINVAL; in drx_ctrl_u_code()
11836 rc = -EIO; in drx_ctrl_u_code()
11863 rc = -EIO; in drx_ctrl_u_code()
11873 rc = -EIO; in drx_ctrl_u_code()
11884 rc = -EINVAL; in drx_ctrl_u_code()
11891 rc = 0; in drx_ctrl_u_code()
11896 return rc; in drx_ctrl_u_code()
12211 int rc = 0; in drx39xxj_init() local
12216 rc = drxj_open(demod); in drx39xxj_init()
12217 if (rc != 0) in drx39xxj_init()
12218 pr_err("drx39xxj_init(): DRX open failed rc=%d!\n", rc); in drx39xxj_init()
12222 return rc; in drx39xxj_init()