Lines Matching +full:0 +full:xfff7
32 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
38 } while (0)
54 AS_START = 0,
61 SYMBOL_DEPENDENT_OFF = 0,
141 DIB8000_POWER_ALL = 0,
149 {.addr = i2c->addr >> 1, .flags = 0, .len = 2}, in dib8000_i2c_read16()
153 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) { in dib8000_i2c_read16()
155 return 0; in dib8000_i2c_read16()
158 msg[0].buf = i2c->i2c_write_buffer; in dib8000_i2c_read16()
159 msg[0].buf[0] = reg >> 8; in dib8000_i2c_read16()
160 msg[0].buf[1] = reg & 0xff; in dib8000_i2c_read16()
166 ret = (msg[1].buf[0] << 8) | msg[1].buf[1]; in dib8000_i2c_read16()
175 state->i2c_write_buffer[0] = reg >> 8; in __dib8000_read_word()
176 state->i2c_write_buffer[1] = reg & 0xff; in __dib8000_read_word()
178 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in __dib8000_read_word()
179 state->msg[0].addr = state->i2c.addr >> 1; in __dib8000_read_word()
180 state->msg[0].flags = 0; in __dib8000_read_word()
181 state->msg[0].buf = state->i2c_write_buffer; in __dib8000_read_word()
182 state->msg[0].len = 2; in __dib8000_read_word()
191 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in __dib8000_read_word()
200 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_read_word()
202 return 0; in dib8000_read_word()
216 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_read32()
218 return 0; in dib8000_read32()
221 rw[0] = __dib8000_read_word(state, reg + 0); in dib8000_read32()
226 return ((rw[0] << 16) | (rw[1])); in dib8000_read32()
231 struct i2c_msg msg = {.addr = i2c->addr >> 1, .flags = 0, .len = 4}; in dib8000_i2c_write16()
232 int ret = 0; in dib8000_i2c_write16()
234 if (mutex_lock_interruptible(i2c->i2c_buffer_lock) < 0) { in dib8000_i2c_write16()
240 msg.buf[0] = (reg >> 8) & 0xff; in dib8000_i2c_write16()
241 msg.buf[1] = reg & 0xff; in dib8000_i2c_write16()
242 msg.buf[2] = (val >> 8) & 0xff; in dib8000_i2c_write16()
243 msg.buf[3] = val & 0xff; in dib8000_i2c_write16()
245 ret = i2c_transfer(i2c->adap, &msg, 1) != 1 ? -EREMOTEIO : 0; in dib8000_i2c_write16()
255 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib8000_write_word()
260 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib8000_write_word()
261 state->i2c_write_buffer[1] = reg & 0xff; in dib8000_write_word()
262 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib8000_write_word()
263 state->i2c_write_buffer[3] = val & 0xff; in dib8000_write_word()
265 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib8000_write_word()
266 state->msg[0].addr = state->i2c.addr >> 1; in dib8000_write_word()
267 state->msg[0].flags = 0; in dib8000_write_word()
268 state->msg[0].buf = state->i2c_write_buffer; in dib8000_write_word()
269 state->msg[0].len = 4; in dib8000_write_word()
272 -EREMOTEIO : 0); in dib8000_write_word()
279 …(769 << 5) | 0x0a, (745 << 5) | 0x03, (595 << 5) | 0x0d, (769 << 5) | 0x0a, (920 << 5) | 0x09, (78…
280 (920 << 5) | 0x09
284 …(692 << 5) | 0x0b, (683 << 5) | 0x01, (519 << 5) | 0x09, (692 << 5) | 0x0b, 0 | 0x1f, 0 | 0x1f, 0 …
288 …(832 << 5) | 0x10, (912 << 5) | 0x05, (900 << 5) | 0x12, (832 << 5) | 0x10, (-931 << 5) | 0x0f, (9…
289 (-931 << 5) | 0x0f
293 …(622 << 5) | 0x0c, (941 << 5) | 0x04, (796 << 5) | 0x10, (622 << 5) | 0x0c, (982 << 5) | 0x0c, (51…
294 (982 << 5) | 0x0c
298 …(699 << 5) | 0x14, (607 << 5) | 0x04, (944 << 5) | 0x13, (699 << 5) | 0x14, (-720 << 5) | 0x0d, (6…
299 (-720 << 5) | 0x0d
303 …(664 << 5) | 0x0c, (925 << 5) | 0x03, (937 << 5) | 0x10, (664 << 5) | 0x0c, (-610 << 5) | 0x0a, (6…
304 (-610 << 5) | 0x0a
308 …(-955 << 5) | 0x0e, (687 << 5) | 0x04, (818 << 5) | 0x10, (-955 << 5) | 0x0e, (-922 << 5) | 0x0d, …
309 (-922 << 5) | 0x0d
313 …(638 << 5) | 0x0d, (683 << 5) | 0x02, (638 << 5) | 0x0d, (638 << 5) | 0x0d, (-655 << 5) | 0x0a, (5…
314 (-655 << 5) | 0x0a
318 …(-707 << 5) | 0x14, (910 << 5) | 0x06, (889 << 5) | 0x16, (-707 << 5) | 0x14, (-958 << 5) | 0x13, …
319 (-958 << 5) | 0x13
323 …(-723 << 5) | 0x13, (910 << 5) | 0x05, (777 << 5) | 0x14, (-723 << 5) | 0x13, (-568 << 5) | 0x0f, …
324 (-568 << 5) | 0x0f
328 …(-940 << 5) | 0x15, (607 << 5) | 0x05, (915 << 5) | 0x16, (-940 << 5) | 0x15, (-848 << 5) | 0x13, …
329 (-848 << 5) | 0x13
333 …(612 << 5) | 0x12, (910 << 5) | 0x04, (864 << 5) | 0x14, (612 << 5) | 0x12, (-869 << 5) | 0x13, (6…
334 (-869 << 5) | 0x13
338 …(-835 << 5) | 0x12, (684 << 5) | 0x05, (735 << 5) | 0x14, (-835 << 5) | 0x12, (-598 << 5) | 0x10, …
339 (-598 << 5) | 0x10
343 …(673 << 5) | 0x0f, (683 << 5) | 0x03, (808 << 5) | 0x12, (673 << 5) | 0x0f, (585 << 5) | 0x0f, (51…
344 (585 << 5) | 0x0f
348 …(863 << 5) | 0x17, (930 << 5) | 0x07, (878 << 5) | 0x19, (863 << 5) | 0x17, (0 << 5) | 0x14, (521 …
349 (0 << 5) | 0x14
353 …(-924 << 5) | 0x17, (910 << 5) | 0x06, (774 << 5) | 0x17, (-924 << 5) | 0x17, (-877 << 5) | 0x15, …
354 (-877 << 5) | 0x15
358 …(-921 << 5) | 0x19, (607 << 5) | 0x06, (881 << 5) | 0x19, (-921 << 5) | 0x19, (-921 << 5) | 0x14, …
359 (-921 << 5) | 0x14
363 …(514 << 5) | 0x14, (910 << 5) | 0x05, (861 << 5) | 0x17, (514 << 5) | 0x14, (690 << 5) | 0x14, (68…
364 (690 << 5) | 0x14
376 396, 305, 105, -51, -77, -12, 41, 31, -11, -30, -11, 14, 15, -2, -13, -7, 5, 8, 1, -6, -7, -3, 0, 1
382 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in fft_to_mode()
401 nud |= (1 << 3) | (1 << 0); in dib8000_set_acquisition_mode()
408 u16 outreg, fifo_threshold, smo_mode, sram = 0x0205; /* by default SDRAM deintlv is enabled */ in dib8000_set_output_mode()
411 outreg = 0; in dib8000_set_output_mode()
413 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8000_set_output_mode()
416 &state->fe[0], mode); in dib8000_set_output_mode()
420 outreg = (1 << 10); /* 0x0400 */ in dib8000_set_output_mode()
423 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ in dib8000_set_output_mode()
426 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ in dib8000_set_output_mode()
430 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ in dib8000_set_output_mode()
431 sram &= 0xfdff; in dib8000_set_output_mode()
433 sram |= 0x0c00; in dib8000_set_output_mode()
441 outreg = 0; in dib8000_set_output_mode()
451 &state->fe[0]); in dib8000_set_output_mode()
463 return 0; in dib8000_set_output_mode()
469 u16 tmp, sync_wait = dib8000_read_word(state, 273) & 0xfff0; in dib8000_set_diversity_in()
476 dib8000_write_word(state, 272, 0); //dvsy_off_lmod4 = 0 in dib8000_set_diversity_in()
477 dib8000_write_word(state, 273, sync_wait); // sync_enable = 0; comb_mode = 0 in dib8000_set_diversity_in()
482 case 0: /* only use the internal way - not the diversity input */ in dib8000_set_diversity_in()
484 dib8000_write_word(state, 271, 0); in dib8000_set_diversity_in()
491 dib8000_write_word(state, 270, 0); in dib8000_set_diversity_in()
496 if (state->revision == 0x8002) { in dib8000_set_diversity_in()
502 return 0; in dib8000_set_diversity_in()
508 u16 reg_774 = 0x3fff, reg_775 = 0xffff, reg_776 = 0xffff, in dib8000_set_power_mode()
509 reg_900 = (dib8000_read_word(state, 900) & 0xfffc) | 0x3, in dib8000_set_power_mode()
512 if (state->revision != 0x8090) in dib8000_set_power_mode()
513 reg_1280 = (dib8000_read_word(state, 1280) & 0x00ff) | 0xff00; in dib8000_set_power_mode()
515 reg_1280 = (dib8000_read_word(state, 1280) & 0x707f) | 0x8f80; in dib8000_set_power_mode()
521 reg_774 = 0x0000; in dib8000_set_power_mode()
522 reg_775 = 0x0000; in dib8000_set_power_mode()
523 reg_776 = 0x0000; in dib8000_set_power_mode()
524 reg_900 &= 0xfffc; in dib8000_set_power_mode()
525 if (state->revision != 0x8090) in dib8000_set_power_mode()
526 reg_1280 &= 0x00ff; in dib8000_set_power_mode()
528 reg_1280 &= 0x707f; in dib8000_set_power_mode()
531 if (state->revision != 0x8090) in dib8000_set_power_mode()
532 reg_1280 &= 0x00ff; in dib8000_set_power_mode()
534 reg_1280 &= 0xfa7b; in dib8000_set_power_mode()
548 int ret = 0; in dib8000_set_adc_state()
554 if (state->revision != 0x8090) { in dib8000_set_adc_state()
555 reg_908 |= (1 << 1) | (1 << 0); in dib8000_set_adc_state()
567 /* en_slowAdc = 1 & reset_sladc = 0 */ in dib8000_set_adc_state()
570 reg = dib8000_read_word(state, 921) & ~((0x3 << 14) in dib8000_set_adc_state()
571 | (0x3 << 12)); in dib8000_set_adc_state()
580 if (state->revision == 0x8090) { in dib8000_set_adc_state()
582 /* reset_sladc = 1 en_slowAdc = 0 */ in dib8000_set_adc_state()
586 reg_908 |= (1 << 1) | (1 << 0); in dib8000_set_adc_state()
590 reg_907 &= 0x0fff; in dib8000_set_adc_state()
591 reg_908 &= 0x0003; in dib8000_set_adc_state()
622 if (bw == 0) in dib8000_set_bandwidth()
625 if (state->timf == 0) { in dib8000_set_bandwidth()
633 dib8000_write_word(state, 29, (u16) ((timf >> 16) & 0xffff)); in dib8000_set_bandwidth()
634 dib8000_write_word(state, 30, (u16) ((timf) & 0xffff)); in dib8000_set_bandwidth()
636 return 0; in dib8000_set_bandwidth()
643 if (state->revision == 0x8090) { in dib8000_sad_calib()
647 dib8000_write_word(state, 922, (sad_sel << 2) | 0x1); in dib8000_sad_calib()
651 dib8000_write_word(state, 923, (0 << 1) | (0 << 0)); in dib8000_sad_calib()
655 dib8000_write_word(state, 923, (1 << 0)); in dib8000_sad_calib()
656 dib8000_write_word(state, 923, (0 << 0)); in dib8000_sad_calib()
660 return 0; in dib8000_sad_calib()
675 if (state->revision != 0x8090) { in dib8000_reset_pll_common()
677 (u16) (((bw->internal * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
679 (u16) ((bw->internal * 1000) & 0xffff)); in dib8000_reset_pll_common()
681 dib8000_write_word(state, 23, (u16) (((bw->internal / 2 * 1000) >> 16) & 0xffff)); in dib8000_reset_pll_common()
683 (u16) ((bw->internal / 2 * 1000) & 0xffff)); in dib8000_reset_pll_common()
685 dib8000_write_word(state, 27, (u16) ((bw->ifreq >> 16) & 0x01ff)); in dib8000_reset_pll_common()
686 dib8000_write_word(state, 28, (u16) (bw->ifreq & 0xffff)); in dib8000_reset_pll_common()
687 dib8000_write_word(state, 26, (u16) ((bw->ifreq >> 25) & 0x0003)); in dib8000_reset_pll_common()
689 if (state->revision != 0x8090) in dib8000_reset_pll_common()
698 if (state->revision != 0x8090) { in dib8000_reset_pll()
700 (pll->pll_prediv << 8) | (pll->pll_ratio << 0)); in dib8000_reset_pll()
702 clk_cfg1 = (1 << 10) | (0 << 9) | (pll->IO_CLK_en_core << 8) | in dib8000_reset_pll()
705 (pll->pll_reset << 0); in dib8000_reset_pll()
708 clk_cfg1 = (clk_cfg1 & 0xfff7) | (pll->pll_bypass << 3); in dib8000_reset_pll()
711 dprintk("clk_cfg1: 0x%04x\n", clk_cfg1); in dib8000_reset_pll()
714 if (state->cfg.pll->ADClkSrc == 0) in dib8000_reset_pll()
716 (0 << 15) | (0 << 12) | (0 << 10) | in dib8000_reset_pll()
718 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
719 else if (state->cfg.refclksel != 0) in dib8000_reset_pll()
720 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
721 ((state->cfg.refclksel & 0x3) << 10) | in dib8000_reset_pll()
723 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
725 dib8000_write_word(state, 904, (0 << 15) | (1 << 12) | in dib8000_reset_pll()
727 (pll->ADClkSrc << 7) | (0 << 1)); in dib8000_reset_pll()
754 prediv = reg_1856 & 0x3f; in dib8000_update_pll()
755 loopdiv = (reg_1856 >> 6) & 0x3f; in dib8000_update_pll()
762 if (state->revision == 0x8090) { in dib8000_update_pll()
763 reg_1856 &= 0xf000; in dib8000_update_pll()
769 ((pll->pll_ratio & 0x3f) << 6) | in dib8000_update_pll()
770 (pll->pll_prediv & 0x3f)); in dib8000_update_pll()
781 (u16) (((internal / 2) >> 16) & 0xffff)); in dib8000_update_pll()
782 dib8000_write_word(state, 24, (u16) ((internal / 2) & 0xffff)); in dib8000_update_pll()
786 while (((dib8000_read_word(state, 1856)>>15)&0x1) != 1) in dib8000_update_pll()
792 reg_1856&0x3f, (reg_1856>>6)&0x3f); in dib8000_update_pll()
805 dib8000_write_word(state, 898, 0x0004); /* sad */ in dib8000_update_pll()
812 if (ratio != 0) { in dib8000_update_pll()
815 …dib8000_write_word(state, 901, (state->cfg.pll->pll_prediv << 8) | (ratio << 0)); /* only the PLL … in dib8000_update_pll()
819 return 0; in dib8000_update_pll()
833 return 0; in dib8000_reset_gpio()
840 st->cfg.gpio_dir |= (dir & 0x1) << num; /* set the new direction */ in dib8000_cfg_gpio()
845 st->cfg.gpio_val |= (val & 0x01) << num; /* set the new value */ in dib8000_cfg_gpio()
850 return 0; in dib8000_cfg_gpio()
863 0x0004,
864 0x0400,
865 0x0814,
868 0x001b,
869 0x7740,
870 0x005b,
871 0x8d80,
872 0x01c9,
873 0xc380,
874 0x0000,
875 0x0080,
876 0x0000,
877 0x0090,
878 0x0001,
879 0xd4c0,
882 0x6680 // P_corm_thres Lock algorithms configuration */
898 0,
899 0,
900 0,
901 0,
904 0x0410,
909 0x2800, // P_coff_corthres_ ( 2k 4k 8k ) 0x2800
910 0x2800,
911 0x2800,
912 0x2800, // P_coff_cpilthres_ ( 2k 4k 8k ) 0x2800
913 0x2800,
914 0x2800,
917 0x0666, // P_pha3_thres
918 0x0000, // P_cti_use_cpe, P_cti_use_prog
921 0x200f, // P_cspu_regul, P_cspu_win_cut
922 0x000f, // P_des_shift_work
925 0x023d, // P_adp_regul_cnt
926 0x00a4, // P_adp_noise_cnt
927 0x00a4, // P_adp_regul_ext
928 0x7ff0, // P_adp_noise_ext
929 0x3ccc, // P_adp_fil
932 0x0000, // P_2d_byp_ti_num
935 0x800, //P_equal_thres_wgn
941 0x0001, // P_div_lock0_wait
943 0x0020, //p_fec_
945 …0x0062, /* P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard …
950 (0 << 9) | /* P_ctrl_pre_freq_inh=0 */
952 (1 << 0), /* P_pre_freq_win_len=1 */
954 0,
964 if ((value = dib8000_i2c_read16(client, 896)) != 0x01b3) { in dib8000_identify()
965 dprintk("wrong Vendor ID (read=0x%x)\n", value); in dib8000_identify()
966 return 0; in dib8000_identify()
970 if (value != 0x8000 && value != 0x8001 && in dib8000_identify()
971 value != 0x8002 && value != 0x8090) { in dib8000_identify()
973 return 0; in dib8000_identify()
977 case 0x8000: in dib8000_identify()
980 case 0x8001: in dib8000_identify()
983 case 0x8002: in dib8000_identify()
986 case 0x8090: in dib8000_identify()
998 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_reset_stats()
1001 memset(&c->strength, 0, sizeof(c->strength)); in dib8000_reset_stats()
1002 memset(&c->cnr, 0, sizeof(c->cnr)); in dib8000_reset_stats()
1003 memset(&c->post_bit_error, 0, sizeof(c->post_bit_error)); in dib8000_reset_stats()
1004 memset(&c->post_bit_count, 0, sizeof(c->post_bit_count)); in dib8000_reset_stats()
1005 memset(&c->block_error, 0, sizeof(c->block_error)); in dib8000_reset_stats()
1014 c->strength.stat[0].scale = FE_SCALE_DECIBEL; in dib8000_reset_stats()
1015 c->strength.stat[0].uvalue = 0; in dib8000_reset_stats()
1017 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1018 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1019 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1020 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1021 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_reset_stats()
1026 state->ber_jiffies_stats = 0; in dib8000_reset_stats()
1027 state->per_jiffies_stats = 0; in dib8000_reset_stats()
1028 memset(&state->ber_jiffies_stats_layer, 0, in dib8000_reset_stats()
1036 if ((state->revision = dib8000_identify(&state->i2c)) == 0) in dib8000_reset()
1040 if (state->revision != 0x8090) in dib8000_reset()
1041 dib8000_write_word(state, 1287, 0x0003); in dib8000_reset()
1043 if (state->revision == 0x8000) in dib8000_reset()
1054 dib8000_write_word(state, 770, 0xffff); in dib8000_reset()
1055 dib8000_write_word(state, 771, 0xffff); in dib8000_reset()
1056 dib8000_write_word(state, 772, 0xfffc); in dib8000_reset()
1057 dib8000_write_word(state, 898, 0x000c); /* restart sad */ in dib8000_reset()
1058 if (state->revision == 0x8090) in dib8000_reset()
1059 dib8000_write_word(state, 1280, 0x0045); in dib8000_reset()
1061 dib8000_write_word(state, 1280, 0x004d); in dib8000_reset()
1062 dib8000_write_word(state, 1281, 0x000c); in dib8000_reset()
1064 dib8000_write_word(state, 770, 0x0000); in dib8000_reset()
1065 dib8000_write_word(state, 771, 0x0000); in dib8000_reset()
1066 dib8000_write_word(state, 772, 0x0000); in dib8000_reset()
1067 dib8000_write_word(state, 898, 0x0004); // sad in dib8000_reset()
1068 dib8000_write_word(state, 1280, 0x0000); in dib8000_reset()
1069 dib8000_write_word(state, 1281, 0x0000); in dib8000_reset()
1072 if (state->revision != 0x8090) { in dib8000_reset()
1078 dib8000_write_word(state, 906, 0x2d98); in dib8000_reset()
1083 if (state->revision != 0x8090) in dib8000_reset()
1084 dib8000_write_word(state, 898, 0x0004); in dib8000_reset()
1086 if (dib8000_reset_gpio(state) != 0) in dib8000_reset()
1089 if ((state->revision != 0x8090) && in dib8000_reset()
1090 (dib8000_set_output_mode(fe, OUTMODE_HIGH_Z) != 0)) in dib8000_reset()
1096 /* P_iqc_ca2 = 0; P_iqc_impnc_on = 0; P_iqc_mode = 0; */ in dib8000_reset()
1097 if (state->cfg.pll->ifreq == 0) in dib8000_reset()
1098 dib8000_write_word(state, 40, 0x0755); /* P_iqc_corr_inh = 0 enable IQcorr block */ in dib8000_reset()
1100 dib8000_write_word(state, 40, 0x1f55); /* P_iqc_corr_inh = 1 disable IQcorr block */ in dib8000_reset()
1103 u16 l = 0, r; in dib8000_reset()
1117 state->isdbt_cfg_loaded = 0; in dib8000_reset()
1120 if ((state->revision != 8090) && (state->cfg.div_cfg != 0)) in dib8000_reset()
1130 if (state->revision != 0x8090) in dib8000_reset()
1134 dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); in dib8000_reset()
1140 return 0; in dib8000_reset()
1146 dib8000_write_word(state, 770, 0x0a00); in dib8000_restart_agc()
1147 dib8000_write_word(state, 770, 0x0000); in dib8000_restart_agc()
1158 if (state->cfg.update_lna(state->fe[0], dyn_gain)) { in dib8000_update_lna()
1163 return 0; in dib8000_update_lna()
1173 return 0; in dib8000_set_agc_config()
1176 for (i = 0; i < state->cfg.agc_config_count; i++) in dib8000_set_agc_config()
1183 dprintk("no valid AGC configuration found for band 0x%02x\n", band); in dib8000_set_agc_config()
1200 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib8000_set_agc_config()
1203 if (state->wbd_ref != 0) in dib8000_set_agc_config()
1208 if (state->revision == 0x8090) { in dib8000_set_agc_config()
1209 reg = dib8000_read_word(state, 922) & (0x3 << 2); in dib8000_set_agc_config()
1224 if (state->revision != 0x8090) in dib8000_set_agc_config()
1226 (dib8000_read_word(state, 923) & 0xffe3) | in dib8000_set_agc_config()
1229 return 0; in dib8000_set_agc_config()
1243 …e->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0) in dib8000_agc_soft_split()
1244 return 0; in dib8000_agc_soft_split()
1261 dib8000_write_word(state, 107, (dib8000_read_word(state, 107) & 0xff00) | split_offset); in dib8000_agc_soft_split()
1269 int ret = 0; in dib8000_agc_startup()
1271 u32 upd_demod_gain_period = 0x8000; in dib8000_agc_startup()
1277 if (state->revision != 0x8090) in dib8000_agc_startup()
1282 reg = dib8000_read_word(state, 1947)&0xff00; in dib8000_agc_startup()
1284 upd_demod_gain_period & 0xFFFF); in dib8000_agc_startup()
1287 ((upd_demod_gain_period >> 16) & 0xFF)); in dib8000_agc_startup()
1291 dib8000_write_word(state, 1920, (reg | 0x3) & in dib8000_agc_startup()
1295 …_config(state, (unsigned char)(BAND_OF_FREQUENCY(fe->dtv_property_cache.frequency / 1000))) != 0) { in dib8000_agc_startup()
1332 state->cfg.agc_control(fe, 0); in dib8000_agc_startup()
1348 drive &= 0x7; in dib8096p_host_bus_drive()
1352 ~(0x7 | (0x7 << 6) | (0x7 << 12)); in dib8096p_host_bus_drive()
1357 reg = dib8000_read_word(state, 1799) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1363 ~(0x7 | (0x7 << 6) | (0x7 << 12)); in dib8096p_host_bus_drive()
1368 reg = dib8000_read_word(state, 1801) & ~((0x7 << 2) | (0x7 << 8)); in dib8096p_host_bus_drive()
1374 ~(0x7 | (0x7 << 6) | (0x7 << 12)); in dib8096p_host_bus_drive()
1387 if ((syncFreq & ((1 << quantif) - 1)) != 0) in dib8096p_calcSyncFreq()
1392 if (syncFreq != 0) in dib8096p_calcSyncFreq()
1409 dib8000_write_word(state, 1609, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibTx()
1410 dib8000_write_word(state, 1610, syncWord & 0xffff); in dib8096p_cfg_DibTx()
1412 dib8000_write_word(state, 1615, 0); in dib8096p_cfg_DibTx()
1423 if ((P_Kin != 0) && (P_Kout != 0)) { in dib8096p_cfg_DibRx()
1433 dib8000_write_word(state, 1540, (syncWord >> 16) & 0xffff); in dib8096p_cfg_DibRx()
1434 dib8000_write_word(state, 1541, syncWord & 0xffff); in dib8096p_cfg_DibRx()
1437 dib8000_write_word(state, 1554, 0); in dib8096p_cfg_DibRx()
1450 case 0: in dib8096p_enMpegMux()
1465 dib8096p_enMpegMux(state, 0); in dib8096p_configMpegMux()
1469 enSerialClkDiv2 = 0; in dib8096p_configMpegMux()
1471 reg_1287 = ((pulseWidth & 0x1f) << 3) | in dib8096p_configMpegMux()
1472 ((enSerialMode & 0x1) << 2) | (enSerialClkDiv2 & 0x1); in dib8096p_configMpegMux()
1480 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 7); in dib8096p_setDibTxMux()
1485 dib8096p_cfg_DibTx(state, 8, 5, 0, 0, 0, 0); in dib8096p_setDibTxMux()
1489 dib8096p_cfg_DibTx(state, 5, 5, 0, 0, 0, 0); in dib8096p_setDibTxMux()
1493 dib8096p_cfg_DibTx(state, 20, 5, 10, 0, 0, 0); in dib8096p_setDibTxMux()
1503 u16 reg_1288 = dib8000_read_word(state, 1288) & ~(0x7 << 4); in dib8096p_setHostBusMux()
1508 dib8096p_enMpegMux(state, 0); in dib8096p_setHostBusMux()
1513 dib8096p_enMpegMux(state, 0); in dib8096p_setHostBusMux()
1532 case 0: /* only use the internal way - not the diversity input */ in dib8096p_set_diversity_in()
1536 dib8096p_cfg_DibRx(state, 8, 5, 0, 0, 0, 8, 0); in dib8096p_set_diversity_in()
1542 if ((reg_1287 & 0x1) == 1) { in dib8096p_set_diversity_in()
1543 /* force enSerialClkDiv2 = 0 */ in dib8096p_set_diversity_in()
1544 reg_1287 &= ~0x1; in dib8096p_set_diversity_in()
1552 dib8096p_cfg_DibRx(state, 5, 5, 0, 0, 0, 0, 0); in dib8096p_set_diversity_in()
1553 state->input_mode_mpeg = 0; in dib8096p_set_diversity_in()
1557 dib8000_set_diversity_in(state->fe[0], onoff); in dib8096p_set_diversity_in()
1558 return 0; in dib8096p_set_diversity_in()
1566 int ret = 0; in dib8096p_set_output_mode()
1572 smo_mode = (dib8000_read_word(state, 299) & 0x0050) | (1 << 1); in dib8096p_set_output_mode()
1574 ~((1 << 10) | (0x7 << 6) | (1 << 1)); in dib8096p_set_output_mode()
1578 outreg = 0; in dib8096p_set_output_mode()
1590 outreg |= (2 << 6) | (0 << 1); in dib8096p_set_output_mode()
1597 dib8096p_configMpegMux(state, 2, 0, 0); in dib8096p_set_output_mode()
1603 outreg |= (0 << 6); in dib8096p_set_output_mode()
1654 if (msg->buf[0] <= 15) in map_addr_to_serpar_number()
1655 msg->buf[0] -= 1; in map_addr_to_serpar_number()
1656 else if (msg->buf[0] == 17) in map_addr_to_serpar_number()
1657 msg->buf[0] = 15; in map_addr_to_serpar_number()
1658 else if (msg->buf[0] == 16) in map_addr_to_serpar_number()
1659 msg->buf[0] = 17; in map_addr_to_serpar_number()
1660 else if (msg->buf[0] == 19) in map_addr_to_serpar_number()
1661 msg->buf[0] = 16; in map_addr_to_serpar_number()
1662 else if (msg->buf[0] >= 21 && msg->buf[0] <= 25) in map_addr_to_serpar_number()
1663 msg->buf[0] -= 3; in map_addr_to_serpar_number()
1664 else if (msg->buf[0] == 28) in map_addr_to_serpar_number()
1665 msg->buf[0] = 23; in map_addr_to_serpar_number()
1666 else if (msg->buf[0] == 99) in map_addr_to_serpar_number()
1667 msg->buf[0] = 99; in map_addr_to_serpar_number()
1670 return 0; in map_addr_to_serpar_number()
1679 u16 serpar_num = msg[0].buf[0]; in dib8096p_tuner_write_serpar()
1682 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_write_serpar()
1684 if (i == 0) in dib8096p_tuner_write_serpar()
1687 dib8000_write_word(state, 1985, (1 << 6) | (serpar_num & 0x3f)); in dib8096p_tuner_write_serpar()
1688 dib8000_write_word(state, 1986, (msg[0].buf[1] << 8) | msg[0].buf[2]); in dib8096p_tuner_write_serpar()
1699 u16 serpar_num = msg[0].buf[0]; in dib8096p_tuner_read_serpar()
1703 n_overflow = (dib8000_read_word(state, 1984) >> 1) & 0x1; in dib8096p_tuner_read_serpar()
1705 if (i == 0) in dib8096p_tuner_read_serpar()
1708 dib8000_write_word(state, 1985, (0<<6) | (serpar_num&0x3f)); in dib8096p_tuner_read_serpar()
1712 n_empty = dib8000_read_word(state, 1984)&0x1; in dib8096p_tuner_read_serpar()
1714 if (i == 0) in dib8096p_tuner_read_serpar()
1719 msg[1].buf[0] = (read_word >> 8) & 0xff; in dib8096p_tuner_read_serpar()
1720 msg[1].buf[1] = (read_word) & 0xff; in dib8096p_tuner_read_serpar()
1728 if (map_addr_to_serpar_number(&msg[0]) == 0) { in dib8096p_tuner_rw_serpar()
1745 ((msg[0].buf[1] << 8) | (msg[0].buf[2]))); in dib8096p_rw_on_apb()
1748 msg[1].buf[0] = (word >> 8) & 0xff; in dib8096p_rw_on_apb()
1749 msg[1].buf[1] = (word) & 0xff; in dib8096p_rw_on_apb()
1758 u16 apb_address = 0, word; in dib8096p_tuner_xfer()
1759 int i = 0; in dib8096p_tuner_xfer()
1761 switch (msg[0].buf[0]) { in dib8096p_tuner_xfer()
1762 case 0x12: in dib8096p_tuner_xfer()
1765 case 0x14: in dib8096p_tuner_xfer()
1768 case 0x24: in dib8096p_tuner_xfer()
1771 case 0x1a: in dib8096p_tuner_xfer()
1774 case 0x22: in dib8096p_tuner_xfer()
1777 case 0x33: in dib8096p_tuner_xfer()
1780 case 0x34: in dib8096p_tuner_xfer()
1783 case 0x35: in dib8096p_tuner_xfer()
1786 case 0x36: in dib8096p_tuner_xfer()
1789 case 0x37: in dib8096p_tuner_xfer()
1792 case 0x38: in dib8096p_tuner_xfer()
1795 case 0x39: in dib8096p_tuner_xfer()
1798 case 0x2a: in dib8096p_tuner_xfer()
1801 case 0x2b: in dib8096p_tuner_xfer()
1804 case 0x2c: in dib8096p_tuner_xfer()
1807 case 0x2d: in dib8096p_tuner_xfer()
1810 case 0x2e: in dib8096p_tuner_xfer()
1813 case 0x2f: in dib8096p_tuner_xfer()
1816 case 0x30: in dib8096p_tuner_xfer()
1819 case 0x31: in dib8096p_tuner_xfer()
1822 case 0x32: in dib8096p_tuner_xfer()
1825 case 0x3e: in dib8096p_tuner_xfer()
1828 case 0x3f: in dib8096p_tuner_xfer()
1831 case 0x40: in dib8096p_tuner_xfer()
1834 case 0x25: in dib8096p_tuner_xfer()
1837 case 0x26: in dib8096p_tuner_xfer()
1840 case 0x27: in dib8096p_tuner_xfer()
1843 case 0x28: in dib8096p_tuner_xfer()
1846 case 0x1d: in dib8096p_tuner_xfer()
1848 i = ((dib8000_read_word(state, 921) >> 12)&0x3); in dib8096p_tuner_xfer()
1850 msg[1].buf[0] = (word >> 8) & 0xff; in dib8096p_tuner_xfer()
1851 msg[1].buf[1] = (word) & 0xff; in dib8096p_tuner_xfer()
1853 case 0x1f: in dib8096p_tuner_xfer()
1855 word = (u16) ((msg[0].buf[1] << 8) | in dib8096p_tuner_xfer()
1856 msg[0].buf[2]); in dib8096p_tuner_xfer()
1857 /* in the VGAMODE Sel are located on bit 0/1 */ in dib8096p_tuner_xfer()
1858 word &= 0x3; in dib8096p_tuner_xfer()
1867 if (apb_address != 0) /* R/W access via APB */ in dib8096p_tuner_xfer()
1872 return 0; in dib8096p_tuner_xfer()
1901 if (en_cur_state > 0xff) in dib8096p_tuner_sleep()
1905 en_cur_state &= 0x00ff; in dib8096p_tuner_sleep()
1907 if (state->tuner_enable != 0) in dib8096p_tuner_sleep()
1913 return 0; in dib8096p_tuner_sleep()
1924 u32 ix = 0, tmp_val = 0, exp = 0, mant = 0; in dib8000_get_adc_power()
1943 int val = 0; in dib8090p_get_dc_power()
1949 case 0: in dib8090p_get_dc_power()
1953 if (val & 0x200) in dib8090p_get_dc_power()
1964 dib8000_write_word(state, 30, (u16) (timf & 0xffff)); in dib8000_update_timf()
1982 dib8000_set_bandwidth(state->fe[0], 6000); in dib8000_ctrl_timf()
1991 static const u8 permu_seg[] = { 6, 5, 7, 4, 8, 3, 9, 2, 10, 1, 11, 0, 12 };
1996 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_layer()
2000 constellation = 0; in dib8000_set_layer()
2035 time_intlv = 0; in dib8000_set_layer()
2037 …ayer_index, (constellation << 10) | ((c->layer[layer_index].segment_count & 0xf) << 6) | (cr << 3)… in dib8000_set_layer()
2038 if (c->layer[layer_index].segment_count > 0) { in dib8000_set_layer()
2055 static const u16 adp_Q64[4] = {0x0148, 0xfff0, 0x00a4, 0xfff8}; /* P_adp_regul_cnt 0.04, P_adp_nois…
2056 static const u16 adp_Q16[4] = {0x023d, 0xffdf, 0x00a4, 0xfff0}; /* P_adp_regul_cnt 0.07, P_adp_nois…
2057 static const u16 adp_Qdefault[4] = {0x099a, 0xffae, 0x0333, 0xfff8}; /* P_adp_regul_cnt 0.3, P_adp…
2060 u16 i, ana_gain = 0; in dib8000_adp_fine_tune()
2066 ana_gain = 0x7; in dib8000_adp_fine_tune()
2067 adp = &adp_Q64[0]; in dib8000_adp_fine_tune()
2070 ana_gain = 0x7; in dib8000_adp_fine_tune()
2071 adp = &adp_Q16[0]; in dib8000_adp_fine_tune()
2074 ana_gain = 0; in dib8000_adp_fine_tune()
2075 adp = &adp_Qdefault[0]; in dib8000_adp_fine_tune()
2079 for (i = 0; i < 4; i++) in dib8000_adp_fine_tune()
2093 for (i = 0; i < 10; i++) in dib8000_update_ana_gain()
2095 } else { /* set -22dB ADC target for ana_gain=0 */ in dib8000_update_ana_gain()
2096 for (i = 0; i < 10; i++) in dib8000_update_ana_gain()
2103 u16 mode = 0; in dib8000_load_ana_fe_coefs()
2105 if (state->isdbt_cfg_loaded == 0) in dib8000_load_ana_fe_coefs()
2106 for (mode = 0; mode < 24; mode++) in dib8000_load_ana_fe_coefs()
2111 0x423, 0x009, 0x5C7,
2112 0x7A6, 0x3D8, 0x527,
2113 0x7FF, 0x79B, 0x3D6,
2114 0x3A2, 0x53B, 0x2F4,
2115 0x213
2119 0x208, 0x0C3, 0x7B9,
2120 0x423, 0x5C7, 0x3D8,
2121 0x7FF, 0x3D6, 0x53B,
2122 0x213, 0x029, 0x0D0,
2123 0x48E
2127 0x740, 0x069, 0x7DD,
2128 0x208, 0x7B9, 0x5C7,
2129 0x7FF, 0x53B, 0x029,
2130 0x48E, 0x4C4, 0x367,
2131 0x684
2136 int sub_channel_prbs_group = 0; in dib8000_get_init_prbs()
2141 return 0; in dib8000_get_init_prbs()
2143 switch (state->fe[0]->dtv_property_cache.transmission_mode) { in dib8000_get_init_prbs()
2155 dprintk("sub_channel_prbs_group = %d , subchannel =%d prbs = 0x%04x\n", in dib8000_get_init_prbs()
2164 u16 coff_pow = 0x2800; in dib8000_set_13seg_channel()
2166 state->seg_mask = 0x1fff; /* All 13 segments enabled */ in dib8000_set_13seg_channel()
2169 …if (state->isdbt_cfg_loaded == 0) { /* if not Sound Broadcasting mode : put default values for 13… in dib8000_set_13seg_channel()
2171 dib8000_write_word(state, 187, (4 << 12) | (8 << 5) | 0x2); in dib8000_set_13seg_channel()
2172 coff_pow = 0x2800; in dib8000_set_13seg_channel()
2173 for (i = 0; i < 6; i++) in dib8000_set_13seg_channel()
2177 …/* P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_freq_step = 3, P_pre_freq_win_len… in dib8000_set_13seg_channel()
2178 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (3 << 5) | 1); in dib8000_set_13seg_channel()
2181 dib8000_write_word(state, 340, (8 << 6) | (6 << 0)); in dib8000_set_13seg_channel()
2183 dib8000_write_word(state, 341, (4 << 3) | (1 << 2) | (1 << 1) | (1 << 0)); in dib8000_set_13seg_channel()
2185 dib8000_write_word(state, 228, 0); /* default value */ in dib8000_set_13seg_channel()
2187 dib8000_write_word(state, 205, 0x200f); /* init value */ in dib8000_set_13seg_channel()
2195 if (state->cfg.pll->ifreq == 0) in dib8000_set_13seg_channel()
2196 …dib8000_write_word(state, 266, ~state->seg_mask | state->seg_diff_mask | 0x40); /* P_equal_noise_s… in dib8000_set_13seg_channel()
2206 dib8000_write_word(state, 1, (init_prbs << 2) | (reg_1 & 0x3)); /* ADDR 1 */ in dib8000_set_subchannel_prbs()
2213 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_small_fine_tune()
2225 if (c->isdbt_partial_reception == 0) { /* 1-seg */ in dib8000_small_fine_tune()
2226 if (c->layer[0].modulation == DQPSK) /* DQPSK */ in dib8000_small_fine_tune()
2231 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ in dib8000_small_fine_tune()
2245 if (c->isdbt_partial_reception == 0) { /* 1-seg */ in dib8000_small_fine_tune()
2246 if (c->layer[0].modulation == DQPSK) /* DQPSK */ in dib8000_small_fine_tune()
2251 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ in dib8000_small_fine_tune()
2267 if (c->isdbt_partial_reception == 0) { /* 1-seg */ in dib8000_small_fine_tune()
2268 if (c->layer[0].modulation == DQPSK) /* DQPSK */ in dib8000_small_fine_tune()
2273 if (c->layer[0].modulation == DQPSK) { /* DQPSK on central segment */ in dib8000_small_fine_tune()
2288 for (i = 0; i < 8; i++) in dib8000_small_fine_tune()
2297 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_sb_channel()
2302 dib8000_write_word(state, 219, dib8000_read_word(state, 219) | 0x1); /* adp_pass =1 */ in dib8000_set_sb_channel()
2303 …dib8000_write_word(state, 190, dib8000_read_word(state, 190) | (0x1 << 14)); /* pha3_force_pha_shi… in dib8000_set_sb_channel()
2305 dib8000_write_word(state, 219, dib8000_read_word(state, 219) & 0xfffe); /* adp_pass =0 */ in dib8000_set_sb_channel()
2306 …8000_write_word(state, 190, dib8000_read_word(state, 190) & 0xbfff); /* pha3_force_pha_shift = 0 */ in dib8000_set_sb_channel()
2310 state->seg_mask = 0x00E0; in dib8000_set_sb_channel()
2312 state->seg_mask = 0x0040; in dib8000_set_sb_channel()
2314 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_sb_channel()
2317 …/* P_coff_cpil_alpha=4, P_coff_inh=0, P_coff_cpil_winlen=64, P_coff_narrow_band=1, P_coff_square_v… in dib8000_set_sb_channel()
2318 …write_word(state, 187, (4 << 12) | (0 << 11) | (63 << 5) | (0x3 << 3) | ((~c->isdbt_partial_recept… in dib8000_set_sb_channel()
2320 …dib8000_write_word(state, 340, (16 << 6) | (8 << 0)); /* P_ctrl_pre_freq_win_len=16, P_ctrl_pre_fr… in dib8000_set_sb_channel()
2321 …dib8000_write_word(state, 341, (6 << 3) | (1 << 2) | (1 << 1) | (1 << 0));/* P_ctrl_pre_freq_thres… in dib8000_set_sb_channel()
2324 if (c->isdbt_partial_reception == 0) { in dib8000_set_sb_channel()
2327 dib8000_write_word(state, 180, 0x1fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2329 dib8000_write_word(state, 180, 0x0fcf | ((state->mode - 1) << 14)); in dib8000_set_sb_channel()
2331 …/* P_ctrl_corm_thres4pre_freq_inh=1,P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_pre_… in dib8000_set_sb_channel()
2332 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (5 << 5) | 4); in dib8000_set_sb_channel()
2333 coff = &coff_thres_1seg[0]; in dib8000_set_sb_channel()
2335 dib8000_write_word(state, 180, 0x1fcf | (1 << 14)); in dib8000_set_sb_channel()
2336 …/* P_ctrl_corm_thres4pre_freq_inh = 1, P_ctrl_pre_freq_mode_sat=1, P_ctrl_pre_freq_inh=0, P_ctrl_p… in dib8000_set_sb_channel()
2337 dib8000_write_word(state, 338, (1 << 12) | (1 << 10) | (0 << 9) | (4 << 5) | 4); in dib8000_set_sb_channel()
2338 coff = &coff_thres_3seg[0]; in dib8000_set_sb_channel()
2342 dib8000_write_word(state, 205, dib8000_read_word(state, 205) & 0xfff0); /* P_cspu_win_cut = 0 */ in dib8000_set_sb_channel()
2344 if (c->isdbt_partial_reception == 0 && c->transmission_mode == TRANSMISSION_MODE_2K) in dib8000_set_sb_channel()
2348 for (i = 0 ; i < 3; i++) { in dib8000_set_sb_channel()
2360 if (c->isdbt_partial_reception == 0) in dib8000_set_sb_channel()
2368 u16 p_cfr_left_edge = 0, p_cfr_right_edge = 0; in dib8000_set_isdbt_common_channel()
2369 u16 tmcc_pow = 0, ana_gain = 0, tmp = 0, i = 0, nbseg_diff = 0 ; in dib8000_set_isdbt_common_channel()
2372 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_isdbt_common_channel()
2385 dib8000_write_word(state, 1, (tmp&0xfffc) | (c->guard_interval & 0x3)); in dib8000_set_isdbt_common_channel()
2387 …dib8000_write_word(state, 274, (dib8000_read_word(state, 274) & 0xffcf) | ((c->isdbt_partial_recep… in dib8000_set_isdbt_common_channel()
2391 state->seg_diff_mask = (c->layer[0].modulation == DQPSK) << permu_seg[0]; in dib8000_set_isdbt_common_channel()
2394 for (i = 0; i < nbseg_diff; i++) in dib8000_set_isdbt_common_channel()
2397 for (i = 0; i < 3; i++) in dib8000_set_isdbt_common_channel()
2399 for (i = 0; i < nbseg_diff; i++) in dib8000_set_isdbt_common_channel()
2404 dib8000_write_word(state, 268, (dib8000_read_word(state, 268) & 0xF9FF) | 0x0200); in dib8000_set_isdbt_common_channel()
2408 for (i = 0; i < 3; i++) in dib8000_set_isdbt_common_channel()
2410 if (autosearching == 0) { in dib8000_set_isdbt_common_channel()
2416 dib8000_write_word(state, 0, (state->mode << 13) | state->seg_diff_mask); in dib8000_set_isdbt_common_channel()
2418 state->differential_constellation = (state->seg_diff_mask != 0); in dib8000_set_isdbt_common_channel()
2439 init_prbs = 0xfff; in dib8000_set_isdbt_common_channel()
2448 for (i = 0; i < 13; i++) { in dib8000_set_isdbt_common_channel()
2450 …p_cfr_left_edge += (1 << i) * ((i == 0) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i -… in dib8000_set_isdbt_common_channel()
2451 …+= (1 << i) * ((i == 12) || ((((state->seg_mask & (~state->seg_diff_mask)) >> (i + 1)) & 1) == 0)); in dib8000_set_isdbt_common_channel()
2463 …dib8000_write_word(state, 288, (~state->seg_mask | state->seg_diff_mask) & 0x1fff); /* P_tmcc_seg_… in dib8000_set_isdbt_common_channel()
2465 …dib8000_write_word(state, 288, 0x1fff); /*disable equalisation of the tmcc when autosearch to be a… in dib8000_set_isdbt_common_channel()
2468 dib8000_write_word(state, 287, ~state->seg_mask | 0x1000); /* P_tmcc_seg_inh */ in dib8000_set_isdbt_common_channel()
2473 for (i = 0; i < 3; i++) in dib8000_set_isdbt_common_channel()
2476 /* Quantif of "P_tmcc_dec_thres_?k" is (0, 5+mode, 9); */ in dib8000_set_isdbt_common_channel()
2482 /*dib8000_write_word(state, 287, (1 << 13) | 0x1000 ); */ in dib8000_set_isdbt_common_channel()
2485 if (state->isdbt_cfg_loaded == 0) in dib8000_set_isdbt_common_channel()
2488 state->isdbt_cfg_loaded = 0; in dib8000_set_isdbt_common_channel()
2494 u32 value = 0; /* P_search_end0 wait time */ in dib8000_wait_lock()
2499 if (state->revision == 0x8090) in dib8000_wait_lock()
2507 dib8000_write_word(state, reg, (u16)((value >> 16) & 0xffff)); in dib8000_wait_lock()
2508 dib8000_write_word(state, (reg + 1), (u16)(value & 0xffff)); in dib8000_wait_lock()
2516 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_autosearch_start()
2517 u8 slist = 0; in dib8000_autosearch_start()
2520 if (state->revision == 0x8090) in dib8000_autosearch_start()
2523 if ((state->revision >= 0x8002) && in dib8000_autosearch_start()
2525 dib8000_write_word(state, 37, 0x0065); /* P_ctrl_pha_off_max default values */ in dib8000_autosearch_start()
2526 dib8000_write_word(state, 116, 0x0000); /* P_ana_gain to 0 */ in dib8000_autosearch_start()
2528 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x1fff) | (0 << 13) | (1 << 15)); /* P… in dib8000_autosearch_start()
2529 dib8000_write_word(state, 1, (dib8000_read_word(state, 1) & 0xfffc) | 0); /* P_guard = 0 */ in dib8000_autosearch_start()
2530 dib8000_write_word(state, 6, 0); /* P_lock0_mask = 0 */ in dib8000_autosearch_start()
2531 dib8000_write_word(state, 7, 0); /* P_lock1_mask = 0 */ in dib8000_autosearch_start()
2532 dib8000_write_word(state, 8, 0); /* P_lock2_mask = 0 */ in dib8000_autosearch_start()
2533 …te, 10, (dib8000_read_word(state, 10) & 0x200) | (16 << 4) | (0 << 0)); /* P_search_list=16, P_sea… in dib8000_autosearch_start()
2535 if (state->revision == 0x8090) in dib8000_autosearch_start()
2540 dib8000_write_word(state, 17, 0); in dib8000_autosearch_start()
2542 dib8000_write_word(state, 19, 0); in dib8000_autosearch_start()
2544 dib8000_write_word(state, 21, (value >> 16) & 0xffff); /* P_search_checkst */ in dib8000_autosearch_start()
2545 dib8000_write_word(state, 22, value & 0xffff); in dib8000_autosearch_start()
2547 if (state->revision == 0x8090) in dib8000_autosearch_start()
2548 …0_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (0 << 8)); /* P_corm_alpha = 0 */ in dib8000_autosearch_start()
2550 …dib8000_write_word(state, 32, (dib8000_read_word(state, 32) & 0xf0ff) | (9 << 8)); /* P_corm_alpha… in dib8000_autosearch_start()
2554 dib8000_write_word(state, 356, 0); in dib8000_autosearch_start()
2555 dib8000_write_word(state, 357, 0x111); in dib8000_autosearch_start()
2557 …dib8000_write_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (1 << 13)); /* P_restart… in dib8000_autosearch_start()
2558 …rite_word(state, 770, (dib8000_read_word(state, 770) & 0xdfff) | (0 << 13)); /* P_restart_ccg = 0 … in dib8000_autosearch_start()
2559 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x7ff) | (0 << 15) | (1 << 13)); /* P_… in dib8000_autosearch_start()
2560 } else if ((state->revision >= 0x8002) && in dib8000_autosearch_start()
2564 c->inversion = 0; in dib8000_autosearch_start()
2565 c->layer[0].modulation = QAM_64; in dib8000_autosearch_start()
2566 c->layer[0].fec = FEC_2_3; in dib8000_autosearch_start()
2567 c->layer[0].interleaving = 0; in dib8000_autosearch_start()
2568 c->layer[0].segment_count = 13; in dib8000_autosearch_start()
2576 dib8000_write_word(state, 6, 0x4); in dib8000_autosearch_start()
2577 if (state->revision == 0x8090) in dib8000_autosearch_start()
2580 dib8000_write_word(state, 7, 0x8); in dib8000_autosearch_start()
2581 dib8000_write_word(state, 8, 0x1000); in dib8000_autosearch_start()
2584 if (state->revision == 0x8090) in dib8000_autosearch_start()
2591 /* P_search_param_select = 0xf; look for the 4 different guard intervals */ in dib8000_autosearch_start()
2592 dib8000_write_word(state, 356, 0); in dib8000_autosearch_start()
2593 dib8000_write_word(state, 357, 0xf); in dib8000_autosearch_start()
2595 value = dib8000_read_word(state, 0); in dib8000_autosearch_start()
2596 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); in dib8000_autosearch_start()
2598 dib8000_write_word(state, 0, (u16)value); in dib8000_autosearch_start()
2600 c->inversion = 0; in dib8000_autosearch_start()
2601 c->layer[0].modulation = QAM_64; in dib8000_autosearch_start()
2602 c->layer[0].fec = FEC_2_3; in dib8000_autosearch_start()
2603 c->layer[0].interleaving = 0; in dib8000_autosearch_start()
2604 c->layer[0].segment_count = 13; in dib8000_autosearch_start()
2606 c->layer[0].segment_count = 13; in dib8000_autosearch_start()
2611 dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); in dib8000_autosearch_start()
2618 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 t… in dib8000_autosearch_start()
2627 …dib8000_write_word(state, 0, (dib8000_read_word(state, 0) & 0x9fff) | (1 << 13)); /* P_mode = 1 */ in dib8000_autosearch_start()
2629 slist = 0; in dib8000_autosearch_start()
2637 dib8000_write_word(state, 6, 0x4); in dib8000_autosearch_start()
2638 if (state->revision == 0x8090) in dib8000_autosearch_start()
2641 dib8000_write_word(state, 7, 0x8); in dib8000_autosearch_start()
2642 dib8000_write_word(state, 8, 0x1000); in dib8000_autosearch_start()
2645 if (state->revision == 0x8090) in dib8000_autosearch_start()
2650 value = dib8000_read_word(state, 0); in dib8000_autosearch_start()
2651 dib8000_write_word(state, 0, (u16)((1 << 15) | value)); in dib8000_autosearch_start()
2653 dib8000_write_word(state, 0, (u16)value); in dib8000_autosearch_start()
2655 return 0; in dib8000_autosearch_start()
2663 if ((state->revision >= 0x8002) && in dib8000_autosearch_irq()
2665 if (irq_pending & 0x1) { in dib8000_autosearch_irq()
2670 if (irq_pending & 0x1) { /* failed */ in dib8000_autosearch_irq()
2675 if (irq_pending & 0x2) { /* succeeded */ in dib8000_autosearch_irq()
2681 return 0; // still pending in dib8000_autosearch_irq()
2690 dib8000_write_word(state, 771, tmp & 0xfffd); in dib8000_viterbi_state()
2699 u32 dds = state->cfg.pll->ifreq & 0x1ffffff; in dib8000_set_dds()
2703 if (state->revision == 0x8090) { in dib8000_set_dds()
2706 if (offset_khz < 0) in dib8000_set_dds()
2717 if (offset_khz < 0) in dib8000_set_dds()
2732 dib8000_write_word(state, 27, (u16)(dds >> 16) & 0x1ff); in dib8000_set_dds()
2733 dib8000_write_word(state, 28, (u16)(dds & 0xffff)); in dib8000_set_dds()
2739 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_frequency_offset()
2744 if (state->fe[0]->ops.tuner_ops.get_frequency) in dib8000_set_frequency_offset()
2745 state->fe[0]->ops.tuner_ops.get_frequency(state->fe[0], ¤t_rf); in dib8000_set_frequency_offset()
2757 if (state->cfg.pll->ifreq == 0) { /* low if tuner */ in dib8000_set_frequency_offset()
2758 if ((c->inversion ^ i) == 0) in dib8000_set_frequency_offset()
2761 if ((c->inversion ^ i) == 0) in dib8000_set_frequency_offset()
2776 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_symbol_duration()
2781 i = 0; in dib8000_get_symbol_duration()
2798 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_isdbt_loop_params()
2799 u16 reg_32 = 0, reg_37 = 0; in dib8000_set_isdbt_loop_params()
2804 if (c->isdbt_partial_reception == 0) { in dib8000_set_isdbt_loop_params()
2805 … = ((11 - state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (11-P_mode), P_corm_alpha=6, P_… in dib8000_set_isdbt_loop_params()
2806 …reg_37 = (3 << 5) | (0 << 4) | (10 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 … in dib8000_set_isdbt_loop_params()
2808 … = ((10 - state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (10-P_mode), P_corm_alpha=6, P_… in dib8000_set_isdbt_loop_params()
2809 …reg_37 = (3 << 5) | (0 << 4) | (9 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P… in dib8000_set_isdbt_loop_params()
2812 …32 = ((9 - state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = (9-P_mode, P_corm_alpha=6, P_c… in dib8000_set_isdbt_loop_params()
2813 …reg_37 = (3 << 5) | (0 << 4) | (8 - state->mode); /* P_ctrl_pha_off_max=3 P_ctrl_sfreq_inh =0 P… in dib8000_set_isdbt_loop_params()
2818 if (c->isdbt_partial_reception == 0) { /* Sound Broadcasting mode 1 seg */ in dib8000_set_isdbt_loop_params()
2819 …2 = ((13-state->mode) << 12) | (6 << 8) | 0x40; /* P_timf_alpha = (13-P_mode) , P_corm_alpha=6, P_… in dib8000_set_isdbt_loop_params()
2822 …2 = ((12-state->mode) << 12) | (6 << 8) | 0x60; /* P_timf_alpha = (12-P_mode) , P_corm_alpha=6, P_… in dib8000_set_isdbt_loop_params()
2826 …reg_32 = ((11-state->mode) << 12) | (6 << 8) | 0x80; /* P_timf_alpha = 8 , P_corm_alpha=6, P_corm_… in dib8000_set_isdbt_loop_params()
2837 dib8000_write_word(state, 770, 0x4000); in dib8000_demod_restart()
2838 dib8000_write_word(state, 770, 0x0000); in dib8000_demod_restart()
2844 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_sync_wait()
2861 if (state->cfg.diversity_delay == 0) in dib8000_set_sync_wait()
2866 dib8000_write_word(state, 273, (dib8000_read_word(state, 273) & 0x000f) | (sync_wait << 4)); in dib8000_set_sync_wait()
2894 return 0; in dib8000_set_tune_state()
2903 return 0; in dib8000_tune_restart_from_demod()
2910 if (state->revision == 0x8090) in dib8000_read_lock()
2917 u16 reg = 0; in dib8090p_init_sdram()
2920 reg = dib8000_read_word(state, 274) & 0xfff0; in dib8090p_init_sdram()
2921 dib8000_write_word(state, 274, reg | 0x7); /* P_dintlv_delay_ram = 7 because of MobileSdram */ in dib8090p_init_sdram()
2929 return 0; in dib8090p_init_sdram()
2949 int i, n_segs = 0; in is_manual_mode()
2953 return 0; in is_manual_mode()
2960 return 0; in is_manual_mode()
2968 return 0; in is_manual_mode()
2977 return 0; in is_manual_mode()
2982 * disable a layer if segment count is 0 or invalid. in is_manual_mode()
2984 for (i = 0; i < 3; i++) { in is_manual_mode()
2989 (c->layer[i].segment_count == 0)) { in is_manual_mode()
3000 return 0; in is_manual_mode()
3008 if (n_segs == 0 || n_segs > 13) { in is_manual_mode()
3010 return 0; in is_manual_mode()
3020 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_tune()
3023 u16 locks, deeper_interleaver = 0, i; in dib8000_tune()
3033 u32 corm[4] = {0, 0, 0, 0}; in dib8000_tune()
3036 #if 0 in dib8000_tune()
3046 if (state->revision == 0x8090) in dib8000_tune()
3054 dib8000_viterbi_state(state, 0); /* force chan dec in restart */ in dib8000_tune()
3057 dib8000_write_word(state, 285, dib8000_read_word(state, 285) & 0x60); in dib8000_tune()
3062 if (state->channel_parameters_set == 0) { /* The channel struct is unknown, search it ! */ in dib8000_tune()
3064 if (state->revision != 0x8090) { in dib8000_tune()
3090 if (state->revision == 0x8090) in dib8000_tune()
3122 if (state->revision == 0x8090) { in dib8000_tune()
3125 corm[0] = (dib8000_read_word(state, 600) << 16) | (dib8000_read_word(state, 601)); in dib8000_tune()
3129 corm[0] = (dib8000_read_word(state, 598) << 16) | (dib8000_read_word(state, 599)); in dib8000_tune()
3131 /* dprintk("corm fft: %u %u %u\n", corm[0], corm[1], corm[2]); */ in dib8000_tune()
3133 max_value = 0; in dib8000_tune()
3140 case 0: in dib8000_tune()
3155 if (state->revision == 0x8090) in dib8000_tune()
3162 if (state->revision == 0x8090) in dib8000_tune()
3163 state->found_guard = dib8000_read_word(state, 572) & 0x3; in dib8000_tune()
3165 state->found_guard = dib8000_read_word(state, 570) & 0x3; in dib8000_tune()
3181 dib8000_set_isdbt_common_channel(state, 0, 0);/* setting the known channel parameters here */ in dib8000_tune()
3189 dib8000_set_diversity_in(state->fe[0], state->diversity_onoff); in dib8000_tune()
3191 locks = (dib8000_read_word(state, 180) >> 6) & 0x3f; /* P_coff_winlen ? */ in dib8000_tune()
3199 if (locks & (0x3 << 11)) { /* coff-lock and off_cpil_lock achieved */ in dib8000_tune()
3203 …*timeout = dib8000_get_timeout(state, (20 * ((dib8000_read_word(state, 188)>>5)&0x1f)), SYMBOL_DEP… in dib8000_tune()
3249 state->subchannel = 0; in dib8000_tune()
3258 …if ((state->revision == 0x8090) || ((dib8000_read_word(state, 1291) >> 9) & 0x1)) { /* fe capable … in dib8000_tune()
3260 for (i = 0; i < 3; i++) { in dib8000_tune()
3263 if (c->layer[i].segment_count > 0) { /* valid layer */ in dib8000_tune()
3264 deeper_interleaver = c->layer[0].interleaving; in dib8000_tune()
3270 if (deeper_interleaver == 0) in dib8000_tune()
3277 if (state->diversity_onoff != 0) /* because of diversity sync */ in dib8000_tune()
3293 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3294 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3295 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); in dib8000_tune()
3311 if (locks & (0x7 << 5)) { in dib8000_tune()
3314 c->layer[0].segment_count ? (locks >> 7) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3315 c->layer[1].segment_count ? (locks >> 6) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled", in dib8000_tune()
3316 c->layer[2].segment_count ? (locks >> 5) & 0x1 ? "locked" : "NOT LOCKED" : "not enabled"); in dib8000_tune()
3346 if ((state->revision != 0x8090) && (state->agc1_max != 0)) { in dib8000_tune()
3351 state->agc1_max = 0; in dib8000_tune()
3352 state->agc1_min = 0; in dib8000_tune()
3353 state->agc2_max = 0; in dib8000_tune()
3354 state->agc2_min = 0; in dib8000_tune()
3357 ret = 0; in dib8000_tune()
3363 if ((ret > 0) && (*tune_state > CT_DEMOD_STEP_3)) in dib8000_tune()
3365 if ((ret > 0) && (ret < state->symbol_duration)) in dib8000_tune()
3378 if (dib8000_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) in dib8000_wakeup()
3381 if (state->revision == 0x8090) in dib8000_wakeup()
3386 if (ret < 0) in dib8000_wakeup()
3390 return 0; in dib8000_wakeup()
3401 if (ret < 0) in dib8000_sleep()
3405 if (state->revision != 0x8090) in dib8000_sleep()
3417 u16 i, val = 0; in dib8000_get_frontend()
3418 enum fe_status stat = 0; in dib8000_get_frontend()
3426 * So, let's just return if frontend 0 has not locked. in dib8000_get_frontend()
3430 return 0; in dib8000_get_frontend()
3439 …for (sub_index_frontend = 0; (sub_index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[sub_inde… in dib8000_get_frontend()
3446 for (i = 0; i < 3; i++) { in dib8000_get_frontend()
3454 return 0; in dib8000_get_frontend()
3458 c->isdbt_sb_mode = dib8000_read_word(state, 508) & 0x1; in dib8000_get_frontend()
3460 if (state->revision == 0x8090) in dib8000_get_frontend()
3464 c->inversion = (val & 0x40) >> 6; in dib8000_get_frontend()
3465 switch ((val & 0x30) >> 4) { in dib8000_get_frontend()
3481 switch (val & 0x3) { in dib8000_get_frontend()
3482 case 0: in dib8000_get_frontend()
3504 for (i = 0; i < 3; i++) { in dib8000_get_frontend()
3507 val = dib8000_read_word(state, 493 + i) & 0x0f; in dib8000_get_frontend()
3510 if (val == 0 || val > 13) in dib8000_get_frontend()
3511 show = 0; in dib8000_get_frontend()
3519 val = dib8000_read_word(state, 499 + i) & 0x3; in dib8000_get_frontend()
3520 /* Interleaving can be 0, 1, 2 or 4 */ in dib8000_get_frontend()
3529 switch (val & 0x7) { in dib8000_get_frontend()
3558 switch (val & 0x3) { in dib8000_get_frontend()
3559 case 0: in dib8000_get_frontend()
3590 for (i = 0; i < 3; i++) { in dib8000_get_frontend()
3597 return 0; in dib8000_get_frontend()
3603 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_set_frontend()
3604 int l, i, active, time, time_slave = 0; in dib8000_set_frontend()
3608 if (c->frequency == 0) { in dib8000_set_frontend()
3610 return 0; in dib8000_set_frontend()
3613 if (c->bandwidth_hz == 0) { in dib8000_set_frontend()
3618 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3624 if (state->revision != 0x8090) { in dib8000_set_frontend()
3626 if (index_frontend != 0) in dib8000_set_frontend()
3630 dib8000_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); in dib8000_set_frontend()
3633 if (index_frontend != 0) in dib8000_set_frontend()
3637 dib8096p_set_output_mode(state->fe[0], OUTMODE_HIGH_Z); in dib8000_set_frontend()
3648 if (state->revision != 0x8090) in dib8000_set_frontend()
3649 dib8000_set_diversity_in(state->fe[index_frontend - 1], 0); in dib8000_set_frontend()
3651 dib8096p_set_diversity_in(state->fe[index_frontend - 1], 0); in dib8000_set_frontend()
3655 time = dib8000_agc_startup(state->fe[0]); in dib8000_set_frontend()
3658 if (time == 0) in dib8000_set_frontend()
3660 else if ((time_slave != 0) && (time_slave > time)) in dib8000_set_frontend()
3663 if (time == 0) in dib8000_set_frontend()
3677 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3679 exit_condition = 0; in dib8000_set_frontend()
3683 } while (exit_condition == 0); in dib8000_set_frontend()
3685 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3690 callback_time = 0; in dib8000_set_frontend()
3691 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3693 if (delay != 0) { in dib8000_set_frontend()
3700 if (state->channel_parameters_set == 0) { /* searching */ in dib8000_set_frontend()
3706 for (l = 0; (l < MAX_NUMBER_OF_FRONTENDS) && (state->fe[l] != NULL); l++) { in dib8000_set_frontend()
3716 for (i = 0; i < 3; i++) { in dib8000_set_frontend()
3729 if (dib8000_get_status(state->fe[0]) == FE_STATUS_TUNE_FAILED || in dib8000_set_frontend()
3730 dib8000_get_status(state->fe[0]) == FE_STATUS_LOCKED || in dib8000_set_frontend()
3731 dib8000_get_status(state->fe[0]) == FE_STATUS_DATA_LOCKED) { in dib8000_set_frontend()
3732 active = 0; in dib8000_set_frontend()
3734 …for (index_frontend = 0; (index_frontend < MAX_NUMBER_OF_FRONTENDS) && (state->fe[index_frontend] … in dib8000_set_frontend()
3738 if (active == 0) in dib8000_set_frontend()
3739 dprintk("tuning done with status %d\n", dib8000_get_status(state->fe[0])); in dib8000_set_frontend()
3742 if ((active == 1) && (callback_time == 0)) { in dib8000_set_frontend()
3744 active = 0; in dib8000_set_frontend()
3752 if (state->revision != 0x8090) in dib8000_set_frontend()
3753 dib8000_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3755 dib8096p_set_output_mode(state->fe[0], state->cfg.output_mode); in dib8000_set_frontend()
3756 if (state->cfg.enMpegOutput == 0) { in dib8000_set_frontend()
3762 return 0; in dib8000_set_frontend()
3770 u16 lock_slave = 0, lock; in dib8000_read_status()
3777 *stat = 0; in dib8000_read_status()
3785 if ((((lock >> 1) & 0xf) == 0xf) || (((lock_slave >> 1) & 0xf) == 0xf)) /* TMCC_SYNC */ in dib8000_read_status()
3793 if (lock & 0x01) in dib8000_read_status()
3797 if (lock & 0x01) in dib8000_read_status()
3801 if (lock & 0x01) in dib8000_read_status()
3806 return 0; in dib8000_read_status()
3814 if (state->revision == 0x8090) in dib8000_read_ber()
3820 return 0; in dib8000_read_ber()
3828 if (state->revision == 0x8090) in dib8000_read_unc_blocks()
3832 return 0; in dib8000_read_unc_blocks()
3841 *strength = 0; in dib8000_read_signal_strength()
3855 return 0; in dib8000_read_signal_strength()
3864 if (state->revision != 0x8090) in dib8000_get_snr()
3868 n = (val >> 6) & 0xff; in dib8000_get_snr()
3869 exp = (val & 0x3f); in dib8000_get_snr()
3870 if ((exp & 0x20) != 0) in dib8000_get_snr()
3871 exp -= 0x40; in dib8000_get_snr()
3874 if (state->revision != 0x8090) in dib8000_get_snr()
3878 s = (val >> 6) & 0xff; in dib8000_get_snr()
3879 exp = (val & 0x3f); in dib8000_get_snr()
3880 if ((exp & 0x20) != 0) in dib8000_get_snr()
3881 exp -= 0x40; in dib8000_get_snr()
3884 if (n > 0) { in dib8000_get_snr()
3888 return 0xffffffff; in dib8000_get_snr()
3901 if ((snr_master >> 16) != 0) { in dib8000_read_snr()
3906 *snr = 0; in dib8000_read_snr()
3908 return 0; in dib8000_read_snr()
3971 { 0, 0 },
3982 if (value >= segments[0].x) in interpolate_value()
3983 return segments[0].y; in interpolate_value()
4010 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_time_us()
4015 int interleaving = 0, fft_div; in dib8000_get_time_us()
4017 if (layer >= 0) { in dib8000_get_time_us()
4021 ini_layer = 0; in dib8000_get_time_us()
4054 denom = 0; in dib8000_get_time_us()
4057 if (nsegs == 0 || nsegs > 13) in dib8000_get_time_us()
4105 return 0; in dib8000_get_time_us()
4124 struct dtv_frontend_properties *c = &state->fe[0]->dtv_property_cache; in dib8000_get_stats()
4126 int show_per_stats = 0; in dib8000_get_stats()
4127 u32 time_us = 0, snr, val; in dib8000_get_stats()
4138 c->strength.stat[0].svalue = db; in dib8000_get_stats()
4147 c->cnr.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4148 c->post_bit_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4149 c->post_bit_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4150 c->block_error.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4151 c->block_count.stat[0].scale = FE_SCALE_NOT_AVAILABLE; in dib8000_get_stats()
4152 return 0; in dib8000_get_stats()
4171 snr = 0; in dib8000_get_stats()
4173 c->cnr.stat[0].svalue = snr; in dib8000_get_stats()
4174 c->cnr.stat[0].scale = FE_SCALE_DECIBEL; in dib8000_get_stats()
4179 state->init_ucb += 0x100000000LL; in dib8000_get_stats()
4181 c->block_error.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4182 c->block_error.stat[0].uvalue = val + state->init_ucb; in dib8000_get_stats()
4191 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4192 c->block_count.stat[0].uvalue += blocks; in dib8000_get_stats()
4206 c->post_bit_error.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4207 c->post_bit_error.stat[0].uvalue += val; in dib8000_get_stats()
4209 c->post_bit_count.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4210 c->post_bit_count.stat[0].uvalue += 100000000; in dib8000_get_stats()
4213 if (state->revision < 0x8002) in dib8000_get_stats()
4214 return 0; in dib8000_get_stats()
4220 for (i = 0; i < 3; i++) { in dib8000_get_stats()
4223 if (nsegs == 0 || nsegs > 13) in dib8000_get_stats()
4226 time_us = 0; in dib8000_get_stats()
4254 c->block_count.stat[0].scale = FE_SCALE_COUNTER; in dib8000_get_stats()
4255 c->block_count.stat[0].uvalue += blocks; in dib8000_get_stats()
4259 return 0; in dib8000_get_stats()
4272 return 0; in dib8000_set_slave_frontend()
4291 int k = 0, ret = 0; in dib8000_i2c_enumeration()
4292 u8 new_addr = 0; in dib8000_i2c_enumeration()
4314 for (k = no_of_demods - 1; k >= 0; k--) { in dib8000_i2c_enumeration()
4320 dib8000_i2c_write16(&client, 1287, 0x0003); /* sram lead in, rdy */ in dib8000_i2c_enumeration()
4321 if (dib8000_identify(&client) == 0) { in dib8000_i2c_enumeration()
4324 dib8000_i2c_write16(&client, 1287, 0x0003); in dib8000_i2c_enumeration()
4326 if (dib8000_identify(&client) == 0) { in dib8000_i2c_enumeration()
4337 dib8000_i2c_write16(&client, 1285, (new_addr << 2) | 0x2); in dib8000_i2c_enumeration()
4341 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr); in dib8000_i2c_enumeration()
4344 for (k = 0; k < no_of_demods; k++) { in dib8000_i2c_enumeration()
4352 dib8000_i2c_write16(&client, 1286, 0); in dib8000_i2c_enumeration()
4368 tune->step_size = 0; in dib8000_fe_get_tune_settings()
4369 tune->max_drift = 0; in dib8000_fe_get_tune_settings()
4370 return 0; in dib8000_fe_get_tune_settings()
4383 kfree(st->fe[0]); in dib8000_release()
4396 u16 val = dib8000_read_word(st, 299) & 0xffef; in dib8000_pid_filter_ctrl()
4397 val |= (onoff & 0x1) << 4; in dib8000_pid_filter_ctrl()
4407 return dib8000_write_word(st, 305 + id, onoff ? (1 << 13) | pid : 0); in dib8000_pid_filter()
4470 state->fe[0] = fe; in dib8000_init()
4472 memcpy(&state->fe[0]->ops, &dib8000_ops, sizeof(struct dvb_frontend_ops)); in dib8000_init()
4476 if (dib8000_identify(&state->i2c) == 0) { in dib8000_init()
4494 …dib8000_write_word(state, 285, (dib8000_read_word(state, 285) & ~0x60) | (3 << 5)); /* ber_rs_len … in dib8000_init()