Lines Matching +full:0 +full:xfff7
22 MODULE_PARM_DESC(debug, "turn on debugging (default: 0)");
28 } while (0)
67 DIB7000M_POWER_ALL = 0,
80 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000m_read_word()
82 return 0; in dib7000m_read_word()
85 state->i2c_write_buffer[0] = (reg >> 8) | 0x80; in dib7000m_read_word()
86 state->i2c_write_buffer[1] = reg & 0xff; in dib7000m_read_word()
88 memset(state->msg, 0, 2 * sizeof(struct i2c_msg)); in dib7000m_read_word()
89 state->msg[0].addr = state->i2c_addr >> 1; in dib7000m_read_word()
90 state->msg[0].flags = 0; in dib7000m_read_word()
91 state->msg[0].buf = state->i2c_write_buffer; in dib7000m_read_word()
92 state->msg[0].len = 2; in dib7000m_read_word()
101 ret = (state->i2c_read_buffer[0] << 8) | state->i2c_read_buffer[1]; in dib7000m_read_word()
111 if (mutex_lock_interruptible(&state->i2c_buffer_lock) < 0) { in dib7000m_write_word()
116 state->i2c_write_buffer[0] = (reg >> 8) & 0xff; in dib7000m_write_word()
117 state->i2c_write_buffer[1] = reg & 0xff; in dib7000m_write_word()
118 state->i2c_write_buffer[2] = (val >> 8) & 0xff; in dib7000m_write_word()
119 state->i2c_write_buffer[3] = val & 0xff; in dib7000m_write_word()
121 memset(&state->msg[0], 0, sizeof(struct i2c_msg)); in dib7000m_write_word()
122 state->msg[0].addr = state->i2c_addr >> 1; in dib7000m_write_word()
123 state->msg[0].flags = 0; in dib7000m_write_word()
124 state->msg[0].buf = state->i2c_write_buffer; in dib7000m_write_word()
125 state->msg[0].len = 4; in dib7000m_write_word()
128 -EREMOTEIO : 0); in dib7000m_write_word()
134 u16 l = 0, r, *n; in dib7000m_write_tab()
153 int ret = 0; in dib7000m_set_output_mode()
155 sram = 0x0005; /* by default SRAM output is disabled */ in dib7000m_set_output_mode()
157 outreg = 0; in dib7000m_set_output_mode()
159 smo_mode = (dib7000m_read_word(state, 294 + state->reg_offs) & 0x0010) | (1 << 1); in dib7000m_set_output_mode()
165 outreg = (1 << 10); /* 0x0400 */ in dib7000m_set_output_mode()
168 outreg = (1 << 10) | (1 << 6); /* 0x0440 */ in dib7000m_set_output_mode()
171 outreg = (1 << 10) | (2 << 6) | (0 << 1); /* 0x0482 */ in dib7000m_set_output_mode()
175 outreg = (1 << 10) | (4 << 6); /* 0x0500 */ in dib7000m_set_output_mode()
177 sram |= 0x0c00; in dib7000m_set_output_mode()
185 outreg = 0; in dib7000m_set_output_mode()
200 if (state->revision == 0x4003) { in dib7000m_set_output_mode()
201 u16 clk_cfg1 = dib7000m_read_word(state, 909) & 0xfffd; in dib7000m_set_output_mode()
212 u16 reg_903 = 0xffff, reg_904 = 0xffff, reg_905 = 0xffff, reg_906 = 0x3fff; in dib7000m_set_power_mode()
213 u8 offset = 0; in dib7000m_set_power_mode()
219 reg_903 = 0x0000; reg_904 = 0x0000; reg_905 = 0x0000; reg_906 = 0x0000; in dib7000m_set_power_mode()
230 reg_906 &= ~((1 << 0)); in dib7000m_set_power_mode()
234 reg_903 = 0x0000; reg_904 = 0x801f; reg_905 = 0x0000; reg_906 = 0x0000; in dib7000m_set_power_mode()
238 reg_903 = 0x0000; reg_904 = 0x8000; reg_905 = 0x010b; reg_906 = 0x0000; in dib7000m_set_power_mode()
248 /* P_sdio_select_clk = 0 on MC and after*/ in dib7000m_set_power_mode()
249 if (state->revision != 0x4000) in dib7000m_set_power_mode()
252 if (state->revision == 0x4003) in dib7000m_set_power_mode()
263 int ret = 0; in dib7000m_set_adc_state()
269 reg_914 |= (1 << 1) | (1 << 0); in dib7000m_set_adc_state()
275 reg_914 |= (1 << 1) | (1 << 0); in dib7000m_set_adc_state()
279 if (state->revision == 0x4000) { // workaround for PA/MA in dib7000m_set_adc_state()
281 dib7000m_write_word(state, 913, 0); in dib7000m_set_adc_state()
282 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
285 dib7000m_write_word(state, 914, reg_914 & 0x3); in dib7000m_set_adc_state()
288 reg_913 &= 0x0fff; in dib7000m_set_adc_state()
289 reg_914 &= 0x0003; in dib7000m_set_adc_state()
326 if (state->timf == 0) { in dib7000m_set_bandwidth()
336 dib7000m_write_word(state, 23, (u16) ((timf >> 16) & 0xffff)); in dib7000m_set_bandwidth()
337 dib7000m_write_word(state, 24, (u16) ((timf ) & 0xffff)); in dib7000m_set_bandwidth()
339 return 0; in dib7000m_set_bandwidth()
348 onoff = 0; in dib7000m_set_diversity_in()
355 …b7000m_write_word(state, 266 + state->reg_offs, (state->div_sync_wait << 4) | (1 << 2) | (2 << 0)); in dib7000m_set_diversity_in()
358 dib7000m_write_word(state, 264 + state->reg_offs, 0); in dib7000m_set_diversity_in()
359 dib7000m_write_word(state, 266 + state->reg_offs, 0); in dib7000m_set_diversity_in()
362 return 0; in dib7000m_set_diversity_in()
369 // dib7000m_write_word(state, 928, (3 << 14) | (1 << 12) | (524 << 0)); // sampling clock of the SA… in dib7000m_sad_calib()
370 dib7000m_write_word(state, 929, (0 << 1) | (0 << 0)); in dib7000m_sad_calib()
374 dib7000m_write_word(state, 929, (1 << 0)); in dib7000m_sad_calib()
375 dib7000m_write_word(state, 929, (0 << 0)); in dib7000m_sad_calib()
379 return 0; in dib7000m_sad_calib()
384 dib7000m_write_word(state, 18, (u16) (((bw->internal*1000) >> 16) & 0xffff)); in dib7000m_reset_pll_common()
385 dib7000m_write_word(state, 19, (u16) ( (bw->internal*1000) & 0xffff)); in dib7000m_reset_pll_common()
386 dib7000m_write_word(state, 21, (u16) ( (bw->ifreq >> 16) & 0xffff)); in dib7000m_reset_pll_common()
387 dib7000m_write_word(state, 22, (u16) ( bw->ifreq & 0xffff)); in dib7000m_reset_pll_common()
400 (bw->enable_refdiv << 1) | (0 << 0); in dib7000m_reset_pll()
401 reg_910 = (((bw->pll_ratio >> 6) & 0x3) << 3) | (bw->pll_range << 1) | bw->pll_reset; in dib7000m_reset_pll()
414 reg_907 |= (bw->pll_ratio & 0x3f) << 9; in dib7000m_reset_pll()
420 dib7000m_write_word(state, 908, 0x0006); // clk_cfg1 in dib7000m_reset_pll()
431 dib7000m_write_word(state, 907, (bw->pll_prediv << 8) | (bw->pll_ratio << 0)); in dib7000mc_reset_pll()
434 //dib7000m_write_word(state, 908, (1 << 14) | (3 << 12) |(0 << 11) | in dib7000mc_reset_pll()
435 clk_cfg1 = (0 << 14) | (3 << 12) |(0 << 11) | in dib7000mc_reset_pll()
437 (1 << 3) | (bw->pll_range << 1) | (bw->pll_reset << 0); in dib7000mc_reset_pll()
439 clk_cfg1 = (clk_cfg1 & 0xfff7) | (bw->pll_bypass << 3); in dib7000mc_reset_pll()
459 return 0; in dib7000m_reset_gpio()
467 0x0004,
468 0x1000,
469 0x0814,
472 0x001b,
473 0x7740,
474 0x005b,
475 0x8d80,
476 0x01c9,
477 0xc380,
478 0x0000,
479 0x0080,
480 0x0000,
481 0x0090,
482 0x0001,
483 0xd4c0,
486 0x6680, // P_corm_thres Lock algorithms configuration
489 0x0410, // P_palf_alpha_regul, P_palf_filter_freeze, P_palf_filter_on
492 0,
493 0,
494 0,
495 0,
496 0,
497 0,
498 0,
499 0,
505 0x0ccd, // P_pha3_thres
506 0, // P_cti_use_cpe, P_cti_use_prog
509 0x200f, // P_cspu_regul, P_cspu_win_cut
512 0x023d, // P_adp_regul_cnt
513 0x00a4, // P_adp_noise_cnt
514 0x00a4, // P_adp_regul_ext
515 0x7ff0, // P_adp_noise_ext
516 0x3ccc, // P_adp_fil
519 0, // P_2d_byp_ti_num
522 0x800, // P_equal_thres_wgn
525 0x0001,
528 0x0010, // P_fec_*
531 0x0062, // P_smo_mode, P_smo_rs_discard, P_smo_fifo_flush, P_smo_pid_parse, P_smo_error_discard
533 0
555 0x2c8a,
560 0,
571 dib7000m_write_word(state, 898, 0xffff); in dib7000m_demod_reset()
572 dib7000m_write_word(state, 899, 0xffff); in dib7000m_demod_reset()
573 dib7000m_write_word(state, 900, 0xff0f); in dib7000m_demod_reset()
574 dib7000m_write_word(state, 901, 0xfffc); in dib7000m_demod_reset()
576 dib7000m_write_word(state, 898, 0); in dib7000m_demod_reset()
577 dib7000m_write_word(state, 899, 0); in dib7000m_demod_reset()
578 dib7000m_write_word(state, 900, 0); in dib7000m_demod_reset()
579 dib7000m_write_word(state, 901, 0); in dib7000m_demod_reset()
581 if (state->revision == 0x4000) in dib7000m_demod_reset()
586 if (dib7000m_reset_gpio(state) != 0) in dib7000m_demod_reset()
589 if (dib7000m_set_output_mode(state, OUTMODE_HIGH_Z) != 0) in dib7000m_demod_reset()
602 dib7000m_write_word(state, 1796, 0x0); // select DVB-T output in dib7000m_demod_reset()
611 dib7000m_write_word(state, 36, 0x0755); in dib7000m_demod_reset()
613 dib7000m_write_word(state, 36, 0x1f55); in dib7000m_demod_reset()
616 if (state->revision == 0x4000) in dib7000m_demod_reset()
628 return 0; in dib7000m_demod_reset()
634 dib7000m_write_word(state, 898, 0x0c00); in dib7000m_restart_agc()
635 dib7000m_write_word(state, 898, 0x0000); in dib7000m_restart_agc()
642 …e->current_agc || !state->current_agc->perform_agc_softsplit || state->current_agc->split.max == 0) in dib7000m_agc_soft_split()
643 return 0; in dib7000m_agc_soft_split()
660 return dib7000m_write_word(state, 103, (dib7000m_read_word(state, 103) & 0xff00) | split_offset); in dib7000m_agc_soft_split()
676 return 0; in dib7000m_update_lna()
684 return 0; in dib7000m_set_agc_config()
687 for (i = 0; i < state->cfg.agc_config_count; i++) in dib7000m_set_agc_config()
694 dprintk("no valid AGC configuration found for band 0x%02x\n", band); in dib7000m_set_agc_config()
711 …state->wbd_ref != 0 ? state->wbd_ref : agc->wbd_ref, agc->wbd_sel, !agc->perform_agc_softsplit, ag… in dib7000m_set_agc_config()
714 if (state->wbd_ref != 0) in dib7000m_set_agc_config()
729 if (state->revision > 0x4000) { // settings for the MC in dib7000m_set_agc_config()
732 // (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | (agc->wbd_sel << 2), agc->wb… in dib7000m_set_agc_config()
733 …dib7000m_write_word(state, 929, (dib7000m_read_word(state, 929) & 0xffe3) | (agc->wbd_inv << 4) | … in dib7000m_set_agc_config()
737 for (i = 0; i < 9; i++) in dib7000m_set_agc_config()
740 return 0; in dib7000m_set_agc_config()
748 dib7000m_write_word(state, 24, (u16) (timf & 0xffff)); in dib7000m_update_timf()
762 case 0: in dib7000m_agc_startup()
767 if (dib7000m_set_agc_config(state, BAND_OF_FREQUENCY(ch->frequency/1000)) != 0) in dib7000m_agc_startup()
782 dib7000m_write_word(state, 103, 1 << 8); /* force 0 split on WBD and restart AGC */ in dib7000m_agc_startup()
832 state->cfg.agc_control(&state->demod, 0); in dib7000m_agc_startup()
851 value = 0; in dib7000m_set_channel()
853 case TRANSMISSION_MODE_2K: value |= (0 << 7); break; in dib7000m_set_channel()
859 case GUARD_INTERVAL_1_32: value |= (0 << 5); break; in dib7000m_set_channel()
866 case QPSK: value |= (0 << 3); break; in dib7000m_set_channel()
877 dib7000m_write_word(state, 0, value); in dib7000m_set_channel()
881 value = 0; in dib7000m_set_channel()
882 if (1 != 0) in dib7000m_set_channel()
888 switch ((ch->hierarchy == 0 || 1 == 1) ? ch->code_rate_HP : ch->code_rate_LP) { in dib7000m_set_channel()
900 /* P_timf_alpha = 6, P_corm_alpha=6, P_corm_thres=0x80 */ in dib7000m_set_channel()
901 dib7000m_write_word(state, 26, (6 << 12) | (6 << 8) | 0x80); in dib7000m_set_channel()
903 …/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=1, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, … in dib7000m_set_channel()
904 dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (1 << 9) | (3 << 5) | (1 << 4) | (0x3)); in dib7000m_set_channel()
906 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max=3 */ in dib7000m_set_channel()
907 dib7000m_write_word(state, 32, (0 << 4) | 0x3); in dib7000m_set_channel()
909 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step=5 */ in dib7000m_set_channel()
910 dib7000m_write_word(state, 33, (0 << 4) | 0x5); in dib7000m_set_channel()
929 /* P_dvsy_sync_mode = 0, P_dvsy_sync_enable=1, P_dvcb_comb_mode=2 */ in dib7000m_set_channel()
930 if (1 == 1 || state->revision > 0x4000) in dib7000m_set_channel()
931 state->div_force_off = 0; in dib7000m_set_channel()
939 est[0] = 0x0148; /* P_adp_regul_cnt 0.04 */ in dib7000m_set_channel()
940 est[1] = 0xfff0; /* P_adp_noise_cnt -0.002 */ in dib7000m_set_channel()
941 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ in dib7000m_set_channel()
942 est[3] = 0xfff8; /* P_adp_noise_ext -0.001 */ in dib7000m_set_channel()
945 est[0] = 0x023d; /* P_adp_regul_cnt 0.07 */ in dib7000m_set_channel()
946 est[1] = 0xffdf; /* P_adp_noise_cnt -0.004 */ in dib7000m_set_channel()
947 est[2] = 0x00a4; /* P_adp_regul_ext 0.02 */ in dib7000m_set_channel()
948 est[3] = 0xfff0; /* P_adp_noise_ext -0.002 */ in dib7000m_set_channel()
951 est[0] = 0x099a; /* P_adp_regul_cnt 0.3 */ in dib7000m_set_channel()
952 est[1] = 0xffae; /* P_adp_noise_cnt -0.01 */ in dib7000m_set_channel()
953 est[2] = 0x0333; /* P_adp_regul_ext 0.1 */ in dib7000m_set_channel()
954 est[3] = 0xfff8; /* P_adp_noise_ext -0.002 */ in dib7000m_set_channel()
957 for (value = 0; value < 4; value++) in dib7000m_set_channel()
969 int ret = 0; in dib7000m_autosearch_start()
979 schan.hierarchy = 0; in dib7000m_autosearch_start()
991 ret |= dib7000m_write_word(state, 6, (u16) ((value >> 16) & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
992 ret |= dib7000m_write_word(state, 7, (u16) (value & 0xffff)); // lock0 wait time in dib7000m_autosearch_start()
994 ret |= dib7000m_write_word(state, 8, (u16) ((value >> 16) & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
995 ret |= dib7000m_write_word(state, 9, (u16) (value & 0xffff)); // lock1 wait time in dib7000m_autosearch_start()
997 ret |= dib7000m_write_word(state, 10, (u16) ((value >> 16) & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
998 ret |= dib7000m_write_word(state, 11, (u16) (value & 0xffff)); // lock2 wait time in dib7000m_autosearch_start()
1001 value = dib7000m_read_word(state, 0); in dib7000m_autosearch_start()
1002 ret |= dib7000m_write_word(state, 0, (u16) (value | (1 << 9))); in dib7000m_autosearch_start()
1005 if (state->revision == 0x4000) in dib7000m_autosearch_start()
1006 dib7000m_write_word(state, 1793, 0); in dib7000m_autosearch_start()
1010 ret |= dib7000m_write_word(state, 0, (u16) value); in dib7000m_autosearch_start()
1019 if (irq_pending & 0x1) { // failed in dib7000m_autosearch_irq()
1024 if (irq_pending & 0x2) { // succeeded in dib7000m_autosearch_irq()
1028 return 0; // still pending in dib7000m_autosearch_irq()
1034 if (state->revision == 0x4000) in dib7000m_autosearch_is_irq()
1044 int ret = 0; in dib7000m_tune()
1048 dib7000m_set_channel(state, ch, 0); in dib7000m_tune()
1051 ret |= dib7000m_write_word(state, 898, 0x4000); in dib7000m_tune()
1052 ret |= dib7000m_write_word(state, 898, 0x0000); in dib7000m_tune()
1056 …/* P_ctrl_inh_cor=0, P_ctrl_alpha_cor=4, P_ctrl_inh_isi=0, P_ctrl_alpha_isi=3, P_ctrl_inh_cor4=1, … in dib7000m_tune()
1057 …ret |= dib7000m_write_word(state, 29, (0 << 14) | (4 << 10) | (0 << 9) | (3 << 5) | (1 << 4) | (0x… in dib7000m_tune()
1060 if (state->timf == 0) in dib7000m_tune()
1064 /* P_timf_alpha, P_corm_alpha=6, P_corm_thres=0x80 */ in dib7000m_tune()
1065 value = (6 << 8) | 0x80; in dib7000m_tune()
1074 /* P_ctrl_freeze_pha_shift=0, P_ctrl_pha_off_max */ in dib7000m_tune()
1075 value = (0 << 4); in dib7000m_tune()
1077 case TRANSMISSION_MODE_2K: value |= 0x6; break; in dib7000m_tune()
1078 case TRANSMISSION_MODE_4K: value |= 0x7; break; in dib7000m_tune()
1080 case TRANSMISSION_MODE_8K: value |= 0x8; break; in dib7000m_tune()
1084 /* P_ctrl_sfreq_inh=0, P_ctrl_sfreq_step */ in dib7000m_tune()
1085 value = (0 << 4); in dib7000m_tune()
1087 case TRANSMISSION_MODE_2K: value |= 0x6; break; in dib7000m_tune()
1088 case TRANSMISSION_MODE_4K: value |= 0x7; break; in dib7000m_tune()
1090 case TRANSMISSION_MODE_8K: value |= 0x8; break; in dib7000m_tune()
1095 if ((dib7000m_read_word(state, 535) >> 6) & 0x1) in dib7000m_tune()
1108 if (dib7000m_set_adc_state(state, DIBX000_SLOW_ADC_ON) != 0) in dib7000m_wakeup()
1111 return 0; in dib7000m_wakeup()
1127 if ((value = dib7000m_read_word(state, 896)) != 0x01b3) { in dib7000m_identify()
1128 dprintk("wrong Vendor ID (0x%x)\n", value); in dib7000m_identify()
1133 if (state->revision != 0x4000 && in dib7000m_identify()
1134 state->revision != 0x4001 && in dib7000m_identify()
1135 state->revision != 0x4002 && in dib7000m_identify()
1136 state->revision != 0x4003) { in dib7000m_identify()
1137 dprintk("wrong Device ID (0x%x)\n", value); in dib7000m_identify()
1142 if (state->revision == 0x4000 && dib7000m_read_word(state, 769) == 0x4000) { in dib7000m_identify()
1148 case 0x4000: dprintk("found DiB7000MA/PA/MB/PB\n"); break; in dib7000m_identify()
1149 case 0x4001: state->reg_offs = 1; dprintk("found DiB7000HC\n"); break; in dib7000m_identify()
1150 case 0x4002: state->reg_offs = 1; dprintk("found DiB7000MC\n"); break; in dib7000m_identify()
1151 case 0x4003: state->reg_offs = 1; dprintk("found DiB9000\n"); break; in dib7000m_identify()
1154 return 0; in dib7000m_identify()
1168 switch ((tps >> 8) & 0x3) { in dib7000m_get_frontend()
1169 case 0: fep->transmission_mode = TRANSMISSION_MODE_2K; break; in dib7000m_get_frontend()
1174 switch (tps & 0x3) { in dib7000m_get_frontend()
1175 case 0: fep->guard_interval = GUARD_INTERVAL_1_32; break; in dib7000m_get_frontend()
1181 switch ((tps >> 14) & 0x3) { in dib7000m_get_frontend()
1182 case 0: fep->modulation = QPSK; break; in dib7000m_get_frontend()
1189 /* (tps >> 13) & 0x1 == hrch is used, (tps >> 10) & 0x7 == alpha */ in dib7000m_get_frontend()
1192 switch ((tps >> 5) & 0x7) { in dib7000m_get_frontend()
1202 switch ((tps >> 2) & 0x7) { in dib7000m_get_frontend()
1211 /* native interleaver: (dib7000m_read_word(state, 481) >> 5) & 0x1 */ in dib7000m_get_frontend()
1213 return 0; in dib7000m_get_frontend()
1230 state->agc_state = 0; in dib7000m_set_frontend()
1247 } while (found == 0 && i--); in dib7000m_set_frontend()
1250 if (found == 0 || found == 1) in dib7000m_set_frontend()
1251 return 0; // no channel found in dib7000m_set_frontend()
1268 *stat = 0; in dib7000m_read_status()
1270 if (lock & 0x8000) in dib7000m_read_status()
1272 if (lock & 0x3000) in dib7000m_read_status()
1274 if (lock & 0x0100) in dib7000m_read_status()
1276 if (lock & 0x0010) in dib7000m_read_status()
1278 if (lock & 0x0008) in dib7000m_read_status()
1281 return 0; in dib7000m_read_status()
1288 return 0; in dib7000m_read_ber()
1295 return 0; in dib7000m_read_unc_blocks()
1303 return 0; in dib7000m_read_signal_strength()
1308 *snr = 0x0000; in dib7000m_read_snr()
1309 return 0; in dib7000m_read_snr()
1315 return 0; in dib7000m_fe_get_tune_settings()
1335 u16 val = dib7000m_read_word(state, 294 + state->reg_offs) & 0xffef; in dib7000m_pid_filter_ctrl()
1336 val |= (onoff & 0x1) << 4; in dib7000m_pid_filter_ctrl()
1347 onoff ? (1 << 13) | pid : 0); in dib7000m_pid_filter()
1351 #if 0
1357 int k = 0;
1358 u8 new_addr = 0;
1360 for (k = no_of_demods-1; k >= 0; k--) {
1364 new_addr = (0x40 + k) << 1;
1366 if (dib7000m_identify(&st) != 0) {
1368 if (dib7000m_identify(&st) != 0) {
1377 dib7000m_write_word(&st, 1796, 0x0); // select DVB-T output
1380 dib7000m_write_word(&st, 1794, (new_addr << 2) | 0x2);
1382 dprintk("IC %d initialized (to i2c_address 0x%x)\n", k, new_addr);
1385 for (k = 0; k < no_of_demods; k++) {
1387 st.i2c_addr = (0x40 + k) << 1;
1396 return 0;
1421 if (dib7000m_identify(st) != 0) in dib7000m_attach()
1424 if (st->revision == 0x4000) in dib7000m_attach()