148 	wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);  in dib3000mb_set_frontend()
153 			wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_2K);  in dib3000mb_set_frontend()
157 			wr(DIB3000MB_REG_FFT, DIB3000_TRANSMISSION_MODE_8K);  in dib3000mb_set_frontend()
169 			wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_32);  in dib3000mb_set_frontend()
173 			wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_16);  in dib3000mb_set_frontend()
177 			wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_8);  in dib3000mb_set_frontend()
181 			wr(DIB3000MB_REG_GUARD_TIME, DIB3000_GUARD_TIME_1_4);  in dib3000mb_set_frontend()
193 			wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_OFF);  in dib3000mb_set_frontend()
200 			wr(DIB3000MB_REG_DDS_INV, DIB3000_DDS_INVERSION_ON);  in dib3000mb_set_frontend()
209 			wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_QPSK);  in dib3000mb_set_frontend()
213 			wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_16QAM);  in dib3000mb_set_frontend()
217 			wr(DIB3000MB_REG_QAM, DIB3000_CONSTELLATION_64QAM);  in dib3000mb_set_frontend()
230 			wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_1);  in dib3000mb_set_frontend()
234 			wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_2);  in dib3000mb_set_frontend()
238 			wr(DIB3000MB_REG_VIT_ALPHA, DIB3000_ALPHA_4);  in dib3000mb_set_frontend()
248 		wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_OFF);  in dib3000mb_set_frontend()
249 		wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_HP);  in dib3000mb_set_frontend()
252 		wr(DIB3000MB_REG_VIT_HRCH, DIB3000_HRCH_ON);  in dib3000mb_set_frontend()
253 		wr(DIB3000MB_REG_VIT_HP, DIB3000_SELECT_LP);  in dib3000mb_set_frontend()
259 			wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_1_2);  in dib3000mb_set_frontend()
263 			wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_2_3);  in dib3000mb_set_frontend()
267 			wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_3_4);  in dib3000mb_set_frontend()
271 			wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_5_6);  in dib3000mb_set_frontend()
275 			wr(DIB3000MB_REG_VIT_CODE_RATE, DIB3000_FEC_7_8);  in dib3000mb_set_frontend()
294 	wr(DIB3000MB_REG_SEQ, seq);  in dib3000mb_set_frontend()
296 	wr(DIB3000MB_REG_ISI, seq ? DIB3000MB_ISI_INHIBIT : DIB3000MB_ISI_ACTIVATE);  in dib3000mb_set_frontend()
300 			wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_2K_1_8);  in dib3000mb_set_frontend()
302 			wr(DIB3000MB_REG_SYNC_IMPROVEMENT, DIB3000MB_SYNC_IMPROVE_DEFAULT);  in dib3000mb_set_frontend()
305 		wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_2K);  in dib3000mb_set_frontend()
307 		wr(DIB3000MB_REG_UNK_121, DIB3000MB_UNK_121_DEFAULT);  in dib3000mb_set_frontend()
310 	wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_OFF);  in dib3000mb_set_frontend()
311 	wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);  in dib3000mb_set_frontend()
312 	wr(DIB3000MB_REG_MOBILE_MODE, DIB3000MB_MOBILE_MODE_OFF);  in dib3000mb_set_frontend()
316 	wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_ACTIVATE);  in dib3000mb_set_frontend()
318 	wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC + DIB3000MB_RESTART_CTRL);  in dib3000mb_set_frontend()
319 	wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);  in dib3000mb_set_frontend()
335 		wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);  in dib3000mb_set_frontend()
337 		wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AUTO_SEARCH);  in dib3000mb_set_frontend()
338 		wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);  in dib3000mb_set_frontend()
357 		wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_CTRL);  in dib3000mb_set_frontend()
358 		wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_OFF);  in dib3000mb_set_frontend()
369 	wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_UP);  in dib3000mb_fe_init()
371 	wr(DIB3000MB_REG_RESTART, DIB3000MB_RESTART_AGC);  in dib3000mb_fe_init()
373 	wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE);  in dib3000mb_fe_init()
374 	wr(DIB3000MB_REG_RESET_DEVICE, DIB3000MB_RESET_DEVICE_RST);  in dib3000mb_fe_init()
376 	wr(DIB3000MB_REG_CLOCK, DIB3000MB_CLOCK_DEFAULT);  in dib3000mb_fe_init()
378 	wr(DIB3000MB_REG_ELECT_OUT_MODE, DIB3000MB_ELECT_OUT_MODE_ON);  in dib3000mb_fe_init()
380 	wr(DIB3000MB_REG_DDS_FREQ_MSB, DIB3000MB_DDS_FREQ_MSB);  in dib3000mb_fe_init()
381 	wr(DIB3000MB_REG_DDS_FREQ_LSB, DIB3000MB_DDS_FREQ_LSB);  in dib3000mb_fe_init()
390 	wr(DIB3000MB_REG_PHASE_NOISE, DIB3000MB_PHASE_NOISE_DEFAULT);  in dib3000mb_fe_init()
398 	wr(DIB3000MB_REG_LOCK0_MASK, DIB3000MB_LOCK0_DEFAULT);  in dib3000mb_fe_init()
399 	wr(DIB3000MB_REG_LOCK1_MASK, DIB3000MB_LOCK1_SEARCH_4);  in dib3000mb_fe_init()
400 	wr(DIB3000MB_REG_LOCK2_MASK, DIB3000MB_LOCK2_DEFAULT);  in dib3000mb_fe_init()
401 	wr(DIB3000MB_REG_SEQ, dib3000_seq[1][1][1]);  in dib3000mb_fe_init()
405 	wr(DIB3000MB_REG_UNK_68, DIB3000MB_UNK_68);  in dib3000mb_fe_init()
406 	wr(DIB3000MB_REG_UNK_69, DIB3000MB_UNK_69);  in dib3000mb_fe_init()
407 	wr(DIB3000MB_REG_UNK_71, DIB3000MB_UNK_71);  in dib3000mb_fe_init()
408 	wr(DIB3000MB_REG_UNK_77, DIB3000MB_UNK_77);  in dib3000mb_fe_init()
409 	wr(DIB3000MB_REG_UNK_78, DIB3000MB_UNK_78);  in dib3000mb_fe_init()
410 	wr(DIB3000MB_REG_ISI, DIB3000MB_ISI_INHIBIT);  in dib3000mb_fe_init()
411 	wr(DIB3000MB_REG_UNK_92, DIB3000MB_UNK_92);  in dib3000mb_fe_init()
412 	wr(DIB3000MB_REG_UNK_96, DIB3000MB_UNK_96);  in dib3000mb_fe_init()
413 	wr(DIB3000MB_REG_UNK_97, DIB3000MB_UNK_97);  in dib3000mb_fe_init()
414 	wr(DIB3000MB_REG_UNK_106, DIB3000MB_UNK_106);  in dib3000mb_fe_init()
415 	wr(DIB3000MB_REG_UNK_107, DIB3000MB_UNK_107);  in dib3000mb_fe_init()
416 	wr(DIB3000MB_REG_UNK_108, DIB3000MB_UNK_108);  in dib3000mb_fe_init()
417 	wr(DIB3000MB_REG_UNK_122, DIB3000MB_UNK_122);  in dib3000mb_fe_init()
418 	wr(DIB3000MB_REG_MOBILE_MODE_QAM, DIB3000MB_MOBILE_MODE_QAM_OFF);  in dib3000mb_fe_init()
419 	wr(DIB3000MB_REG_BERLEN, DIB3000MB_BERLEN_DEFAULT);  in dib3000mb_fe_init()
423 	wr(DIB3000MB_REG_MOBILE_ALGO, DIB3000MB_MOBILE_ALGO_ON);  in dib3000mb_fe_init()
424 	wr(DIB3000MB_REG_MULTI_DEMOD_MSB, DIB3000MB_MULTI_DEMOD_MSB);  in dib3000mb_fe_init()
425 	wr(DIB3000MB_REG_MULTI_DEMOD_LSB, DIB3000MB_MULTI_DEMOD_LSB);  in dib3000mb_fe_init()
427 	wr(DIB3000MB_REG_OUTPUT_MODE, DIB3000MB_OUTPUT_MODE_SLAVE);  in dib3000mb_fe_init()
429 	wr(DIB3000MB_REG_FIFO_142, DIB3000MB_FIFO_142);  in dib3000mb_fe_init()
430 	wr(DIB3000MB_REG_MPEG2_OUT_MODE, DIB3000MB_MPEG2_OUT_MODE_188);  in dib3000mb_fe_init()
431 	wr(DIB3000MB_REG_PID_PARSE, DIB3000MB_PID_PARSE_ACTIVATE);  in dib3000mb_fe_init()
432 	wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);  in dib3000mb_fe_init()
433 	wr(DIB3000MB_REG_FIFO_146, DIB3000MB_FIFO_146);  in dib3000mb_fe_init()
434 	wr(DIB3000MB_REG_FIFO_147, DIB3000MB_FIFO_147);  in dib3000mb_fe_init()
436 	wr(DIB3000MB_REG_DATA_IN_DIVERSITY, DIB3000MB_DATA_DIVERSITY_IN_OFF);  in dib3000mb_fe_init()
674 	wr(DIB3000MB_REG_POWER_CONTROL, DIB3000MB_POWER_DOWN);  in dib3000mb_sleep()
705 	wr(index+DIB3000MB_REG_FIRST_PID,pid);  in dib3000mb_pid_control()
715 		wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_ACTIVATE);  in dib3000mb_fifo_control()
717 		wr(DIB3000MB_REG_FIFO, DIB3000MB_FIFO_INHIBIT);  in dib3000mb_fifo_control()
726 	wr(DIB3000MB_REG_PID_PARSE,onoff);  in dib3000mb_pid_parse()
734 		wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_ENABLE(pll_addr));  in dib3000mb_tuner_pass_ctrl()
736 		wr(DIB3000MB_REG_TUNER, DIB3000_TUNER_WRITE_DISABLE(pll_addr));  in dib3000mb_tuner_pass_ctrl()