512 	u16 PllCfg, i, v;  in dib0090_reset_digital()  local
530 	PllCfg = dib0090_read_reg(state, 0x21);  in dib0090_reset_digital()
533 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_reset_digital()
537 		PllCfg |= (1 << 15);  in dib0090_reset_digital()
538 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
541 		PllCfg &= ~(1 << 13);  in dib0090_reset_digital()
542 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
545 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_reset_digital()
546 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
549 		PllCfg |= (1 << 13);  in dib0090_reset_digital()
550 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
566 		PllCfg &= ~(1 << 15);  in dib0090_reset_digital()
567 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
571 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_reset_digital()
572 		dib0090_write_reg(state, 0x21, PllCfg);  in dib0090_reset_digital()
579 	u16 PllCfg;  in dib0090_fw_reset_digital()  local
602 	PllCfg = dib0090_fw_read_reg(state, 0x21);  in dib0090_fw_reset_digital()
605 …if ((PllCfg & 0x1FFF) != ((cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io.pll_pr…  in dib0090_fw_reset_digital()
608 		PllCfg |= (1 << 15);  in dib0090_fw_reset_digital()
609 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
612 		PllCfg &= ~(1 << 13);  in dib0090_fw_reset_digital()
613 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
616 …PllCfg = (1 << 15) | (0 << 13) | (cfg->io.pll_range << 12) | (cfg->io.pll_loopdiv << 6) | (cfg->io…  in dib0090_fw_reset_digital()
617 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
620 		PllCfg |= (1 << 13);  in dib0090_fw_reset_digital()
621 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
637 		PllCfg &= ~(1 << 15);  in dib0090_fw_reset_digital()
638 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()
642 		PllCfg |= (cfg->io.pll_bypass << 15);  in dib0090_fw_reset_digital()
643 		dib0090_fw_write_reg(state, 0x21, PllCfg);  in dib0090_fw_reset_digital()