Lines Matching refs:dib0070_write_reg
101 static int dib0070_write_reg(struct dib0070_state *state, u8 reg, u16 val) in dib0070_write_reg() function
151 dib0070_write_reg(state, 0x02, tmp); in dib0070_set_bandwidth()
157 dib0070_write_reg(state, 0x17, value & 0xfffc); in dib0070_set_bandwidth()
159 dib0070_write_reg(state, 0x01, tmp | (60 << 9)); in dib0070_set_bandwidth()
161 dib0070_write_reg(state, 0x17, value); in dib0070_set_bandwidth()
173 dib0070_write_reg(state, 0x0f, 0xed10); in dib0070_captrim()
174 dib0070_write_reg(state, 0x17, 0x0034); in dib0070_captrim()
176 dib0070_write_reg(state, 0x18, 0x0032); in dib0070_captrim()
184 dib0070_write_reg(state, 0x14, state->lo4 | state->captrim); in dib0070_captrim()
217 dib0070_write_reg(state, 0x14, state->lo4 | state->fcaptrim); in dib0070_captrim()
218 dib0070_write_reg(state, 0x18, 0x07ff); in dib0070_captrim()
231 return dib0070_write_reg(state, 0x15, lo5); in dib0070_set_ctrl_lo5()
239 dib0070_write_reg(state, 0x1b, 0xff00); in dib0070_ctrl_agc_filter()
240 dib0070_write_reg(state, 0x1a, 0x0000); in dib0070_ctrl_agc_filter()
242 dib0070_write_reg(state, 0x1b, 0x4112); in dib0070_ctrl_agc_filter()
244 dib0070_write_reg(state, 0x1a, state->cfg->vga_filter); in dib0070_ctrl_agc_filter()
247 dib0070_write_reg(state, 0x1a, 0x0009); in dib0070_ctrl_agc_filter()
379 dib0070_write_reg(state, 0x17, 0x30); in dib0070_tune_digital()
431 dib0070_write_reg(state, 0x11, (u16)FBDiv); in dib0070_tune_digital()
432 dib0070_write_reg(state, 0x12, (Den << 8) | REFDIV); in dib0070_tune_digital()
433 dib0070_write_reg(state, 0x13, (u16) Rest); in dib0070_tune_digital()
439 dib0070_write_reg(state, 0x1d, 0xFFFF); in dib0070_tune_digital()
444 dib0070_write_reg(state, 0x20, in dib0070_tune_digital()
473 dib0070_write_reg(state, 0x0f, in dib0070_tune_digital()
479 dib0070_write_reg(state, 0x0f, in dib0070_tune_digital()
486 dib0070_write_reg(state, 0x06, 0x3fff); in dib0070_tune_digital()
487 dib0070_write_reg(state, 0x07, in dib0070_tune_digital()
489 dib0070_write_reg(state, 0x08, (state->lna_match->lna_band << 10) | (3 << 7) | (127)); in dib0070_tune_digital()
490 dib0070_write_reg(state, 0x0d, 0x0d80); in dib0070_tune_digital()
493 dib0070_write_reg(state, 0x18, 0x07ff); in dib0070_tune_digital()
494 dib0070_write_reg(state, 0x17, 0x0033); in dib0070_tune_digital()
557 return dib0070_write_reg(state, 0x07, rxrf2 | (no << 11)); in dib0070_set_rf_output()
605 dib0070_write_reg(state, 0x18, 0x07ff); in dib0070_read_wbd_offset()
606 …dib0070_write_reg(state, 0x20, 0x0800 | 0x4000 | 0x0040 | 0x0020 | 0x0010 | 0x0008 | 0x0002 | 0x00… in dib0070_read_wbd_offset()
607 …dib0070_write_reg(state, 0x0f, (1 << 14) | (2 << 12) | (gain << 9) | (1 << 8) | (1 << 7) | (0 << 0… in dib0070_read_wbd_offset()
610 dib0070_write_reg(state, 0x20, tuner_en); in dib0070_read_wbd_offset()
671 dib0070_write_reg(state, (u8)r, pgm_read_word(n++)); in dib0070_reset()
687 dib0070_write_reg(state, 0x10, r); in dib0070_reset()
688 dib0070_write_reg(state, 0x1f, (1 << 8) | ((state->cfg->clock_pad_drive & 0xf) << 5)); in dib0070_reset()
692 dib0070_write_reg(state, 0x02, r | (1 << 5)); in dib0070_reset()
701 dib0070_write_reg(state, 0x01, (54 << 9) | 0xc8); in dib0070_reset()