Lines Matching +full:8 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
7 * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved.
11 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved.
37 #define TEGRA_CEC_HWCTRL_RX_SNOOP BIT(15)
38 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE BIT(16)
39 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE BIT(24)
40 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE BIT(30)
41 #define TEGRA_CEC_HWCTRL_TX_RX_MODE BIT(31)
43 #define TEGRA_CEC_INPUT_FILTER_MODE BIT(31)
47 #define TEGRA_CEC_TX_REG_EOM BIT(8)
48 #define TEGRA_CEC_TX_REG_BCAST BIT(12)
49 #define TEGRA_CEC_TX_REG_START_BIT BIT(16)
50 #define TEGRA_CEC_TX_REG_RETRY BIT(17)
53 #define TEGRA_CEC_RX_REGISTER_EOM BIT(8)
54 #define TEGRA_CEC_RX_REGISTER_ACK BIT(9)
57 #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT 8
62 #define TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT 8
69 #define TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT 8
74 #define TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT 8
80 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT 8
82 #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY BIT(0)
83 #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN BIT(1)
84 #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD BIT(2)
85 #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED BIT(3)
86 #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED BIT(4)
87 #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED BIT(5)
88 #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL BIT(8)
89 #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN BIT(9)
90 #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED BIT(10)
91 #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED BIT(11)
92 #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED BIT(12)
93 #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13)
94 #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14)
96 #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY BIT(0)
97 #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN BIT(1)
98 #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD BIT(2)
99 #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED BIT(3)
100 #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED BIT(4)
101 #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED BIT(5)
102 #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL BIT(8)
103 #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN BIT(9)
104 #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED BIT(10)
105 #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED BIT(11)
106 #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED BIT(12)
107 #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L BIT(13)
108 #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H BIT(14)
113 #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT BIT(25)
114 #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER BIT(26)