Lines Matching +full:in +full:- +full:between

1 # SPDX-License-Identifier: GPL-2.0-only
5 	  Mailbox is a framework to control hardware communication between
6 	  on-chip processors through queued messages and interrupt driven
17 	  used in Secure mode only.
24 	  which provides unidirectional mailboxes between processing elements.
33 	  which provides unidirectional mailboxes between processing elements.
37 	  will be discovered and possibly managed at probe-time.
53 	  which can be used in Secure mode only.
61 	  send short messages between Highbank's A9 cores and the EnergyCore
71 	  running on the Cortex-M3 rWTM secure processor of the Armada 37xx
80 	  interprocessor communication involving DSP, IVA1.0 and IVA2 in
81 	  OMAP2/3; or IPU, IVA HD and DSP in OMAP4/5. Say Y here if you
88 	  This driver provides support for inter-processor communication
89 	  between CPU cores and MCU processor on Some Rockchip SOCs.
99 	  between the OS and a platform such as the BMC. This medium
110 	  to send message between processors. Say Y here if you want to use the
136 	  and K3 architecture SoCs. These may be used for communication between
147 	  between application processors and other processors/MCU/DSP. Select
157 	  between application processors and MCU. Say Y here if you want to
176 	  module will be called mailbox-mpfs.
185 	  providing an interface for invoking the inter-process communication
193 	  between different remote processors and host processors on Tegra186
198 	tristate "APM SoC X-Gene SLIMpro Mailbox Controller"
201 	  An implementation of the APM X-Gene Interprocessor Communication
202 	  Mailbox (IPCM) between the ARM 64-bit cores and SLIMpro controller.
203 	  It is used to send short messages between ARM64-bit cores and
205 	  want to use the APM X-Gene SLIMpro IPCM support.
231 	  with hardware for Inter-Processor Communication Controller (IPCC)
232 	  between processors. Say Y here if you want to have this support.
240           between processors with ADSP. It will place the message to share
259 	  between processors with Xilinx ZynqMP IPI. It will place the
268 	  Mailbox implementation for the hardware message box present in
270 	  between the application CPUs and the power management coprocessor.
277 	  to send message between application processors and MCU. Say Y here if
285 	  controller driver enables communication between AP and CPUCP. Say
292 	  Qualcomm Technologies, Inc. Inter-Processor Communication Controller