Lines Matching +full:0 +full:x0f
21 #define LP50XX_DEV_CFG0 0x00
22 #define LP50XX_DEV_CFG1 0x01
23 #define LP50XX_LED_CFG0 0x02
26 #define LP5012_BNK_BRT 0x03
27 #define LP5012_BNKA_CLR 0x04
28 #define LP5012_BNKB_CLR 0x05
29 #define LP5012_BNKC_CLR 0x06
30 #define LP5012_LED0_BRT 0x07
31 #define LP5012_OUT0_CLR 0x0b
32 #define LP5012_RESET 0x17
35 #define LP5024_BNK_BRT 0x03
36 #define LP5024_BNKA_CLR 0x04
37 #define LP5024_BNKB_CLR 0x05
38 #define LP5024_BNKC_CLR 0x06
39 #define LP5024_LED0_BRT 0x07
40 #define LP5024_OUT0_CLR 0x0f
41 #define LP5024_RESET 0x27
44 #define LP5036_LED_CFG1 0x03
45 #define LP5036_BNK_BRT 0x04
46 #define LP5036_BNKA_CLR 0x05
47 #define LP5036_BNKB_CLR 0x06
48 #define LP5036_BNKC_CLR 0x07
49 #define LP5036_LED0_BRT 0x08
50 #define LP5036_OUT0_CLR 0x14
51 #define LP5036_RESET 0x38
53 #define LP50XX_SW_RESET 0xff
67 {LP50XX_DEV_CFG0, 0x0},
68 {LP50XX_DEV_CFG1, 0x3c},
69 {LP50XX_LED_CFG0, 0x0},
70 {LP5012_BNK_BRT, 0xff},
71 {LP5012_BNKA_CLR, 0x0f},
72 {LP5012_BNKB_CLR, 0x0f},
73 {LP5012_BNKC_CLR, 0x0f},
74 {LP5012_LED0_BRT, 0x0f},
75 /* LEDX_BRT registers are all 0xff for defaults */
76 {0x08, 0xff}, {0x09, 0xff}, {0x0a, 0xff},
77 {LP5012_OUT0_CLR, 0x0f},
78 /* OUTX_CLR registers are all 0x0 for defaults */
79 {0x0c, 0x00}, {0x0d, 0x00}, {0x0e, 0x00}, {0x0f, 0x00}, {0x10, 0x00},
80 {0x11, 0x00}, {0x12, 0x00}, {0x13, 0x00}, {0x14, 0x00}, {0x15, 0x00},
81 {0x16, 0x00},
82 {LP5012_RESET, 0x00}
86 {LP50XX_DEV_CFG0, 0x0},
87 {LP50XX_DEV_CFG1, 0x3c},
88 {LP50XX_LED_CFG0, 0x0},
89 {LP5024_BNK_BRT, 0xff},
90 {LP5024_BNKA_CLR, 0x0f},
91 {LP5024_BNKB_CLR, 0x0f},
92 {LP5024_BNKC_CLR, 0x0f},
93 {LP5024_LED0_BRT, 0x0f},
94 /* LEDX_BRT registers are all 0xff for defaults */
95 {0x08, 0xff}, {0x09, 0xff}, {0x0a, 0xff}, {0x0b, 0xff}, {0x0c, 0xff},
96 {0x0d, 0xff}, {0x0e, 0xff},
97 {LP5024_OUT0_CLR, 0x0f},
98 /* OUTX_CLR registers are all 0x0 for defaults */
99 {0x10, 0x00}, {0x11, 0x00}, {0x12, 0x00}, {0x13, 0x00}, {0x14, 0x00},
100 {0x15, 0x00}, {0x16, 0x00}, {0x17, 0x00}, {0x18, 0x00}, {0x19, 0x00},
101 {0x1a, 0x00}, {0x1b, 0x00}, {0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00},
102 {0x1f, 0x00}, {0x20, 0x00}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00},
103 {0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00},
104 {LP5024_RESET, 0x00}
108 {LP50XX_DEV_CFG0, 0x0},
109 {LP50XX_DEV_CFG1, 0x3c},
110 {LP50XX_LED_CFG0, 0x0},
111 {LP5036_LED_CFG1, 0x0},
112 {LP5036_BNK_BRT, 0xff},
113 {LP5036_BNKA_CLR, 0x0f},
114 {LP5036_BNKB_CLR, 0x0f},
115 {LP5036_BNKC_CLR, 0x0f},
116 {LP5036_LED0_BRT, 0x0f},
117 /* LEDX_BRT registers are all 0xff for defaults */
118 {0x08, 0xff}, {0x09, 0xff}, {0x0a, 0xff}, {0x0b, 0xff}, {0x0c, 0xff},
119 {0x0d, 0xff}, {0x0e, 0xff}, {0x0f, 0xff}, {0x10, 0xff}, {0x11, 0xff},
120 {0x12, 0xff}, {0x13, 0xff},
121 {LP5036_OUT0_CLR, 0x0f},
122 /* OUTX_CLR registers are all 0x0 for defaults */
123 {0x15, 0x00}, {0x16, 0x00}, {0x17, 0x00}, {0x18, 0x00}, {0x19, 0x00},
124 {0x1a, 0x00}, {0x1b, 0x00}, {0x1c, 0x00}, {0x1d, 0x00}, {0x1e, 0x00},
125 {0x1f, 0x00}, {0x20, 0x00}, {0x21, 0x00}, {0x22, 0x00}, {0x23, 0x00},
126 {0x24, 0x00}, {0x25, 0x00}, {0x26, 0x00}, {0x27, 0x00}, {0x28, 0x00},
127 {0x29, 0x00}, {0x2a, 0x00}, {0x2b, 0x00}, {0x2c, 0x00}, {0x2d, 0x00},
128 {0x2e, 0x00}, {0x2f, 0x00}, {0x30, 0x00}, {0x31, 0x00}, {0x32, 0x00},
129 {0x33, 0x00}, {0x34, 0x00}, {0x35, 0x00}, {0x36, 0x00}, {0x37, 0x00},
130 {LP5036_RESET, 0x00}
308 int ret = 0; in lp50xx_brightness_set()
325 for (i = 0; i < led->mc_cdev.num_colors; i++) { in lp50xx_brightness_set()
349 u32 bank_enable_mask = 0; in lp50xx_set_banks()
353 for (i = 0; i < priv->chip_info->max_modules; i++) { in lp50xx_set_banks()
387 return regmap_write(priv->regmap, LP50XX_DEV_CFG0, 0); in lp50xx_enable_disable()
394 u32 led_banks[LP5036_MAX_LED_MODULES] = {0}; in lp50xx_probe_leds()
432 return 0; in lp50xx_probe_leds()
446 int i = 0; in lp50xx_probe_dt()
460 if (ret < 0) { in lp50xx_probe_dt()
470 num_colors = 0; in lp50xx_probe_dt()
512 return 0; in lp50xx_probe_dt()
566 ret = lp50xx_enable_disable(led, 0); in lp50xx_remove()