Lines Matching full:hw
103 spinlock_t lock; /* HW access lock */
268 struct inf_hw *hw = dev_id; in diva_irq() local
271 spin_lock(&hw->lock); in diva_irq()
272 val = inb((u32)hw->cfg.start + DIVA_PCI_CTRL); in diva_irq()
274 spin_unlock(&hw->lock); in diva_irq()
277 hw->irqcnt++; in diva_irq()
278 mISDNipac_irq(&hw->ipac, irqloops); in diva_irq()
279 spin_unlock(&hw->lock); in diva_irq()
286 struct inf_hw *hw = dev_id; in diva20x_irq() local
289 spin_lock(&hw->lock); in diva20x_irq()
290 val = readb(hw->cfg.p); in diva20x_irq()
292 spin_unlock(&hw->lock); in diva20x_irq()
295 hw->irqcnt++; in diva20x_irq()
296 mISDNipac_irq(&hw->ipac, irqloops); in diva20x_irq()
297 writeb(PITA_INT0_STATUS, hw->cfg.p); /* ACK PITA INT0 */ in diva20x_irq()
298 spin_unlock(&hw->lock); in diva20x_irq()
305 struct inf_hw *hw = dev_id; in tiger_irq() local
308 spin_lock(&hw->lock); in tiger_irq()
309 val = inb((u32)hw->cfg.start + TIGER_AUX_STATUS); in tiger_irq()
311 spin_unlock(&hw->lock); in tiger_irq()
314 hw->irqcnt++; in tiger_irq()
315 mISDNipac_irq(&hw->ipac, irqloops); in tiger_irq()
316 spin_unlock(&hw->lock); in tiger_irq()
323 struct inf_hw *hw = dev_id; in elsa_irq() local
326 spin_lock(&hw->lock); in elsa_irq()
327 val = inb((u32)hw->cfg.start + ELSA_IRQ_ADDR); in elsa_irq()
329 spin_unlock(&hw->lock); in elsa_irq()
332 hw->irqcnt++; in elsa_irq()
333 mISDNipac_irq(&hw->ipac, irqloops); in elsa_irq()
334 spin_unlock(&hw->lock); in elsa_irq()
341 struct inf_hw *hw = dev_id; in niccy_irq() local
344 spin_lock(&hw->lock); in niccy_irq()
345 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
347 spin_unlock(&hw->lock); in niccy_irq()
350 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in niccy_irq()
351 hw->irqcnt++; in niccy_irq()
352 mISDNipac_irq(&hw->ipac, irqloops); in niccy_irq()
353 spin_unlock(&hw->lock); in niccy_irq()
360 struct inf_hw *hw = dev_id; in gazel_irq() local
363 spin_lock(&hw->lock); in gazel_irq()
364 ret = mISDNipac_irq(&hw->ipac, irqloops); in gazel_irq()
365 spin_unlock(&hw->lock); in gazel_irq()
372 struct inf_hw *hw = dev_id; in ipac_irq() local
375 spin_lock(&hw->lock); in ipac_irq()
376 val = hw->ipac.read_reg(hw, IPAC_ISTA); in ipac_irq()
378 spin_unlock(&hw->lock); in ipac_irq()
381 hw->irqcnt++; in ipac_irq()
382 mISDNipac_irq(&hw->ipac, irqloops); in ipac_irq()
383 spin_unlock(&hw->lock); in ipac_irq()
388 enable_hwirq(struct inf_hw *hw) in enable_hwirq() argument
393 switch (hw->ci->typ) { in enable_hwirq()
396 writel(PITA_INT0_ENABLE, hw->cfg.p); in enable_hwirq()
400 outb(TIGER_IRQ_BIT, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in enable_hwirq()
403 outb(QS1000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
406 outb(QS3000_IRQ_ON, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in enable_hwirq()
409 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
411 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in enable_hwirq()
414 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
416 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in enable_hwirq()
420 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
424 (u32)hw->cfg.start + GAZEL_INCSR); in enable_hwirq()
432 disable_hwirq(struct inf_hw *hw) in disable_hwirq() argument
437 switch (hw->ci->typ) { in disable_hwirq()
440 writel(0, hw->cfg.p); in disable_hwirq()
444 outb(0, (u32)hw->cfg.start + TIGER_AUX_IRQMASK); in disable_hwirq()
447 outb(QS1000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
450 outb(QS3000_IRQ_OFF, (u32)hw->cfg.start + ELSA_IRQ_ADDR); in disable_hwirq()
453 val = inl((u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
455 outl(val, (u32)hw->cfg.start + NICCY_IRQ_CTRL_REG); in disable_hwirq()
458 w = inw((u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
460 outw(w, (u32)hw->cfg.start + SCT_PLX_IRQ_ADDR); in disable_hwirq()
464 outb(0, (u32)hw->cfg.start + GAZEL_INCSR); in disable_hwirq()
472 ipac_chip_reset(struct inf_hw *hw) in ipac_chip_reset() argument
474 hw->ipac.write_reg(hw, IPAC_POTA2, 0x20); in ipac_chip_reset()
476 hw->ipac.write_reg(hw, IPAC_POTA2, 0x00); in ipac_chip_reset()
478 hw->ipac.write_reg(hw, IPAC_CONF, hw->ipac.conf); in ipac_chip_reset()
479 hw->ipac.write_reg(hw, IPAC_MASK, 0xc0); in ipac_chip_reset()
483 reset_inf(struct inf_hw *hw) in reset_inf() argument
489 pr_notice("%s: resetting card\n", hw->name); in reset_inf()
490 switch (hw->ci->typ) { in reset_inf()
493 outb(0, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
495 outb(DIVA_RESET_BIT, (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
498 outb(9, (u32)hw->cfg.start + 0x69); in reset_inf()
500 (u32)hw->cfg.start + DIVA_PCI_CTRL); in reset_inf()
504 hw->cfg.p + PITA_MISC_REG); in reset_inf()
506 writel(PITA_PARA_MPX_MODE, hw->cfg.p + PITA_MISC_REG); in reset_inf()
511 hw->cfg.p + PITA_MISC_REG); in reset_inf()
514 hw->cfg.p + PITA_MISC_REG); in reset_inf()
519 ipac_chip_reset(hw); in reset_inf()
520 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); in reset_inf()
521 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); in reset_inf()
522 hw->ipac.write_reg(hw, IPAC_PCFG, 0x12); in reset_inf()
526 ipac_chip_reset(hw); in reset_inf()
527 hw->ipac.write_reg(hw, IPAC_ACFG, 0x00); in reset_inf()
528 hw->ipac.write_reg(hw, IPAC_AOE, 0x3c); in reset_inf()
529 hw->ipac.write_reg(hw, IPAC_ATX, 0xff); in reset_inf()
534 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
536 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
538 w = inw((u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
540 outw(w, (u32)hw->cfg.start + SCT_PLX_RESET_ADDR); in reset_inf()
544 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
546 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
549 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
551 hw->ipac.isac.adf2 = 0x87; in reset_inf()
552 hw->ipac.hscx[0].slot = 0x1f; in reset_inf()
553 hw->ipac.hscx[1].slot = 0x23; in reset_inf()
556 val = inl((u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
558 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
561 outl(val, (u32)hw->cfg.start + GAZEL_CNTRL); in reset_inf()
563 ipac_chip_reset(hw); in reset_inf()
564 hw->ipac.write_reg(hw, IPAC_ACFG, 0xff); in reset_inf()
565 hw->ipac.write_reg(hw, IPAC_AOE, 0x00); in reset_inf()
566 hw->ipac.conf = 0x01; /* IOM off */ in reset_inf()
571 enable_hwirq(hw); in reset_inf()
575 inf_ctrl(struct inf_hw *hw, u32 cmd, u_long arg) in inf_ctrl() argument
581 reset_inf(hw); in inf_ctrl()
585 hw->name, __func__, cmd, arg); in inf_ctrl()
593 init_irq(struct inf_hw *hw) in init_irq() argument
598 if (!hw->ci->irqfunc) in init_irq()
600 ret = request_irq(hw->irq, hw->ci->irqfunc, IRQF_SHARED, hw->name, hw); in init_irq()
602 pr_info("%s: couldn't get interrupt %d\n", hw->name, hw->irq); in init_irq()
606 spin_lock_irqsave(&hw->lock, flags); in init_irq()
607 reset_inf(hw); in init_irq()
608 ret = hw->ipac.init(&hw->ipac); in init_irq()
610 spin_unlock_irqrestore(&hw->lock, flags); in init_irq()
612 hw->name, ret); in init_irq()
615 spin_unlock_irqrestore(&hw->lock, flags); in init_irq()
618 pr_notice("%s: IRQ %d count %d\n", hw->name, in init_irq()
619 hw->irq, hw->irqcnt); in init_irq()
620 if (!hw->irqcnt) { in init_irq()
622 hw->name, hw->irq, 3 - cnt); in init_irq()
626 free_irq(hw->irq, hw); in init_irq()
631 release_io(struct inf_hw *hw) in release_io() argument
633 if (hw->cfg.mode) { in release_io()
634 if (hw->cfg.mode == AM_MEMIO) { in release_io()
635 release_mem_region(hw->cfg.start, hw->cfg.size); in release_io()
636 if (hw->cfg.p) in release_io()
637 iounmap(hw->cfg.p); in release_io()
639 release_region(hw->cfg.start, hw->cfg.size); in release_io()
640 hw->cfg.mode = AM_NONE; in release_io()
642 if (hw->addr.mode) { in release_io()
643 if (hw->addr.mode == AM_MEMIO) { in release_io()
644 release_mem_region(hw->addr.start, hw->addr.size); in release_io()
645 if (hw->addr.p) in release_io()
646 iounmap(hw->addr.p); in release_io()
648 release_region(hw->addr.start, hw->addr.size); in release_io()
649 hw->addr.mode = AM_NONE; in release_io()
654 setup_io(struct inf_hw *hw) in setup_io() argument
658 if (hw->ci->cfg_mode) { in setup_io()
659 hw->cfg.start = pci_resource_start(hw->pdev, hw->ci->cfg_bar); in setup_io()
660 hw->cfg.size = pci_resource_len(hw->pdev, hw->ci->cfg_bar); in setup_io()
661 if (hw->ci->cfg_mode == AM_MEMIO) { in setup_io()
662 if (!request_mem_region(hw->cfg.start, hw->cfg.size, in setup_io()
663 hw->name)) in setup_io()
666 if (!request_region(hw->cfg.start, hw->cfg.size, in setup_io()
667 hw->name)) in setup_io()
672 "already in use\n", hw->name, in setup_io()
673 (ulong)hw->cfg.start, (ulong)hw->cfg.size); in setup_io()
676 hw->cfg.mode = hw->ci->cfg_mode; in setup_io()
677 if (hw->ci->cfg_mode == AM_MEMIO) { in setup_io()
678 hw->cfg.p = ioremap(hw->cfg.start, hw->cfg.size); in setup_io()
679 if (!hw->cfg.p) in setup_io()
684 hw->name, (ulong)hw->cfg.start, in setup_io()
685 (ulong)hw->cfg.size, hw->ci->cfg_mode); in setup_io()
688 if (hw->ci->addr_mode) { in setup_io()
689 hw->addr.start = pci_resource_start(hw->pdev, hw->ci->addr_bar); in setup_io()
690 hw->addr.size = pci_resource_len(hw->pdev, hw->ci->addr_bar); in setup_io()
691 if (hw->ci->addr_mode == AM_MEMIO) { in setup_io()
692 if (!request_mem_region(hw->addr.start, hw->addr.size, in setup_io()
693 hw->name)) in setup_io()
696 if (!request_region(hw->addr.start, hw->addr.size, in setup_io()
697 hw->name)) in setup_io()
702 "already in use\n", hw->name, in setup_io()
703 (ulong)hw->addr.start, (ulong)hw->addr.size); in setup_io()
706 hw->addr.mode = hw->ci->addr_mode; in setup_io()
707 if (hw->ci->addr_mode == AM_MEMIO) { in setup_io()
708 hw->addr.p = ioremap(hw->addr.start, hw->addr.size); in setup_io()
709 if (!hw->addr.p) in setup_io()
714 hw->name, (ulong)hw->addr.start, in setup_io()
715 (ulong)hw->addr.size, hw->ci->addr_mode); in setup_io()
719 switch (hw->ci->typ) { in setup_io()
722 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
723 hw->isac.mode = hw->cfg.mode; in setup_io()
724 hw->isac.a.io.ale = (u32)hw->cfg.start + DIVA_ISAC_ALE; in setup_io()
725 hw->isac.a.io.port = (u32)hw->cfg.start + DIVA_ISAC_PORT; in setup_io()
726 hw->hscx.mode = hw->cfg.mode; in setup_io()
727 hw->hscx.a.io.ale = (u32)hw->cfg.start + DIVA_HSCX_ALE; in setup_io()
728 hw->hscx.a.io.port = (u32)hw->cfg.start + DIVA_HSCX_PORT; in setup_io()
731 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
732 hw->ipac.isac.off = 0x80; in setup_io()
733 hw->isac.mode = hw->addr.mode; in setup_io()
734 hw->isac.a.p = hw->addr.p; in setup_io()
735 hw->hscx.mode = hw->addr.mode; in setup_io()
736 hw->hscx.a.p = hw->addr.p; in setup_io()
739 hw->ipac.type = IPAC_TYPE_IPACX; in setup_io()
740 hw->isac.mode = hw->addr.mode; in setup_io()
741 hw->isac.a.p = hw->addr.p; in setup_io()
742 hw->hscx.mode = hw->addr.mode; in setup_io()
743 hw->hscx.a.p = hw->addr.p; in setup_io()
747 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
748 hw->ipac.isac.off = 0x80; in setup_io()
749 hw->isac.mode = hw->cfg.mode; in setup_io()
750 hw->isac.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
751 hw->isac.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
752 hw->hscx.mode = hw->cfg.mode; in setup_io()
753 hw->hscx.a.io.ale = (u32)hw->cfg.start + TIGER_IPAC_ALE; in setup_io()
754 hw->hscx.a.io.port = (u32)hw->cfg.start + TIGER_IPAC_PORT; in setup_io()
755 outb(0xff, (ulong)hw->cfg.start); in setup_io()
757 outb(0x00, (ulong)hw->cfg.start); in setup_io()
759 outb(TIGER_IOMASK, (ulong)hw->cfg.start + TIGER_AUX_CTRL); in setup_io()
763 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
764 hw->ipac.isac.off = 0x80; in setup_io()
765 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
766 hw->isac.a.io.port = (u32)hw->addr.start + 1; in setup_io()
767 hw->isac.mode = hw->addr.mode; in setup_io()
768 hw->hscx.a.io.ale = (u32)hw->addr.start; in setup_io()
769 hw->hscx.a.io.port = (u32)hw->addr.start + 1; in setup_io()
770 hw->hscx.mode = hw->addr.mode; in setup_io()
773 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
774 hw->isac.mode = hw->addr.mode; in setup_io()
775 hw->isac.a.io.ale = (u32)hw->addr.start + NICCY_ISAC_ALE; in setup_io()
776 hw->isac.a.io.port = (u32)hw->addr.start + NICCY_ISAC_PORT; in setup_io()
777 hw->hscx.mode = hw->addr.mode; in setup_io()
778 hw->hscx.a.io.ale = (u32)hw->addr.start + NICCY_HSCX_ALE; in setup_io()
779 hw->hscx.a.io.port = (u32)hw->addr.start + NICCY_HSCX_PORT; in setup_io()
782 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
783 hw->ipac.isac.off = 0x80; in setup_io()
784 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
785 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
786 hw->isac.mode = hw->addr.mode; in setup_io()
787 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
788 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
789 hw->hscx.mode = hw->addr.mode; in setup_io()
792 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
793 hw->ipac.isac.off = 0x80; in setup_io()
794 hw->isac.a.io.ale = (u32)hw->addr.start + 0x08; in setup_io()
795 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
796 hw->isac.mode = hw->addr.mode; in setup_io()
797 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
798 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
799 hw->hscx.mode = hw->addr.mode; in setup_io()
802 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
803 hw->ipac.isac.off = 0x80; in setup_io()
804 hw->isac.a.io.ale = (u32)hw->addr.start + 0x10; in setup_io()
805 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
806 hw->isac.mode = hw->addr.mode; in setup_io()
807 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
808 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
809 hw->hscx.mode = hw->addr.mode; in setup_io()
812 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
813 hw->ipac.isac.off = 0x80; in setup_io()
814 hw->isac.a.io.ale = (u32)hw->addr.start + 0x20; in setup_io()
815 hw->isac.a.io.port = hw->isac.a.io.ale + 4; in setup_io()
816 hw->isac.mode = hw->addr.mode; in setup_io()
817 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
818 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
819 hw->hscx.mode = hw->addr.mode; in setup_io()
822 hw->ipac.type = IPAC_TYPE_ISAC | IPAC_TYPE_HSCX; in setup_io()
823 hw->ipac.isac.off = 0x80; in setup_io()
824 hw->isac.mode = hw->addr.mode; in setup_io()
825 hw->isac.a.io.port = (u32)hw->addr.start; in setup_io()
826 hw->hscx.mode = hw->addr.mode; in setup_io()
827 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
830 hw->ipac.type = IPAC_TYPE_IPAC; in setup_io()
831 hw->ipac.isac.off = 0x80; in setup_io()
832 hw->isac.mode = hw->addr.mode; in setup_io()
833 hw->isac.a.io.ale = (u32)hw->addr.start; in setup_io()
834 hw->isac.a.io.port = (u32)hw->addr.start + GAZEL_IPAC_DATA_PORT; in setup_io()
835 hw->hscx.mode = hw->addr.mode; in setup_io()
836 hw->hscx.a.io.ale = hw->isac.a.io.ale; in setup_io()
837 hw->hscx.a.io.port = hw->isac.a.io.port; in setup_io()
842 switch (hw->isac.mode) { in setup_io()
844 ASSIGN_FUNC_IPAC(MIO, hw->ipac); in setup_io()
847 ASSIGN_FUNC_IPAC(IND, hw->ipac); in setup_io()
850 ASSIGN_FUNC_IPAC(IO, hw->ipac); in setup_io()