1 // SPDX-License-Identifier: GPL-2.0-only
3  * Copyright (C) 2014-2015 Toradex AG
9  * one of the two available CPU's on Vybrid VF6xx SoC's (Cortex-A5 or
10  * Cortex-M4). The router will be configured transparently on a IRQ
14  *   CPU 0, CPU 1 or both. The routing is useful for dual-core
18  * o It is required to setup the interrupt router even on single-core
28 #include <dt-bindings/interrupt-controller/arm-gic.h>
55 		data->saved_irsprc[i] = readw_relaxed(data->mscm_ir_base + MSCM_IRSPRC(i));  in vf610_mscm_ir_save()
63 		writew_relaxed(data->saved_irsprc[i], data->mscm_ir_base + MSCM_IRSPRC(i));  in vf610_mscm_ir_restore()
88 	irq_hw_number_t hwirq = data->hwirq;  in vf610_mscm_ir_enable()
89 	struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;  in vf610_mscm_ir_enable()
92 	irsprc = readw_relaxed(chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));  in vf610_mscm_ir_enable()
95 	WARN_ON(irsprc & ~chip_data->cpu_mask);  in vf610_mscm_ir_enable()
97 	writew_relaxed(chip_data->cpu_mask,  in vf610_mscm_ir_enable()
98 		       chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));  in vf610_mscm_ir_enable()
105 	irq_hw_number_t hwirq = data->hwirq;  in vf610_mscm_ir_disable()
106 	struct vf610_mscm_ir_chip_data *chip_data = data->chip_data;  in vf610_mscm_ir_disable()
108 	writew_relaxed(0x0, chip_data->mscm_ir_base + MSCM_IRSPRC(hwirq));  in vf610_mscm_ir_disable()
114 	.name			= "mscm-ir",
132 	if (!irq_domain_get_of_node(domain->parent))  in vf610_mscm_ir_domain_alloc()
133 		return -EINVAL;  in vf610_mscm_ir_domain_alloc()
135 	if (fwspec->param_count != 2)  in vf610_mscm_ir_domain_alloc()
136 		return -EINVAL;  in vf610_mscm_ir_domain_alloc()
138 	hwirq = fwspec->param[0];  in vf610_mscm_ir_domain_alloc()
142 					      domain->host_data);  in vf610_mscm_ir_domain_alloc()
144 	parent_fwspec.fwnode = domain->parent->fwnode;  in vf610_mscm_ir_domain_alloc()
146 	if (mscm_ir_data->is_nvic) {  in vf610_mscm_ir_domain_alloc()
148 		parent_fwspec.param[0] = fwspec->param[0];  in vf610_mscm_ir_domain_alloc()
152 		parent_fwspec.param[1] = fwspec->param[0];  in vf610_mscm_ir_domain_alloc()
153 		parent_fwspec.param[2] = fwspec->param[1];  in vf610_mscm_ir_domain_alloc()
165 	if (WARN_ON(fwspec->param_count < 2))  in vf610_mscm_ir_domain_translate()
166 		return -EINVAL;  in vf610_mscm_ir_domain_translate()
167 	*hwirq = fwspec->param[0];  in vf610_mscm_ir_domain_translate()
168 	*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;  in vf610_mscm_ir_domain_translate()
187 		pr_err("vf610_mscm_ir: interrupt-parent not found\n");  in vf610_mscm_ir_of_init()
188 		return -EINVAL;  in vf610_mscm_ir_of_init()
193 		return -ENOMEM;  in vf610_mscm_ir_of_init()
195 	mscm_ir_data->mscm_ir_base = of_io_request_and_map(node, 0, "mscm-ir");  in vf610_mscm_ir_of_init()
196 	if (IS_ERR(mscm_ir_data->mscm_ir_base)) {  in vf610_mscm_ir_of_init()
198 		ret = PTR_ERR(mscm_ir_data->mscm_ir_base);  in vf610_mscm_ir_of_init()
210 	mscm_ir_data->cpu_mask = 0x1 << cpuid;  in vf610_mscm_ir_of_init()
216 		ret = -ENOMEM;  in vf610_mscm_ir_of_init()
220 	if (of_device_is_compatible(irq_domain_get_of_node(domain->parent),  in vf610_mscm_ir_of_init()
221 				    "arm,armv7m-nvic"))  in vf610_mscm_ir_of_init()
222 		mscm_ir_data->is_nvic = true;  in vf610_mscm_ir_of_init()
229 	iounmap(mscm_ir_data->mscm_ir_base);  in vf610_mscm_ir_of_init()
234 IRQCHIP_DECLARE(vf610_mscm_ir, "fsl,vf610-mscm-ir", vf610_mscm_ir_of_init);