drivers/irqchip/irq-sun6i-r.c

1 // SPDX-License-Identifier: GPL-2.0-only
3  * The R_INTC in Allwinner A31 and newer SoCs manages several types of
7  *              bit 0                  bits 1-15^           bits 19-31
9  *   +---------+                      +---------+    +---------+  +---------+
11  *   +---------+                      +---------+    +---------+  +---------+
14  * +------V------+ +------------+       |     |         | +--V------V--+ |
17  * +-------------+ +------------+       |     |         | +------------+ |
19  *         +--V-------V--+           +--V--+  |      +--V--+    |     +--V--+
21  *         |    Latch    |           | SPI |  |      | SPI |... |  ...| SPI |
22  *         +-------------+           | N+d |  |      |  m  |    |     | m+7 |
23  *             |     |               +-----+  |      +-----+    |     +-----+
25  *     +-------V-+ +-V----------+   +---------V--+     +--------V--------+
26  *     | GIC SPI | |  AND with  |   |  AND with  |     |    AND with     |
28  *     +---------+ +------------+   +------------+     +-----------------+
30  *                 +------V-----+   +------V-----+     +--------V--------+
33  *                 +------------+   +------------+     +-----------------+
35  * ^ bits 16-18 are direct IRQs for peripherals with banked interrupts, such as
36  *   the MSGBOX. These IRQs do not map to any GIC SPI.
39  * set of 128 mux bits. This requires a second set of top-level registers.
52 #include <dt-bindings/interrupt-controller/arm-gic.h>
94 		data->chip_data = SUN6I_NMI_NEEDS_ACK;  in sun6i_r_intc_nmi_ack()
100 	if (data->chip_data == SUN6I_NMI_NEEDS_ACK && !irqd_irq_masked(data)) {  in sun6i_r_intc_nmi_eoi()
101 		data->chip_data = NULL;  in sun6i_r_intc_nmi_eoi()
110 	if (data->chip_data == SUN6I_NMI_NEEDS_ACK) {  in sun6i_r_intc_nmi_unmask()
111 		data->chip_data = NULL;  in sun6i_r_intc_nmi_unmask()
136 		return -EINVAL;  in sun6i_r_intc_nmi_set_type()
161 	unsigned long offset_from_nmi = data->hwirq - nmi_hwirq;  in sun6i_r_intc_irq_set_wake()
165 	else if (test_bit(data->hwirq, wake_mux_valid))  in sun6i_r_intc_irq_set_wake()
166 		assign_bit(data->hwirq, wake_mux_enabled, on);  in sun6i_r_intc_irq_set_wake()
169 		return -EPERM;  in sun6i_r_intc_irq_set_wake()
175 	.name			= "sun6i-r-intc",
188 	.name			= "sun6i-r-intc",
203 	/* Accept the old two-cell binding for the NMI only. */  in sun6i_r_intc_domain_translate()
204 	if (fwspec->param_count == 2 && fwspec->param[0] == 0) {  in sun6i_r_intc_domain_translate()
206 		*type  = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;  in sun6i_r_intc_domain_translate()
210 	/* Otherwise this binding should match the GIC SPI binding. */  in sun6i_r_intc_domain_translate()
211 	if (fwspec->param_count < 3)  in sun6i_r_intc_domain_translate()
212 		return -EINVAL;  in sun6i_r_intc_domain_translate()
213 	if (fwspec->param[0] != GIC_SPI)  in sun6i_r_intc_domain_translate()
214 		return -EINVAL;  in sun6i_r_intc_domain_translate()
216 	*hwirq = fwspec->param[1];  in sun6i_r_intc_domain_translate()
217 	*type  = fwspec->param[2] & IRQ_TYPE_SENSE_MASK;  in sun6i_r_intc_domain_translate()
236 		return -EINVAL;  in sun6i_r_intc_domain_alloc()
238 	/* Construct a GIC-compatible fwspec from this fwspec. */  in sun6i_r_intc_domain_alloc()
240 		.fwnode      = domain->parent->fwnode,  in sun6i_r_intc_domain_alloc()
323 		return -EINVAL;  in sun6i_r_intc_init()
326 	bitmap_set(wake_irq_enabled, v->first_mux_irq, v->nr_mux_irqs);  in sun6i_r_intc_init()
327 	bitmap_from_arr32(wake_mux_valid, v->mux_valid, SUN6I_NR_MUX_BITS);  in sun6i_r_intc_init()
332 		return -ENXIO;  in sun6i_r_intc_init()
346 		return -ENOMEM;  in sun6i_r_intc_init()
368 IRQCHIP_DECLARE(sun6i_a31_r_intc, "allwinner,sun6i-a31-r-intc", sun6i_a31_r_intc_init);
381 IRQCHIP_DECLARE(sun50i_h6_r_intc, "allwinner,sun50i-h6-r-intc", sun50i_h6_r_intc_init);