1 // SPDX-License-Identifier: GPL-2.0
10 #include <linux/interrupt.h>
19 #include <dt-bindings/interrupt-controller/arm-gic.h>
23 #define ICR0			0	/* Interrupt Control Register 0 */
27 #define ICR0_NMIF		BIT(1)	/* NMI Interrupt Request */
29 #define ICR1			2	/* Interrupt Control Register 1 */
38 #define IRQRR			4	/* IRQ Interrupt Request Register */
43 	void __iomem *base;  member
51 	return data->domain->host_data;  in irq_data_to_priv()
60 	tmp = readw_relaxed(priv->base + IRQRR);  in rza1_irqc_eoi()
62 		writew_relaxed(GENMASK(IRQC_NUM_IRQ - 1, 0) & ~bit,  in rza1_irqc_eoi()
63 			       priv->base + IRQRR);  in rza1_irqc_eoi()
92 		return -EINVAL;  in rza1_irqc_set_type()
95 	tmp = readw_relaxed(priv->base + ICR1);  in rza1_irqc_set_type()
98 	writew_relaxed(tmp, priv->base + ICR1);  in rza1_irqc_set_type()
105 	struct rza1_irqc_priv *priv = domain->host_data;  in rza1_irqc_alloc()
107 	unsigned int hwirq = fwspec->param[0];  in rza1_irqc_alloc()
112 	ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &priv->chip,  in rza1_irqc_alloc()
117 	spec.fwnode = &priv->dev->of_node->fwnode;  in rza1_irqc_alloc()
118 	spec.param_count = priv->map[hwirq].args_count;  in rza1_irqc_alloc()
120 		spec.param[i] = priv->map[hwirq].args[i];  in rza1_irqc_alloc()
129 	if (fwspec->param_count != 2 || fwspec->param[0] >= IRQC_NUM_IRQ)  in rza1_irqc_translate()
130 		return -EINVAL;  in rza1_irqc_translate()
132 	*hwirq = fwspec->param[0];  in rza1_irqc_translate()
133 	*type = fwspec->param[1];  in rza1_irqc_translate()
146 	struct device *dev = priv->dev;  in rza1_irqc_parse_map()
151 	imap = of_get_property(dev->of_node, "interrupt-map", &imaplen);  in rza1_irqc_parse_map()
153 		return -EINVAL;  in rza1_irqc_parse_map()
157 			return -EINVAL;  in rza1_irqc_parse_map()
159 		/* Check interrupt number, ignore sense */  in rza1_irqc_parse_map()
161 			return -EINVAL;  in rza1_irqc_parse_map()
166 			return -EINVAL;  in rza1_irqc_parse_map()
170 		imaplen -= 3;  in rza1_irqc_parse_map()
172 		ret = of_property_read_u32(ipar, "#interrupt-cells", &intsize);  in rza1_irqc_parse_map()
178 			return -EINVAL;  in rza1_irqc_parse_map()
180 		priv->map[i].args_count = intsize;  in rza1_irqc_parse_map()
182 			priv->map[i].args[j] = be32_to_cpup(imap++);  in rza1_irqc_parse_map()
184 		imaplen -= intsize;  in rza1_irqc_parse_map()
192 	struct device *dev = &pdev->dev;  in rza1_irqc_probe()
193 	struct device_node *np = dev->of_node;  in rza1_irqc_probe()
194 	struct irq_domain *parent = NULL;  in rza1_irqc_probe()  local
201 		return -ENOMEM;  in rza1_irqc_probe()
204 	priv->dev = dev;  in rza1_irqc_probe()
206 	priv->base = devm_platform_ioremap_resource(pdev, 0);  in rza1_irqc_probe()
207 	if (IS_ERR(priv->base))  in rza1_irqc_probe()
208 		return PTR_ERR(priv->base);  in rza1_irqc_probe()
212 		parent = irq_find_host(gic_node);  in rza1_irqc_probe()
214 	if (!parent) {  in rza1_irqc_probe()
215 		dev_err(dev, "cannot find parent domain\n");  in rza1_irqc_probe()
216 		ret = -ENODEV;  in rza1_irqc_probe()
222 		dev_err(dev, "cannot parse %s: %d\n", "interrupt-map", ret);  in rza1_irqc_probe()
226 	priv->chip.name = "rza1-irqc";  in rza1_irqc_probe()
227 	priv->chip.irq_mask = irq_chip_mask_parent;  in rza1_irqc_probe()
228 	priv->chip.irq_unmask = irq_chip_unmask_parent;  in rza1_irqc_probe()
229 	priv->chip.irq_eoi = rza1_irqc_eoi;  in rza1_irqc_probe()
230 	priv->chip.irq_retrigger = irq_chip_retrigger_hierarchy;  in rza1_irqc_probe()
231 	priv->chip.irq_set_type = rza1_irqc_set_type;  in rza1_irqc_probe()
232 	priv->chip.flags = IRQCHIP_MASK_ON_SUSPEND | IRQCHIP_SKIP_SET_WAKE;  in rza1_irqc_probe()
234 	priv->irq_domain = irq_domain_add_hierarchy(parent, 0, IRQC_NUM_IRQ,  in rza1_irqc_probe()
237 	if (!priv->irq_domain) {  in rza1_irqc_probe()
239 		ret = -ENOMEM;  in rza1_irqc_probe()
251 	irq_domain_remove(priv->irq_domain);  in rza1_irqc_remove()
255 	{ .compatible = "renesas,rza1-irqc" },