2  * Marvell Orion SoCs IRQ chip driver.
21  * Orion SoC main interrupt controller
35 	struct irq_domain_chip_generic *dgc = orion_irq_domain->gc;  in orion_handle_irq()
38 	for (n = 0; n < dgc->num_chips; n++, base += ORION_IRQS_PER_CHIP) {  in orion_handle_irq()
41 		u32 stat = readl_relaxed(gc->reg_base + ORION_IRQ_CAUSE) &  in orion_handle_irq()
42 			gc->mask_cache;  in orion_handle_irq()
46 						  gc->irq_base + hwirq);  in orion_handle_irq()
69 				ORION_IRQS_PER_CHIP, 1, np->full_name,  in orion_irq_init()
81 		if (!request_mem_region(r.start, resource_size(&r), np->name))  in orion_irq_init()
85 		gc->reg_base = ioremap(r.start, resource_size(&r));  in orion_irq_init()
86 		if (!gc->reg_base)  in orion_irq_init()
89 		gc->chip_types[0].regs.mask = ORION_IRQ_MASK;  in orion_irq_init()
90 		gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;  in orion_irq_init()
91 		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;  in orion_irq_init()
94 		writel(0, gc->reg_base + ORION_IRQ_MASK);  in orion_irq_init()
100 IRQCHIP_DECLARE(orion_intc, "marvell,orion-intc", orion_irq_init);
103  * Orion SoC bridge interrupt controller
113 	u32 stat = readl_relaxed(gc->reg_base + ORION_BRIDGE_IRQ_CAUSE) &  in orion_bridge_irq_handler()
114 		   gc->mask_cache;  in orion_bridge_irq_handler()
119 		generic_handle_domain_irq(d, gc->irq_base + hwirq);  in orion_bridge_irq_handler()
132 	ct->chip.irq_ack(d);  in orion_bridge_irq_startup()
133 	ct->chip.irq_unmask(d);  in orion_bridge_irq_startup()
153 		return -ENOMEM;  in orion_bridge_irq_init()
156 	ret = irq_alloc_domain_generic_chips(domain, nrirqs, 1, np->name,  in orion_bridge_irq_init()
169 	if (!request_mem_region(r.start, resource_size(&r), np->name)) {  in orion_bridge_irq_init()
170 		pr_err("%s: unable to request mem region\n", np->name);  in orion_bridge_irq_init()
171 		return -ENOMEM;  in orion_bridge_irq_init()
178 		return -EINVAL;  in orion_bridge_irq_init()
182 	gc->reg_base = ioremap(r.start, resource_size(&r));  in orion_bridge_irq_init()
183 	if (!gc->reg_base) {  in orion_bridge_irq_init()
185 		return -ENOMEM;  in orion_bridge_irq_init()
188 	gc->chip_types[0].regs.ack = ORION_BRIDGE_IRQ_CAUSE;  in orion_bridge_irq_init()
189 	gc->chip_types[0].regs.mask = ORION_BRIDGE_IRQ_MASK;  in orion_bridge_irq_init()
190 	gc->chip_types[0].chip.irq_startup = orion_bridge_irq_startup;  in orion_bridge_irq_init()
191 	gc->chip_types[0].chip.irq_ack = irq_gc_ack_clr_bit;  in orion_bridge_irq_init()
192 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_clr_bit;  in orion_bridge_irq_init()
193 	gc->chip_types[0].chip.irq_unmask = irq_gc_mask_set_bit;  in orion_bridge_irq_init()
196 	writel(0, gc->reg_base + ORION_BRIDGE_IRQ_MASK);  in orion_bridge_irq_init()
197 	writel(0, gc->reg_base + ORION_BRIDGE_IRQ_CAUSE);  in orion_bridge_irq_init()
205 		"marvell,orion-bridge-intc", orion_bridge_irq_init);