drivers/irqchip/irq-mscc-ocelot.c

1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3  * Microsemi Ocelot IRQ controller driver
15 #define ICPU_CFG_INTR_DST_INTR_IDENT(_p, x) ((_p)->reg_off_ident + 0x4 * (x))
16 #define ICPU_CFG_INTR_INTR_TRIGGER(_p, x)   ((_p)->reg_off_trigger + 0x4 * (x))
80 	struct irq_domain *d = data->domain;  in ocelot_irq_unmask()
81 	struct chip_props *p = d->host_data;  in ocelot_irq_unmask()
83 	unsigned int mask = data->mask;  in ocelot_irq_unmask()
96 		irq_reg_writel(gc, mask, p->reg_off_sticky);  in ocelot_irq_unmask()
98 	*ct->mask_cache &= ~mask;  in ocelot_irq_unmask()
99 	irq_reg_writel(gc, mask, p->reg_off_ena_set);  in ocelot_irq_unmask()
107 	struct chip_props *p = d->host_data;  in ocelot_irq_handler()
133 		return -EINVAL;  in vcoreiii_irq_init()
135 	domain = irq_domain_add_linear(node, p->n_irq,  in vcoreiii_irq_init()
139 		return -ENOMEM;  in vcoreiii_irq_init()
142 	ret = irq_alloc_domain_generic_chips(domain, p->n_irq, 1,  in vcoreiii_irq_init()
143 					     "icpu", handle_level_irq,  in vcoreiii_irq_init()
151 	gc->reg_base = of_iomap(node, 0);  in vcoreiii_irq_init()
152 	if (!gc->reg_base) {  in vcoreiii_irq_init()
154 		ret = -ENOMEM;  in vcoreiii_irq_init()
158 	gc->chip_types[0].chip.irq_ack = irq_gc_ack_set_bit;  in vcoreiii_irq_init()
159 	gc->chip_types[0].regs.ack = p->reg_off_sticky;  in vcoreiii_irq_init()
160 	if (p->flags & FLAGS_HAS_TRIGGER) {  in vcoreiii_irq_init()
161 		gc->chip_types[0].regs.mask = p->reg_off_ena_clr;  in vcoreiii_irq_init()
162 		gc->chip_types[0].chip.irq_unmask = ocelot_irq_unmask;  in vcoreiii_irq_init()
163 		gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;  in vcoreiii_irq_init()
165 		gc->chip_types[0].regs.enable = p->reg_off_ena_set;  in vcoreiii_irq_init()
166 		gc->chip_types[0].regs.disable = p->reg_off_ena_clr;  in vcoreiii_irq_init()
167 		gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;  in vcoreiii_irq_init()
168 		gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;  in vcoreiii_irq_init()
172 	irq_reg_writel(gc, 0, p->reg_off_ena);  in vcoreiii_irq_init()
173 	irq_reg_writel(gc, 0xffffffff, p->reg_off_sticky);  in vcoreiii_irq_init()
176 	if (p->flags & FLAGS_NEED_INIT_ENABLE)  in vcoreiii_irq_init()
177 		irq_reg_writel(gc, BIT(0), p->reg_off_ena_irq0);  in vcoreiii_irq_init()
179 	domain->host_data = p;  in vcoreiii_irq_init()
200 IRQCHIP_DECLARE(ocelot_icpu, "mscc,ocelot-icpu-intr", ocelot_irq_init);
208 IRQCHIP_DECLARE(serval_icpu, "mscc,serval-icpu-intr", serval_irq_init);
216 IRQCHIP_DECLARE(luton_icpu, "mscc,luton-icpu-intr", luton_irq_init);
224 IRQCHIP_DECLARE(jaguar2_icpu, "mscc,jaguar2-icpu-intr", jaguar2_irq_init);