60 	struct irq_chip_generic		*gc;  member
75 	struct irq_chip_generic *gc = handler->priv->gc;  in liointc_chained_handle_irq()  local
86 			(handler->parent_int_map & gc->mask_cache &  in liointc_chained_handle_irq()
96 		generic_handle_domain_irq(gc->domain, bit);  in liointc_chained_handle_irq()
103 static void liointc_set_bit(struct irq_chip_generic *gc,  in liointc_set_bit()  argument
108 		writel(readl(gc->reg_base + offset) | mask,  in liointc_set_bit()
109 				gc->reg_base + offset);  in liointc_set_bit()
111 		writel(readl(gc->reg_base + offset) & ~mask,  in liointc_set_bit()
112 				gc->reg_base + offset);  in liointc_set_bit()
117 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);  in liointc_set_type()  local
121 	irq_gc_lock_irqsave(gc, flags);  in liointc_set_type()
124 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);  in liointc_set_type()
125 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);  in liointc_set_type()
128 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, false);  in liointc_set_type()
129 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);  in liointc_set_type()
132 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);  in liointc_set_type()
133 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, false);  in liointc_set_type()
136 		liointc_set_bit(gc, LIOINTC_REG_INTC_EDGE, mask, true);  in liointc_set_type()
137 		liointc_set_bit(gc, LIOINTC_REG_INTC_POL, mask, true);  in liointc_set_type()
140 		irq_gc_unlock_irqrestore(gc, flags);  in liointc_set_type()
143 	irq_gc_unlock_irqrestore(gc, flags);  in liointc_set_type()
149 static void liointc_suspend(struct irq_chip_generic *gc)  in liointc_suspend()  argument
151 	struct liointc_priv *priv = gc->private;  in liointc_suspend()
153 	priv->int_pol = readl(gc->reg_base + LIOINTC_REG_INTC_POL);  in liointc_suspend()
154 	priv->int_edge = readl(gc->reg_base + LIOINTC_REG_INTC_EDGE);  in liointc_suspend()
157 static void liointc_resume(struct irq_chip_generic *gc)  in liointc_resume()  argument
159 	struct liointc_priv *priv = gc->private;  in liointc_resume()
163 	irq_gc_lock_irqsave(gc, flags);  in liointc_resume()
165 	writel(0xffffffff, gc->reg_base + LIOINTC_REG_INTC_DISABLE);  in liointc_resume()
168 		writeb(priv->map_cache[i], gc->reg_base + i);  in liointc_resume()
169 	writel(priv->int_pol, gc->reg_base + LIOINTC_REG_INTC_POL);  in liointc_resume()
170 	writel(priv->int_edge, gc->reg_base + LIOINTC_REG_INTC_EDGE);  in liointc_resume()
172 	writel(gc->mask_cache, gc->reg_base + LIOINTC_REG_INTC_ENABLE);  in liointc_resume()
173 	irq_gc_unlock_irqrestore(gc, flags);  in liointc_resume()
209 	struct irq_chip_generic *gc;  in liointc_init()  local
286 	gc = irq_get_domain_generic_chip(domain, 0);  in liointc_init()
287 	gc->private = priv;  in liointc_init()
288 	gc->reg_base = base;  in liointc_init()
289 	gc->domain = domain;  in liointc_init()
290 	gc->suspend = liointc_suspend;  in liointc_init()
291 	gc->resume = liointc_resume;  in liointc_init()
293 	ct = gc->chip_types;  in liointc_init()
302 	gc->mask_cache = 0;  in liointc_init()
303 	priv->gc = gc;  in liointc_init()