Lines Matching full:gic
5 * Interrupt architecture for the GIC:
42 #include <linux/irqchip/arm-gic.h>
50 #include "irq-gic-common.h"
114 * The GIC mapping of CPU interfaces does not necessarily match
116 * by the GIC itself.
309 pr_warn("GIC: PPI%ld is secure or misconfigured\n", gicirq - 16); in gic_set_type()
318 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
337 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
338 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
353 * is read after we've read the ACK register on the GIC. in gic_handle_irq()
361 * The GIC encodes the source CPU in GICC_IAR, in gic_handle_irq()
370 generic_handle_domain_irq(gic->domain, irqnr); in gic_handle_irq()
400 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); in gic_irq_print_chip() local
402 if (gic->domain->pm_dev) in gic_irq_print_chip()
403 seq_printf(p, gic->domain->pm_dev->of_node->name); in gic_irq_print_chip()
405 seq_printf(p, "GIC-%d", (int)(gic - &gic_data[0])); in gic_irq_print_chip()
415 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument
417 void __iomem *base = gic_data_dist_base(gic); in gic_get_cpumask()
429 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); in gic_get_cpumask()
440 static void gic_cpu_if_up(struct gic_chip_data *gic) in gic_cpu_if_up() argument
442 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_cpu_if_up()
447 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) in gic_cpu_if_up()
464 static void gic_dist_init(struct gic_chip_data *gic) in gic_dist_init() argument
468 unsigned int gic_irqs = gic->gic_irqs; in gic_dist_init()
469 void __iomem *base = gic_data_dist_base(gic); in gic_dist_init()
476 cpumask = gic_get_cpumask(gic); in gic_dist_init()
487 static int gic_cpu_init(struct gic_chip_data *gic) in gic_cpu_init() argument
489 void __iomem *dist_base = gic_data_dist_base(gic); in gic_cpu_init()
490 void __iomem *base = gic_data_cpu_base(gic); in gic_cpu_init()
495 * Setting up the CPU map is only relevant for the primary GIC in gic_cpu_init()
499 if (gic == &gic_data[0]) { in gic_cpu_init()
501 * Get what the GIC says our CPU mask is. in gic_cpu_init()
507 cpu_mask = gic_get_cpumask(gic); in gic_cpu_init()
522 gic_cpu_if_up(gic); in gic_cpu_init()
545 * Saves the GIC distributor registers during suspend or idle. Must be called
546 * with interrupts disabled but before powering down the GIC. After calling
547 * this function, no interrupts will be delivered by the GIC, and another
550 void gic_dist_save(struct gic_chip_data *gic) in gic_dist_save() argument
556 if (WARN_ON(!gic)) in gic_dist_save()
559 gic_irqs = gic->gic_irqs; in gic_dist_save()
560 dist_base = gic_data_dist_base(gic); in gic_dist_save()
566 gic->saved_spi_conf[i] = in gic_dist_save()
570 gic->saved_spi_target[i] = in gic_dist_save()
574 gic->saved_spi_enable[i] = in gic_dist_save()
578 gic->saved_spi_active[i] = in gic_dist_save()
583 * Restores the GIC distributor registers during resume or when coming out of
585 * that occurred while the GIC was suspended is still present, it will be
587 * the GIC and need to be handled by the platform-specific wakeup source.
589 void gic_dist_restore(struct gic_chip_data *gic) in gic_dist_restore() argument
595 if (WARN_ON(!gic)) in gic_dist_restore()
598 gic_irqs = gic->gic_irqs; in gic_dist_restore()
599 dist_base = gic_data_dist_base(gic); in gic_dist_restore()
607 writel_relaxed(gic->saved_spi_conf[i], in gic_dist_restore()
615 writel_relaxed(gic->saved_spi_target[i], in gic_dist_restore()
621 writel_relaxed(gic->saved_spi_enable[i], in gic_dist_restore()
628 writel_relaxed(gic->saved_spi_active[i], in gic_dist_restore()
635 void gic_cpu_save(struct gic_chip_data *gic) in gic_cpu_save() argument
642 if (WARN_ON(!gic)) in gic_cpu_save()
645 dist_base = gic_data_dist_base(gic); in gic_cpu_save()
646 cpu_base = gic_data_cpu_base(gic); in gic_cpu_save()
651 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_save()
655 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_save()
659 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_save()
665 void gic_cpu_restore(struct gic_chip_data *gic) in gic_cpu_restore() argument
672 if (WARN_ON(!gic)) in gic_cpu_restore()
675 dist_base = gic_data_dist_base(gic); in gic_cpu_restore()
676 cpu_base = gic_data_cpu_base(gic); in gic_cpu_restore()
681 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_restore()
688 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_restore()
695 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_restore()
704 gic_cpu_if_up(gic); in gic_cpu_restore()
737 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
739 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
741 if (WARN_ON(!gic->saved_ppi_enable)) in gic_pm_init()
744 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
746 if (WARN_ON(!gic->saved_ppi_active)) in gic_pm_init()
749 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, in gic_pm_init()
751 if (WARN_ON(!gic->saved_ppi_conf)) in gic_pm_init()
754 if (gic == &gic_data[0]) in gic_pm_init()
760 free_percpu(gic->saved_ppi_active); in gic_pm_init()
762 free_percpu(gic->saved_ppi_enable); in gic_pm_init()
767 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
797 struct gic_chip_data *gic = irq_data_get_irq_chip_data(d); in gic_set_affinity() local
800 if (unlikely(gic != &gic_data[0])) in gic_set_affinity()
865 "irqchip/arm/gic:starting", in gic_smp_init()
931 * @cpu: the logical CPU number to get the GIC ID for.
1044 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); in gic_init_physaddr()
1055 struct gic_chip_data *gic = d->host_data; in gic_irq_domain_map() local
1060 gic == &gic_data[0]) ? &gic_chip_mode1 : &gic_chip; in gic_irq_domain_map()
1163 static int gic_init_bases(struct gic_chip_data *gic, in gic_init_bases() argument
1168 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1169 /* Frankein-GIC without banked registers... */ in gic_init_bases()
1172 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1173 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1174 if (WARN_ON(!gic->dist_base.percpu_base || in gic_init_bases()
1175 !gic->cpu_base.percpu_base)) { in gic_init_bases()
1183 unsigned long offset = gic->percpu_offset * core_id; in gic_init_bases()
1184 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = in gic_init_bases()
1185 gic->raw_dist_base + offset; in gic_init_bases()
1186 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = in gic_init_bases()
1187 gic->raw_cpu_base + offset; in gic_init_bases()
1192 /* Normal, sane GIC... */ in gic_init_bases()
1193 WARN(gic->percpu_offset, in gic_init_bases()
1195 gic->percpu_offset); in gic_init_bases()
1196 gic->dist_base.common_base = gic->raw_dist_base; in gic_init_bases()
1197 gic->cpu_base.common_base = gic->raw_cpu_base; in gic_init_bases()
1202 * The GIC only supports up to 1020 interrupt sources. in gic_init_bases()
1204 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; in gic_init_bases()
1208 gic->gic_irqs = gic_irqs; in gic_init_bases()
1210 gic->domain = irq_domain_create_linear(handle, gic_irqs, in gic_init_bases()
1212 gic); in gic_init_bases()
1213 if (WARN_ON(!gic->domain)) { in gic_init_bases()
1218 gic_dist_init(gic); in gic_init_bases()
1219 ret = gic_cpu_init(gic); in gic_init_bases()
1223 ret = gic_pm_init(gic); in gic_init_bases()
1230 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1231 free_percpu(gic->dist_base.percpu_base); in gic_init_bases()
1232 free_percpu(gic->cpu_base.percpu_base); in gic_init_bases()
1238 static int __init __gic_init_bases(struct gic_chip_data *gic, in __gic_init_bases() argument
1243 if (WARN_ON(!gic || gic->domain)) in __gic_init_bases()
1246 if (gic == &gic_data[0]) { in __gic_init_bases()
1250 * This is only necessary for the primary GIC. in __gic_init_bases()
1257 pr_info("GIC: Using split EOI/Deactivate mode\n"); in __gic_init_bases()
1260 ret = gic_init_bases(gic, handle); in __gic_init_bases()
1261 if (gic == &gic_data[0]) in __gic_init_bases()
1267 static void gic_teardown(struct gic_chip_data *gic) in gic_teardown() argument
1269 if (WARN_ON(!gic)) in gic_teardown()
1272 if (gic->raw_dist_base) in gic_teardown()
1273 iounmap(gic->raw_dist_base); in gic_teardown()
1274 if (gic->raw_cpu_base) in gic_teardown()
1275 iounmap(gic->raw_cpu_base); in gic_teardown()
1305 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode()
1318 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode()
1335 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode()
1358 pr_warn("GIC: Adjusting CPU interface base to %pa\n", in gic_check_eoimode()
1389 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) in gic_of_setup() argument
1391 if (!gic || !node) in gic_of_setup()
1394 gic->raw_dist_base = of_iomap(node, 0); in gic_of_setup()
1395 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) in gic_of_setup()
1398 gic->raw_cpu_base = of_iomap(node, 1); in gic_of_setup()
1399 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) in gic_of_setup()
1402 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) in gic_of_setup()
1403 gic->percpu_offset = 0; in gic_of_setup()
1405 gic_enable_of_quirks(node, gic_quirks, gic); in gic_of_setup()
1410 gic_teardown(gic); in gic_of_setup()
1415 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1419 if (!dev || !dev->of_node || !gic || !irq) in gic_of_init_child()
1422 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); in gic_of_init_child()
1423 if (!*gic) in gic_of_init_child()
1426 ret = gic_of_setup(*gic, dev->of_node); in gic_of_init_child()
1430 ret = gic_init_bases(*gic, &dev->of_node->fwnode); in gic_of_init_child()
1432 gic_teardown(*gic); in gic_of_init_child()
1436 irq_domain_set_pm_device((*gic)->domain, dev); in gic_of_init_child()
1437 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); in gic_of_init_child()
1469 struct gic_chip_data *gic; in gic_of_init() local
1478 gic = &gic_data[gic_cnt]; in gic_of_init()
1480 ret = gic_of_setup(gic, node); in gic_of_init()
1488 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) in gic_of_init()
1491 ret = __gic_init_bases(gic, &node->fwnode); in gic_of_init()
1493 gic_teardown(gic); in gic_of_init()
1513 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1514 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1515 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1516 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1517 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1518 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1638 struct gic_chip_data *gic = &gic_data[0]; in gic_v2_acpi_init() local
1649 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); in gic_v2_acpi_init()
1650 if (!gic->raw_cpu_base) { in gic_v2_acpi_init()
1656 gic->raw_dist_base = ioremap(dist->base_address, in gic_v2_acpi_init()
1658 if (!gic->raw_dist_base) { in gic_v2_acpi_init()
1660 gic_teardown(gic); in gic_v2_acpi_init()
1673 * Initialize GIC instance zero (no multi-GIC support). in gic_v2_acpi_init()
1678 gic_teardown(gic); in gic_v2_acpi_init()
1682 ret = __gic_init_bases(gic, gsi_domain_handle); in gic_v2_acpi_init()
1684 pr_err("Failed to initialise GIC\n"); in gic_v2_acpi_init()
1686 gic_teardown(gic); in gic_v2_acpi_init()