1 // SPDX-License-Identifier: GPL-2.0+
8  * If an interrupt fires on bank 1 that isn't in the shortcuts list, bit 8
9  * on bank 0 is set to signify that an interrupt in bank 1 has fired, and
12  * If an interrupt fires on bank 1 that _is_ in the shortcuts list, its
13  * shortcut bit in bank 0 is set as well as its interrupt bit in the bank 1
18  * In a proper cascaded interrupt controller, the interrupt lines with
19  * cascaded interrupt controllers on them are just normal interrupt lines.
30  *  Bits 0-6: IRQ (index in order of interrupts from banks 1, 2, then 0)
34  * An interrupt must be disabled before configuring it for FIQ generation
80 	void __iomem *base;  member
94 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.disable[HWIRQ_BANK(d->hwirq)]);  in armctrl_mask_irq()
99 	writel_relaxed(HWIRQ_BIT(d->hwirq), intc.enable[HWIRQ_BANK(d->hwirq)]);  in armctrl_unmask_irq()
103 	.name = "ARMCTRL-level",
115 		return -EINVAL;  in armctrl_xlate()
118 		return -EINVAL;  in armctrl_xlate()
121 		return -EINVAL;  in armctrl_xlate()
124 		return -EINVAL;  in armctrl_xlate()
136 				  struct device_node *parent,  in armctrl_of_init()  argument
139 	void __iomem *base;  in armctrl_of_init()  local
143 	base = of_iomap(node, 0);  in armctrl_of_init()
144 	if (!base)  in armctrl_of_init()
153 		intc.pending[b] = base + reg_pending[b];  in armctrl_of_init()
154 		intc.enable[b] = base + reg_enable[b];  in armctrl_of_init()
155 		intc.disable[b] = base + reg_disable[b];  in armctrl_of_init()
173 	reg = readl_relaxed(base + REG_FIQ_CONTROL);  in armctrl_of_init()
175 		writel_relaxed(0, base + REG_FIQ_CONTROL);  in armctrl_of_init()
183 			panic("%pOF: unable to get parent interrupt.\n",  in armctrl_of_init()
195 					  struct device_node *parent)  in bcm2835_armctrl_of_init()  argument
197 	return armctrl_of_init(node, parent, false);  in bcm2835_armctrl_of_init()
201 					  struct device_node *parent)  in bcm2836_armctrl_of_init()  argument
203 	return armctrl_of_init(node, parent, true);  in bcm2836_armctrl_of_init()
208  * Handle each interrupt across the entire interrupt controller.  This reads the
209  * status register before handling each interrupt, which is necessary given that
210  * handle_IRQ may briefly re-enable interrupts for soft IRQ handling.
217 	return MAKE_HWIRQ(bank, ffs(stat) - 1);  in armctrl_translate_bank()
222 	return MAKE_HWIRQ(bank, shortcuts[ffs(stat >> SHORTCUT_SHIFT) - 1]);  in armctrl_translate_shortcut()
232 		return MAKE_HWIRQ(0, ffs(stat & BANK0_HWIRQ_MASK) - 1);  in get_next_armctrl_hwirq()
262 IRQCHIP_DECLARE(bcm2835_armctrl_ic, "brcm,bcm2835-armctrl-ic",
264 IRQCHIP_DECLARE(bcm2836_armctrl_ic, "brcm,bcm2836-armctrl-ic",