72 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(aic5_domain, 0);  in aic5_handle()  local
76 	irqnr = irq_reg_readl(bgc, AT91_AIC5_IVR);  in aic5_handle()
77 	irqstat = irq_reg_readl(bgc, AT91_AIC5_ISR);  in aic5_handle()
80 		irq_reg_writel(bgc, 0, AT91_AIC5_EOICR);  in aic5_handle()
88 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_mask()  local
95 	irq_gc_lock(bgc);  in aic5_mask()
99 	irq_gc_unlock(bgc);  in aic5_mask()
105 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_unmask()  local
112 	irq_gc_lock(bgc);  in aic5_unmask()
116 	irq_gc_unlock(bgc);  in aic5_unmask()
122 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_retrigger()  local
125 	irq_gc_lock(bgc);  in aic5_retrigger()
126 	irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);  in aic5_retrigger()
127 	irq_reg_writel(bgc, 1, AT91_AIC5_ISCR);  in aic5_retrigger()
128 	irq_gc_unlock(bgc);  in aic5_retrigger()
136 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_set_type()  local
140 	irq_gc_lock(bgc);  in aic5_set_type()
141 	irq_reg_writel(bgc, d->hwirq, AT91_AIC5_SSR);  in aic5_set_type()
142 	smr = irq_reg_readl(bgc, AT91_AIC5_SMR);  in aic5_set_type()
145 		irq_reg_writel(bgc, smr, AT91_AIC5_SMR);  in aic5_set_type()
146 	irq_gc_unlock(bgc);  in aic5_set_type()
158 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_suspend()  local
165 			irq_reg_writel(bgc, i, AT91_AIC5_SSR);  in aic5_suspend()
166 			smr_cache[i] = irq_reg_readl(bgc, AT91_AIC5_SMR);  in aic5_suspend()
169 	irq_gc_lock(bgc);  in aic5_suspend()
175 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_suspend()
177 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_suspend()
179 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_suspend()
181 	irq_gc_unlock(bgc);  in aic5_suspend()
188 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_resume()  local
193 	irq_gc_lock(bgc);  in aic5_resume()
196 		irq_reg_writel(bgc, 0xffffffff, AT91_AIC5_SPU);  in aic5_resume()
198 			irq_reg_writel(bgc, i, AT91_AIC5_SSR);  in aic5_resume()
199 			irq_reg_writel(bgc, i, AT91_AIC5_SVR);  in aic5_resume()
200 			irq_reg_writel(bgc, smr_cache[i], AT91_AIC5_SMR);  in aic5_resume()
211 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_resume()
213 			irq_reg_writel(bgc, 1, AT91_AIC5_IECR);  in aic5_resume()
215 			irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_resume()
217 	irq_gc_unlock(bgc);  in aic5_resume()
224 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(domain, 0);  in aic5_pm_shutdown()  local
228 	irq_gc_lock(bgc);  in aic5_pm_shutdown()
230 		irq_reg_writel(bgc, i + gc->irq_base, AT91_AIC5_SSR);  in aic5_pm_shutdown()
231 		irq_reg_writel(bgc, 1, AT91_AIC5_IDCR);  in aic5_pm_shutdown()
232 		irq_reg_writel(bgc, 1, AT91_AIC5_ICCR);  in aic5_pm_shutdown()
234 	irq_gc_unlock(bgc);  in aic5_pm_shutdown()
279 	struct irq_chip_generic *bgc = irq_get_domain_generic_chip(d, 0);  in aic5_irq_domain_xlate()  local
284 	if (!bgc)  in aic5_irq_domain_xlate()
292 	irq_gc_lock_irqsave(bgc, flags);  in aic5_irq_domain_xlate()
293 	irq_reg_writel(bgc, *out_hwirq, AT91_AIC5_SSR);  in aic5_irq_domain_xlate()
294 	smr = irq_reg_readl(bgc, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()
296 	irq_reg_writel(bgc, smr, AT91_AIC5_SMR);  in aic5_irq_domain_xlate()
297 	irq_gc_unlock_irqrestore(bgc, flags);  in aic5_irq_domain_xlate()