62 	struct irq_domain_chip_generic *dgc = aic_domain->gc;  in aic_handle()
63 	struct irq_chip_generic *gc = dgc->gc[0];  in aic_handle()  local
67 	irqnr = irq_reg_readl(gc, AT91_AIC_IVR);  in aic_handle()
68 	irqstat = irq_reg_readl(gc, AT91_AIC_ISR);  in aic_handle()
71 		irq_reg_writel(gc, 0, AT91_AIC_EOICR);  in aic_handle()
78 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic_retrigger()  local
81 	irq_gc_lock(gc);  in aic_retrigger()
82 	irq_reg_writel(gc, d->mask, AT91_AIC_ISCR);  in aic_retrigger()
83 	irq_gc_unlock(gc);  in aic_retrigger()
90 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic_set_type()  local
94 	smr = irq_reg_readl(gc, AT91_AIC_SMR(d->hwirq));  in aic_set_type()
99 	irq_reg_writel(gc, smr, AT91_AIC_SMR(d->hwirq));  in aic_set_type()
107 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic_suspend()  local
109 	irq_gc_lock(gc);  in aic_suspend()
110 	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IDCR);  in aic_suspend()
111 	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IECR);  in aic_suspend()
112 	irq_gc_unlock(gc);  in aic_suspend()
117 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic_resume()  local
119 	irq_gc_lock(gc);  in aic_resume()
120 	irq_reg_writel(gc, gc->wake_active, AT91_AIC_IDCR);  in aic_resume()
121 	irq_reg_writel(gc, gc->mask_cache, AT91_AIC_IECR);  in aic_resume()
122 	irq_gc_unlock(gc);  in aic_resume()
127 	struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d);  in aic_pm_shutdown()  local
129 	irq_gc_lock(gc);  in aic_pm_shutdown()
130 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);  in aic_pm_shutdown()
131 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);  in aic_pm_shutdown()
132 	irq_gc_unlock(gc);  in aic_pm_shutdown()
142 	struct irq_chip_generic *gc = irq_get_domain_generic_chip(domain, 0);  in aic_hw_init()  local
150 		irq_reg_writel(gc, 0, AT91_AIC_EOICR);  in aic_hw_init()
157 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_SPU);  in aic_hw_init()
160 	irq_reg_writel(gc, 0, AT91_AIC_DCR);  in aic_hw_init()
163 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_IDCR);  in aic_hw_init()
164 	irq_reg_writel(gc, 0xffffffff, AT91_AIC_ICCR);  in aic_hw_init()
167 		irq_reg_writel(gc, i, AT91_AIC_SVR(i));  in aic_hw_init()
176 	struct irq_domain_chip_generic *dgc = d->gc;  in aic_irq_domain_xlate()
177 	struct irq_chip_generic *gc;  in aic_irq_domain_xlate()  local
195 	gc = dgc->gc[idx];  in aic_irq_domain_xlate()
197 	irq_gc_lock_irqsave(gc, flags);  in aic_irq_domain_xlate()
198 	smr = irq_reg_readl(gc, AT91_AIC_SMR(*out_hwirq));  in aic_irq_domain_xlate()
200 	irq_reg_writel(gc, smr, AT91_AIC_SMR(*out_hwirq));  in aic_irq_domain_xlate()
201 	irq_gc_unlock_irqrestore(gc, flags);  in aic_irq_domain_xlate()
243 	struct irq_chip_generic *gc;  in aic_of_init()  local
255 	gc = irq_get_domain_generic_chip(domain, 0);  in aic_of_init()
257 	gc->chip_types[0].regs.eoi = AT91_AIC_EOICR;  in aic_of_init()
258 	gc->chip_types[0].regs.enable = AT91_AIC_IECR;  in aic_of_init()
259 	gc->chip_types[0].regs.disable = AT91_AIC_IDCR;  in aic_of_init()
260 	gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg;  in aic_of_init()
261 	gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg;  in aic_of_init()
262 	gc->chip_types[0].chip.irq_retrigger = aic_retrigger;  in aic_of_init()
263 	gc->chip_types[0].chip.irq_set_type = aic_set_type;  in aic_of_init()
264 	gc->chip_types[0].chip.irq_suspend = aic_suspend;  in aic_of_init()
265 	gc->chip_types[0].chip.irq_resume = aic_resume;  in aic_of_init()
266 	gc->chip_types[0].chip.irq_pm_shutdown = aic_pm_shutdown;  in aic_of_init()