Lines Matching +full:soc +full:- +full:s
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2011-2014 NVIDIA CORPORATION. All rights reserved.
17 #include <linux/dma-mapping.h>
19 #include <soc/tegra/ahb.h>
20 #include <soc/tegra/mc.h>
22 #include "iommu-pages.h"
27 const struct tegra_smmu_group_soc *soc; member
37 const struct tegra_smmu_soc *soc; member
75 writel(value, smmu->regs + offset); in smmu_writel()
80 return readl(smmu->regs + offset); in smmu_readl()
90 ((smmu)->soc->num_tlb_lines & (smmu)->tlb_mask)
122 /* per-SWGROUP SMMU_*_ASID register */
137 #define SMMU_PAGE_MASK (~(SMMU_SIZE_PT-1))
160 return (iova >> SMMU_PDE_SHIFT) & (SMMU_NUM_PDE - 1); in iova_pd_index()
165 return (iova >> SMMU_PTE_SHIFT) & (SMMU_NUM_PTE - 1); in iova_pt_index()
171 return (addr & smmu->pfn_mask) == addr; in smmu_dma_addr_valid()
176 return (dma_addr_t)(pde & smmu->pfn_mask) << 12; in smmu_pde_to_dma()
189 offset &= ~(smmu->mc->soc->atom_size - 1); in smmu_flush_ptc()
191 if (smmu->mc->soc->num_address_bits > 32) { in smmu_flush_ptc()
214 if (smmu->soc->num_asids == 4) in smmu_flush_tlb_asid()
229 if (smmu->soc->num_asids == 4) in smmu_flush_tlb_section()
244 if (smmu->soc->num_asids == 4) in smmu_flush_tlb_group()
262 id = find_first_zero_bit(smmu->asids, smmu->soc->num_asids); in tegra_smmu_alloc_asid()
263 if (id >= smmu->soc->num_asids) in tegra_smmu_alloc_asid()
264 return -ENOSPC; in tegra_smmu_alloc_asid()
266 set_bit(id, smmu->asids); in tegra_smmu_alloc_asid()
274 clear_bit(id, smmu->asids); in tegra_smmu_free_asid()
285 as->attr = SMMU_PD_READABLE | SMMU_PD_WRITABLE | SMMU_PD_NONSECURE; in tegra_smmu_domain_alloc_paging()
287 as->pd = __iommu_alloc_pages(GFP_KERNEL | __GFP_DMA, 0); in tegra_smmu_domain_alloc_paging()
288 if (!as->pd) { in tegra_smmu_domain_alloc_paging()
293 as->count = kcalloc(SMMU_NUM_PDE, sizeof(u32), GFP_KERNEL); in tegra_smmu_domain_alloc_paging()
294 if (!as->count) { in tegra_smmu_domain_alloc_paging()
295 __iommu_free_pages(as->pd, 0); in tegra_smmu_domain_alloc_paging()
300 as->pts = kcalloc(SMMU_NUM_PDE, sizeof(*as->pts), GFP_KERNEL); in tegra_smmu_domain_alloc_paging()
301 if (!as->pts) { in tegra_smmu_domain_alloc_paging()
302 kfree(as->count); in tegra_smmu_domain_alloc_paging()
303 __iommu_free_pages(as->pd, 0); in tegra_smmu_domain_alloc_paging()
308 spin_lock_init(&as->lock); in tegra_smmu_domain_alloc_paging()
311 as->domain.geometry.aperture_start = 0; in tegra_smmu_domain_alloc_paging()
312 as->domain.geometry.aperture_end = 0xffffffff; in tegra_smmu_domain_alloc_paging()
313 as->domain.geometry.force_aperture = true; in tegra_smmu_domain_alloc_paging()
315 return &as->domain; in tegra_smmu_domain_alloc_paging()
324 WARN_ON_ONCE(as->use_count); in tegra_smmu_domain_free()
325 kfree(as->count); in tegra_smmu_domain_free()
326 kfree(as->pts); in tegra_smmu_domain_free()
336 for (i = 0; i < smmu->soc->num_swgroups; i++) { in tegra_smmu_find_swgroup()
337 if (smmu->soc->swgroups[i].swgroup == swgroup) { in tegra_smmu_find_swgroup()
338 group = &smmu->soc->swgroups[i]; in tegra_smmu_find_swgroup()
355 value = smmu_readl(smmu, group->reg); in tegra_smmu_enable()
359 smmu_writel(smmu, value, group->reg); in tegra_smmu_enable()
361 pr_warn("%s group from swgroup %u not found\n", __func__, in tegra_smmu_enable()
367 for (i = 0; i < smmu->soc->num_clients; i++) { in tegra_smmu_enable()
368 const struct tegra_mc_client *client = &smmu->soc->clients[i]; in tegra_smmu_enable()
370 if (client->swgroup != swgroup) in tegra_smmu_enable()
373 value = smmu_readl(smmu, client->regs.smmu.reg); in tegra_smmu_enable()
374 value |= BIT(client->regs.smmu.bit); in tegra_smmu_enable()
375 smmu_writel(smmu, value, client->regs.smmu.reg); in tegra_smmu_enable()
388 value = smmu_readl(smmu, group->reg); in tegra_smmu_disable()
392 smmu_writel(smmu, value, group->reg); in tegra_smmu_disable()
395 for (i = 0; i < smmu->soc->num_clients; i++) { in tegra_smmu_disable()
396 const struct tegra_mc_client *client = &smmu->soc->clients[i]; in tegra_smmu_disable()
398 if (client->swgroup != swgroup) in tegra_smmu_disable()
401 value = smmu_readl(smmu, client->regs.smmu.reg); in tegra_smmu_disable()
402 value &= ~BIT(client->regs.smmu.bit); in tegra_smmu_disable()
403 smmu_writel(smmu, value, client->regs.smmu.reg); in tegra_smmu_disable()
413 mutex_lock(&smmu->lock); in tegra_smmu_as_prepare()
415 if (as->use_count > 0) { in tegra_smmu_as_prepare()
416 as->use_count++; in tegra_smmu_as_prepare()
420 as->pd_dma = dma_map_page(smmu->dev, as->pd, 0, SMMU_SIZE_PD, in tegra_smmu_as_prepare()
422 if (dma_mapping_error(smmu->dev, as->pd_dma)) { in tegra_smmu_as_prepare()
423 err = -ENOMEM; in tegra_smmu_as_prepare()
427 /* We can't handle 64-bit DMA addresses */ in tegra_smmu_as_prepare()
428 if (!smmu_dma_addr_valid(smmu, as->pd_dma)) { in tegra_smmu_as_prepare()
429 err = -ENOMEM; in tegra_smmu_as_prepare()
433 err = tegra_smmu_alloc_asid(smmu, &as->id); in tegra_smmu_as_prepare()
437 smmu_flush_ptc(smmu, as->pd_dma, 0); in tegra_smmu_as_prepare()
438 smmu_flush_tlb_asid(smmu, as->id); in tegra_smmu_as_prepare()
440 smmu_writel(smmu, as->id & 0x7f, SMMU_PTB_ASID); in tegra_smmu_as_prepare()
441 value = SMMU_PTB_DATA_VALUE(as->pd_dma, as->attr); in tegra_smmu_as_prepare()
445 as->smmu = smmu; in tegra_smmu_as_prepare()
446 as->use_count++; in tegra_smmu_as_prepare()
448 mutex_unlock(&smmu->lock); in tegra_smmu_as_prepare()
453 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); in tegra_smmu_as_prepare()
455 mutex_unlock(&smmu->lock); in tegra_smmu_as_prepare()
463 mutex_lock(&smmu->lock); in tegra_smmu_as_unprepare()
465 if (--as->use_count > 0) { in tegra_smmu_as_unprepare()
466 mutex_unlock(&smmu->lock); in tegra_smmu_as_unprepare()
470 tegra_smmu_free_asid(smmu, as->id); in tegra_smmu_as_unprepare()
472 dma_unmap_page(smmu->dev, as->pd_dma, SMMU_SIZE_PD, DMA_TO_DEVICE); in tegra_smmu_as_unprepare()
474 as->smmu = NULL; in tegra_smmu_as_unprepare()
476 mutex_unlock(&smmu->lock); in tegra_smmu_as_unprepare()
489 return -ENOENT; in tegra_smmu_attach_dev()
491 for (index = 0; index < fwspec->num_ids; index++) { in tegra_smmu_attach_dev()
496 tegra_smmu_enable(smmu, fwspec->ids[index], as->id); in tegra_smmu_attach_dev()
500 return -ENODEV; in tegra_smmu_attach_dev()
505 while (index--) { in tegra_smmu_attach_dev()
506 tegra_smmu_disable(smmu, fwspec->ids[index], as->id); in tegra_smmu_attach_dev()
523 return -ENODEV; in tegra_smmu_identity_attach()
529 smmu = as->smmu; in tegra_smmu_identity_attach()
530 for (index = 0; index < fwspec->num_ids; index++) { in tegra_smmu_identity_attach()
531 tegra_smmu_disable(smmu, fwspec->ids[index], as->id); in tegra_smmu_identity_attach()
550 struct tegra_smmu *smmu = as->smmu; in tegra_smmu_set_pde()
551 u32 *pd = page_address(as->pd); in tegra_smmu_set_pde()
558 dma_sync_single_range_for_device(smmu->dev, as->pd_dma, offset, in tegra_smmu_set_pde()
562 smmu_flush_ptc(smmu, as->pd_dma, offset); in tegra_smmu_set_pde()
563 smmu_flush_tlb_section(smmu, as->id, iova); in tegra_smmu_set_pde()
578 struct tegra_smmu *smmu = as->smmu; in tegra_smmu_pte_lookup()
582 pt_page = as->pts[pd_index]; in tegra_smmu_pte_lookup()
586 pd = page_address(as->pd); in tegra_smmu_pte_lookup()
596 struct tegra_smmu *smmu = as->smmu; in as_get_pte()
598 if (!as->pts[pde]) { in as_get_pte()
601 dma = dma_map_page(smmu->dev, page, 0, SMMU_SIZE_PT, in as_get_pte()
603 if (dma_mapping_error(smmu->dev, dma)) { in as_get_pte()
609 dma_unmap_page(smmu->dev, dma, SMMU_SIZE_PT, in as_get_pte()
615 as->pts[pde] = page; in as_get_pte()
622 u32 *pd = page_address(as->pd); in as_get_pte()
627 return tegra_smmu_pte_offset(as->pts[pde], iova); in as_get_pte()
634 as->count[pd_index]++; in tegra_smmu_pte_get_use()
640 struct page *page = as->pts[pde]; in tegra_smmu_pte_put_use()
646 if (--as->count[pde] == 0) { in tegra_smmu_pte_put_use()
647 struct tegra_smmu *smmu = as->smmu; in tegra_smmu_pte_put_use()
648 u32 *pd = page_address(as->pd); in tegra_smmu_pte_put_use()
653 dma_unmap_page(smmu->dev, pte_dma, SMMU_SIZE_PT, DMA_TO_DEVICE); in tegra_smmu_pte_put_use()
655 as->pts[pde] = NULL; in tegra_smmu_pte_put_use()
662 struct tegra_smmu *smmu = as->smmu; in tegra_smmu_set_pte()
667 dma_sync_single_range_for_device(smmu->dev, pte_dma, offset, in tegra_smmu_set_pte()
670 smmu_flush_tlb_group(smmu, as->id, iova); in tegra_smmu_set_pte()
679 struct page *page = as->pts[pde]; in as_get_pde_page()
688 * spinlock needs to be unlocked and re-locked after allocation. in as_get_pde_page()
691 spin_unlock_irqrestore(&as->lock, *flags); in as_get_pde_page()
696 spin_lock_irqsave(&as->lock, *flags); in as_get_pde_page()
703 if (as->pts[pde]) { in as_get_pde_page()
707 page = as->pts[pde]; in as_get_pde_page()
726 return -ENOMEM; in __tegra_smmu_map()
730 return -ENOMEM; in __tegra_smmu_map()
732 /* If we aren't overwriting a pre-existing entry, increment use */ in __tegra_smmu_map()
776 spin_lock_irqsave(&as->lock, flags); in tegra_smmu_map()
778 spin_unlock_irqrestore(&as->lock, flags); in tegra_smmu_map()
792 spin_lock_irqsave(&as->lock, flags); in tegra_smmu_unmap()
794 spin_unlock_irqrestore(&as->lock, flags); in tegra_smmu_unmap()
811 pfn = *pte & as->smmu->pfn_mask; in tegra_smmu_iova_to_phys()
827 put_device(&pdev->dev); in tegra_smmu_find()
831 return mc->smmu; in tegra_smmu_find()
837 const struct iommu_ops *ops = smmu->iommu.ops; in tegra_smmu_configure()
840 err = iommu_fwspec_init(dev, dev_fwnode(smmu->dev)); in tegra_smmu_configure()
846 err = ops->of_xlate(dev, args); in tegra_smmu_configure()
858 struct device_node *np = dev->of_node; in tegra_smmu_probe_device()
864 while (of_parse_phandle_with_args(np, "iommus", "#iommu-cells", index, in tegra_smmu_probe_device()
882 return ERR_PTR(-ENODEV); in tegra_smmu_probe_device()
884 return &smmu->iommu; in tegra_smmu_probe_device()
892 for (i = 0; i < smmu->soc->num_groups; i++) in tegra_smmu_find_group()
893 for (j = 0; j < smmu->soc->groups[i].num_swgroups; j++) in tegra_smmu_find_group()
894 if (smmu->soc->groups[i].swgroups[j] == swgroup) in tegra_smmu_find_group()
895 return &smmu->soc->groups[i]; in tegra_smmu_find_group()
903 struct tegra_smmu *smmu = group->smmu; in tegra_smmu_group_release()
905 mutex_lock(&smmu->lock); in tegra_smmu_group_release()
906 list_del(&group->list); in tegra_smmu_group_release()
907 mutex_unlock(&smmu->lock); in tegra_smmu_group_release()
914 const struct tegra_smmu_group_soc *soc; in tegra_smmu_device_group() local
915 unsigned int swgroup = fwspec->ids[0]; in tegra_smmu_device_group()
920 soc = tegra_smmu_find_group(smmu, swgroup); in tegra_smmu_device_group()
922 mutex_lock(&smmu->lock); in tegra_smmu_device_group()
925 list_for_each_entry(group, &smmu->groups, list) in tegra_smmu_device_group()
926 if ((group->swgroup == swgroup) || (soc && group->soc == soc)) { in tegra_smmu_device_group()
927 grp = iommu_group_ref_get(group->group); in tegra_smmu_device_group()
928 mutex_unlock(&smmu->lock); in tegra_smmu_device_group()
932 group = devm_kzalloc(smmu->dev, sizeof(*group), GFP_KERNEL); in tegra_smmu_device_group()
934 mutex_unlock(&smmu->lock); in tegra_smmu_device_group()
938 INIT_LIST_HEAD(&group->list); in tegra_smmu_device_group()
939 group->swgroup = swgroup; in tegra_smmu_device_group()
940 group->smmu = smmu; in tegra_smmu_device_group()
941 group->soc = soc; in tegra_smmu_device_group()
944 group->group = pci_device_group(dev); in tegra_smmu_device_group()
946 group->group = generic_device_group(dev); in tegra_smmu_device_group()
948 if (IS_ERR(group->group)) { in tegra_smmu_device_group()
949 devm_kfree(smmu->dev, group); in tegra_smmu_device_group()
950 mutex_unlock(&smmu->lock); in tegra_smmu_device_group()
954 iommu_group_set_iommudata(group->group, group, tegra_smmu_group_release); in tegra_smmu_device_group()
955 if (soc) in tegra_smmu_device_group()
956 iommu_group_set_name(group->group, soc->name); in tegra_smmu_device_group()
957 list_add_tail(&group->list, &smmu->groups); in tegra_smmu_device_group()
958 mutex_unlock(&smmu->lock); in tegra_smmu_device_group()
960 return group->group; in tegra_smmu_device_group()
966 struct platform_device *iommu_pdev = of_find_device_by_node(args->np); in tegra_smmu_of_xlate()
968 u32 id = args->args[0]; in tegra_smmu_of_xlate()
971 * Note: we are here releasing the reference of &iommu_pdev->dev, which in tegra_smmu_of_xlate()
972 * is mc->dev. Although some functions in tegra_smmu_ops may keep using in tegra_smmu_of_xlate()
973 * its private data beyond this point, it's still safe to do so because in tegra_smmu_of_xlate()
977 put_device(&iommu_pdev->dev); in tegra_smmu_of_xlate()
979 dev_iommu_priv_set(dev, mc->smmu); in tegra_smmu_of_xlate()
1014 { .compatible = "nvidia,tegra30-ahb", }, in tegra_smmu_ahb_enable()
1026 static int tegra_smmu_swgroups_show(struct seq_file *s, void *data) in tegra_smmu_swgroups_show() argument
1028 struct tegra_smmu *smmu = s->private; in tegra_smmu_swgroups_show()
1032 seq_printf(s, "swgroup enabled ASID\n"); in tegra_smmu_swgroups_show()
1033 seq_printf(s, "------------------------\n"); in tegra_smmu_swgroups_show()
1035 for (i = 0; i < smmu->soc->num_swgroups; i++) { in tegra_smmu_swgroups_show()
1036 const struct tegra_smmu_swgroup *group = &smmu->soc->swgroups[i]; in tegra_smmu_swgroups_show()
1040 value = smmu_readl(smmu, group->reg); in tegra_smmu_swgroups_show()
1049 seq_printf(s, "%-9s %-7s %#04x\n", group->name, status, in tegra_smmu_swgroups_show()
1058 static int tegra_smmu_clients_show(struct seq_file *s, void *data) in tegra_smmu_clients_show() argument
1060 struct tegra_smmu *smmu = s->private; in tegra_smmu_clients_show()
1064 seq_printf(s, "client enabled\n"); in tegra_smmu_clients_show()
1065 seq_printf(s, "--------------------\n"); in tegra_smmu_clients_show()
1067 for (i = 0; i < smmu->soc->num_clients; i++) { in tegra_smmu_clients_show()
1068 const struct tegra_mc_client *client = &smmu->soc->clients[i]; in tegra_smmu_clients_show()
1071 value = smmu_readl(smmu, client->regs.smmu.reg); in tegra_smmu_clients_show()
1073 if (value & BIT(client->regs.smmu.bit)) in tegra_smmu_clients_show()
1078 seq_printf(s, "%-12s %s\n", client->name, status); in tegra_smmu_clients_show()
1088 smmu->debugfs = debugfs_create_dir("smmu", NULL); in tegra_smmu_debugfs_init()
1090 debugfs_create_file("swgroups", S_IRUGO, smmu->debugfs, smmu, in tegra_smmu_debugfs_init()
1092 debugfs_create_file("clients", S_IRUGO, smmu->debugfs, smmu, in tegra_smmu_debugfs_init()
1098 debugfs_remove_recursive(smmu->debugfs); in tegra_smmu_debugfs_exit()
1102 const struct tegra_smmu_soc *soc, in tegra_smmu_probe() argument
1111 return ERR_PTR(-ENOMEM); in tegra_smmu_probe()
1119 * callback via the IOMMU device's .drvdata field. in tegra_smmu_probe()
1121 mc->smmu = smmu; in tegra_smmu_probe()
1123 smmu->asids = devm_bitmap_zalloc(dev, soc->num_asids, GFP_KERNEL); in tegra_smmu_probe()
1124 if (!smmu->asids) in tegra_smmu_probe()
1125 return ERR_PTR(-ENOMEM); in tegra_smmu_probe()
1127 INIT_LIST_HEAD(&smmu->groups); in tegra_smmu_probe()
1128 mutex_init(&smmu->lock); in tegra_smmu_probe()
1130 smmu->regs = mc->regs; in tegra_smmu_probe()
1131 smmu->soc = soc; in tegra_smmu_probe()
1132 smmu->dev = dev; in tegra_smmu_probe()
1133 smmu->mc = mc; in tegra_smmu_probe()
1135 smmu->pfn_mask = in tegra_smmu_probe()
1136 BIT_MASK(mc->soc->num_address_bits - SMMU_PTE_SHIFT) - 1; in tegra_smmu_probe()
1138 mc->soc->num_address_bits, smmu->pfn_mask); in tegra_smmu_probe()
1139 smmu->tlb_mask = (1 << fls(smmu->soc->num_tlb_lines)) - 1; in tegra_smmu_probe()
1140 dev_dbg(dev, "TLB lines: %u, mask: %#lx\n", smmu->soc->num_tlb_lines, in tegra_smmu_probe()
1141 smmu->tlb_mask); in tegra_smmu_probe()
1145 if (soc->supports_request_limit) in tegra_smmu_probe()
1153 if (soc->supports_round_robin_arbitration) in tegra_smmu_probe()
1165 err = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, dev_name(dev)); in tegra_smmu_probe()
1169 err = iommu_device_register(&smmu->iommu, &tegra_smmu_ops, dev); in tegra_smmu_probe()
1171 iommu_device_sysfs_remove(&smmu->iommu); in tegra_smmu_probe()
1183 iommu_device_unregister(&smmu->iommu); in tegra_smmu_remove()
1184 iommu_device_sysfs_remove(&smmu->iommu); in tegra_smmu_remove()