Lines Matching refs:iommu_write_reg
115 iommu_write_reg(obj, p[i], i * sizeof(u32)); in omap_iommu_restore_ctx()
141 iommu_write_reg(obj, MMU_IRQ_TWL_MASK, MMU_IRQENABLE); in __iommu_set_twl()
143 iommu_write_reg(obj, MMU_IRQ_TLB_MISS_MASK, MMU_IRQENABLE); in __iommu_set_twl()
151 iommu_write_reg(obj, l, MMU_CNTL); in __iommu_set_twl()
169 iommu_write_reg(obj, pa, MMU_TTB); in omap2_iommu_enable()
174 iommu_write_reg(obj, MMU_GP_REG_BUS_ERR_BACK_EN, MMU_GP_REG); in omap2_iommu_enable()
186 iommu_write_reg(obj, l, MMU_CNTL); in omap2_iommu_disable()
245 iommu_write_reg(obj, status, MMU_IRQSTATUS); in iommu_report_fault()
267 iommu_write_reg(obj, val, MMU_LOCK); in iotlb_lock_set()
278 iommu_write_reg(obj, cr->cam | MMU_CAM_V, MMU_CAM); in iotlb_load_cr()
279 iommu_write_reg(obj, cr->ram, MMU_RAM); in iotlb_load_cr()
281 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); in iotlb_load_cr()
282 iommu_write_reg(obj, 1, MMU_LD_TLB); in iotlb_load_cr()
428 iommu_write_reg(obj, 1, MMU_FLUSH_ENTRY); in flush_iotlb_page()
452 iommu_write_reg(obj, 1, MMU_GFLUSH); in flush_iotlb_all()
823 iommu_write_reg(obj, 0, MMU_IRQENABLE); in iommu_fault_handler()