13 PMU_FORMAT_ATTR(event,		"config:0-27");		/* ES: Events Select */
67 		return 0;						\
68 	return (iommu_pmu->filter & _filter) ? attr->mode : 0;		\
77 IOMMU_PMU_ATTR(filter_requester_id_en,	"config1:0",		IOMMU_PMU_FILTER_REQUESTER_ID);
84 IOMMU_PMU_ATTR(filter_pasid,		"config2:0-21",		IOMMU_PMU_FILTER_PASID);
88 #define iommu_pmu_en_requester_id(e)		((e) & 0x1)
89 #define iommu_pmu_en_domain(e)			(((e) >> 1) & 0x1)
90 #define iommu_pmu_en_pasid(e)			(((e) >> 2) & 0x1)
91 #define iommu_pmu_en_ats(e)			(((e) >> 3) & 0x1)
92 #define iommu_pmu_en_page_table(e)		(((e) >> 4) & 0x1)
93 #define iommu_pmu_get_requester_id(filter)	(((filter) >> 16) & 0xffff)
94 #define iommu_pmu_get_domain(filter)		(((filter) >> 32) & 0xffff)
95 #define iommu_pmu_get_pasid(filter)		((filter) & 0x3fffff)
96 #define iommu_pmu_get_ats(filter)		(((filter) >> 24) & 0x1f)
97 #define iommu_pmu_get_page_table(filter)	(((filter) >> 32) & 0x1f)
115 			    0);							\
141 		return 0;							\
142 	return (iommu_pmu->evcap[_g_idx] & _event) ? attr->mode : 0;		\
151 IOMMU_PMU_EVENT_ATTR(iommu_clocks,		"event_group=0x0,event=0x001", 0x0, 0x001)
152 IOMMU_PMU_EVENT_ATTR(iommu_requests,		"event_group=0x0,event=0x002", 0x0, 0x002)
153 IOMMU_PMU_EVENT_ATTR(pw_occupancy,		"event_group=0x0,event=0x004", 0x0, 0x004)
154 IOMMU_PMU_EVENT_ATTR(ats_blocked,		"event_group=0x0,event=0x008", 0x0, 0x008)
155 IOMMU_PMU_EVENT_ATTR(iommu_mrds,		"event_group=0x1,event=0x001", 0x1, 0x001)
156 IOMMU_PMU_EVENT_ATTR(iommu_mem_blocked,		"event_group=0x1,event=0x020", 0x1, 0x020)
157 IOMMU_PMU_EVENT_ATTR(pg_req_posted,		"event_group=0x1,event=0x040", 0x1, 0x040)
158 IOMMU_PMU_EVENT_ATTR(ctxt_cache_lookup,		"event_group=0x2,event=0x001", 0x2, 0x001)
159 IOMMU_PMU_EVENT_ATTR(ctxt_cache_hit,		"event_group=0x2,event=0x002", 0x2, 0x002)
160 IOMMU_PMU_EVENT_ATTR(pasid_cache_lookup,	"event_group=0x2,event=0x004", 0x2, 0x004)
161 IOMMU_PMU_EVENT_ATTR(pasid_cache_hit,		"event_group=0x2,event=0x008", 0x2, 0x008)
162 IOMMU_PMU_EVENT_ATTR(ss_nonleaf_lookup,		"event_group=0x2,event=0x010", 0x2, 0x010)
163 IOMMU_PMU_EVENT_ATTR(ss_nonleaf_hit,		"event_group=0x2,event=0x020", 0x2, 0x020)
164 IOMMU_PMU_EVENT_ATTR(fs_nonleaf_lookup,		"event_group=0x2,event=0x040", 0x2, 0x040)
165 IOMMU_PMU_EVENT_ATTR(fs_nonleaf_hit,		"event_group=0x2,event=0x080", 0x2, 0x080)
166 IOMMU_PMU_EVENT_ATTR(hpt_nonleaf_lookup,	"event_group=0x2,event=0x100", 0x2, 0x100)
167 IOMMU_PMU_EVENT_ATTR(hpt_nonleaf_hit,		"event_group=0x2,event=0x200", 0x2, 0x200)
168 IOMMU_PMU_EVENT_ATTR(iotlb_lookup,		"event_group=0x3,event=0x001", 0x3, 0x001)
169 IOMMU_PMU_EVENT_ATTR(iotlb_hit,			"event_group=0x3,event=0x002", 0x3, 0x002)
170 IOMMU_PMU_EVENT_ATTR(hpt_leaf_lookup,		"event_group=0x3,event=0x004", 0x3, 0x004)
171 IOMMU_PMU_EVENT_ATTR(hpt_leaf_hit,		"event_group=0x3,event=0x008", 0x3, 0x008)
172 IOMMU_PMU_EVENT_ATTR(int_cache_lookup,		"event_group=0x4,event=0x001", 0x4, 0x001)
173 IOMMU_PMU_EVENT_ATTR(int_cache_hit_nonposted,	"event_group=0x4,event=0x002", 0x4, 0x002)
174 IOMMU_PMU_EVENT_ATTR(int_cache_hit_posted,	"event_group=0x4,event=0x004", 0x4, 0x004)
254 	return 0;  in iommu_pmu_validate_event()
261 	int nr = 0;  in iommu_pmu_validate_group()
276 	return 0;  in iommu_pmu_validate_group()
290 	if (event->cpu < 0)  in iommu_pmu_event_init()
334 	if (WARN_ON_ONCE(hwc->idx < 0 || hwc->idx >= IOMMU_PMU_IDX_MAX))  in iommu_pmu_start()
340 	hwc->state = 0;  in iommu_pmu_start()
356 	ecmd_submit_sync(iommu, DMA_ECMD_ENABLE, hwc->idx, 0);  in iommu_pmu_start()
368 		ecmd_submit_sync(iommu, DMA_ECMD_DISABLE, hwc->idx, 0);  in iommu_pmu_stop()
386 	return 0;  in iommu_pmu_validate_per_cntr_event()
399 	for (idx = iommu_pmu->num_cntr - 1; idx >= 0; idx--) {  in iommu_pmu_assign_event()
407 	if (idx < 0)  in iommu_pmu_assign_event()
432 	return 0;  in iommu_pmu_assign_event()
442 	if (ret < 0)  in iommu_pmu_add()
448 		iommu_pmu_start(event, 0);  in iommu_pmu_add()
450 	return 0;  in iommu_pmu_add()
478 	ecmd_submit_sync(iommu, DMA_ECMD_UNFREEZE, 0, 0);  in iommu_pmu_enable()
486 	ecmd_submit_sync(iommu, DMA_ECMD_FREEZE, 0, 0);  in iommu_pmu_disable()
571 		return 0;  in alloc_iommu_pmu()
617 	for (i = 0; i < iommu_pmu->num_eg; i++) {  in alloc_iommu_pmu()
630 	for (i = 0; i < iommu_pmu->num_cntr; i++) {  in alloc_iommu_pmu()
640 		for (j = 0; j < iommu_pmu->num_eg; j++)  in alloc_iommu_pmu()
653 	for (i = 0; i < iommu_pmu->num_cntr; i++) {  in alloc_iommu_pmu()
673 		for (j = 0; j < iommu_pmu->num_eg; j++)  in alloc_iommu_pmu()
674 			iommu_pmu->cntr_evcap[i][j] = 0;  in alloc_iommu_pmu()
677 		for (j = 0; j < iommu_cntrcap_egcnt(cap); j++) {  in alloc_iommu_pmu()
693 	return 0;  in alloc_iommu_pmu()
696 	for (i = 0; i < iommu_pmu->num_cntr; i++)  in alloc_iommu_pmu()
717 		for (i = 0; i < iommu_pmu->num_cntr; i++)  in free_iommu_pmu()
732 	if (irq <= 0)  in iommu_pmu_set_interrupt()
742 		iommu->perf_irq = 0;  in iommu_pmu_set_interrupt()
745 	return 0;  in iommu_pmu_set_interrupt()
755 	iommu->perf_irq = 0;  in iommu_pmu_unset_interrupt()