Lines Matching +full:segment +full:- +full:no +full:- +full:remap
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2006-2008 Intel Corporation
14 * These routines are used by both DMA-remapping and Interrupt-remapping
35 #include "../iommu-pages.h"
50 * 1) The hotplug framework guarentees that DMAR unit will be hot-added
52 * 2) The hotplug framework guarantees that DMAR unit will be hot-removed
76 if (drhd->include_all) in dmar_register_drhd_unit()
77 list_add_tail_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
79 list_add_rcu(&drhd->list, &dmar_drhd_units); in dmar_register_drhd_unit()
89 if (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_NAMESPACE || in dmar_alloc_dev_scope()
90 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT || in dmar_alloc_dev_scope()
91 scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_alloc_dev_scope()
93 else if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_IOAPIC && in dmar_alloc_dev_scope()
94 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_HPET) { in dmar_alloc_dev_scope()
97 start += scope->length; in dmar_alloc_dev_scope()
135 if (pci_domain_nr(dev->bus) > U16_MAX) in dmar_alloc_pci_notify_info()
140 for (tmp = dev; tmp; tmp = tmp->bus->self) in dmar_alloc_pci_notify_info()
150 dmar_dev_scope_status = -ENOMEM; in dmar_alloc_pci_notify_info()
155 info->event = event; in dmar_alloc_pci_notify_info()
156 info->dev = dev; in dmar_alloc_pci_notify_info()
157 info->seg = pci_domain_nr(dev->bus); in dmar_alloc_pci_notify_info()
158 info->level = level; in dmar_alloc_pci_notify_info()
160 for (tmp = dev; tmp; tmp = tmp->bus->self) { in dmar_alloc_pci_notify_info()
161 level--; in dmar_alloc_pci_notify_info()
162 info->path[level].bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
163 info->path[level].device = PCI_SLOT(tmp->devfn); in dmar_alloc_pci_notify_info()
164 info->path[level].function = PCI_FUNC(tmp->devfn); in dmar_alloc_pci_notify_info()
165 if (pci_is_root_bus(tmp->bus)) in dmar_alloc_pci_notify_info()
166 info->bus = tmp->bus->number; in dmar_alloc_pci_notify_info()
184 if (info->bus != bus) in dmar_match_pci_path()
186 if (info->level != count) in dmar_match_pci_path()
190 if (path[i].device != info->path[i].device || in dmar_match_pci_path()
191 path[i].function != info->path[i].function) in dmar_match_pci_path()
202 i = info->level - 1; in dmar_match_pci_path()
203 if (bus == info->path[i].bus && in dmar_match_pci_path()
204 path[0].device == info->path[i].device && in dmar_match_pci_path()
205 path[0].function == info->path[i].function) { in dmar_match_pci_path()
206 pr_info(FW_BUG "RMRR entry for device %02x:%02x.%x is broken - applying workaround\n", in dmar_match_pci_path()
214 /* Return: > 0 if match found, 0 if no match found, < 0 if error happens */
216 void *start, void*end, u16 segment, in dmar_insert_dev_scope() argument
221 struct device *tmp, *dev = &info->dev->dev; in dmar_insert_dev_scope()
225 if (segment != info->seg) in dmar_insert_dev_scope()
228 for (; start < end; start += scope->length) { in dmar_insert_dev_scope()
230 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
231 scope->entry_type != ACPI_DMAR_SCOPE_TYPE_BRIDGE) in dmar_insert_dev_scope()
235 level = (scope->length - sizeof(*scope)) / sizeof(*path); in dmar_insert_dev_scope()
236 if (!dmar_match_pci_path(info, scope->bus, path, level)) in dmar_insert_dev_scope()
245 * "BRIDGE_OTHER" (0680h) - we don't declare a socpe mismatch in dmar_insert_dev_scope()
248 if ((scope->entry_type == ACPI_DMAR_SCOPE_TYPE_ENDPOINT && in dmar_insert_dev_scope()
249 info->dev->hdr_type != PCI_HEADER_TYPE_NORMAL) || in dmar_insert_dev_scope()
250 (scope->entry_type == ACPI_DMAR_SCOPE_TYPE_BRIDGE && in dmar_insert_dev_scope()
251 (info->dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in dmar_insert_dev_scope()
252 info->dev->class >> 16 != PCI_BASE_CLASS_BRIDGE))) { in dmar_insert_dev_scope()
254 pci_name(info->dev)); in dmar_insert_dev_scope()
255 return -EINVAL; in dmar_insert_dev_scope()
260 devices[i].bus = info->dev->bus->number; in dmar_insert_dev_scope()
261 devices[i].devfn = info->dev->devfn; in dmar_insert_dev_scope()
267 return -EINVAL; in dmar_insert_dev_scope()
273 int dmar_remove_dev_scope(struct dmar_pci_notify_info *info, u16 segment, in dmar_remove_dev_scope() argument
279 if (info->seg != segment) in dmar_remove_dev_scope()
283 if (tmp == &info->dev->dev) { in dmar_remove_dev_scope()
300 if (dmaru->include_all) in dmar_pci_bus_add_dev()
303 drhd = container_of(dmaru->hdr, in dmar_pci_bus_add_dev()
306 ((void *)drhd) + drhd->header.length, in dmar_pci_bus_add_dev()
307 dmaru->segment, in dmar_pci_bus_add_dev()
308 dmaru->devices, dmaru->devices_cnt); in dmar_pci_bus_add_dev()
328 if (dmar_remove_dev_scope(info, dmaru->segment, in dmar_pci_bus_del_dev()
329 dmaru->devices, dmaru->devices_cnt)) in dmar_pci_bus_del_dev()
338 dev_set_msi_domain(&pdev->dev, dev_get_msi_domain(&physfn->dev)); in vf_inherit_msi_domain()
350 if (pdev->is_virtfn) { in dmar_pci_bus_notifier()
396 if (dmaru->segment == drhd->segment && in dmar_find_dmaru()
397 dmaru->reg_base_addr == drhd->address) in dmar_find_dmaru()
404 * dmar_parse_one_drhd - parses exactly one DMA remapping hardware definition
419 dmaru = kzalloc(sizeof(*dmaru) + header->length, GFP_KERNEL); in dmar_parse_one_drhd()
421 return -ENOMEM; in dmar_parse_one_drhd()
427 dmaru->hdr = (void *)(dmaru + 1); in dmar_parse_one_drhd()
428 memcpy(dmaru->hdr, header, header->length); in dmar_parse_one_drhd()
429 dmaru->reg_base_addr = drhd->address; in dmar_parse_one_drhd()
430 dmaru->segment = drhd->segment; in dmar_parse_one_drhd()
432 dmaru->reg_size = 1UL << (drhd->size + 12); in dmar_parse_one_drhd()
433 dmaru->include_all = drhd->flags & 0x1; /* BIT0: INCLUDE_ALL */ in dmar_parse_one_drhd()
434 dmaru->devices = dmar_alloc_dev_scope((void *)(drhd + 1), in dmar_parse_one_drhd()
435 ((void *)drhd) + drhd->header.length, in dmar_parse_one_drhd()
436 &dmaru->devices_cnt); in dmar_parse_one_drhd()
437 if (dmaru->devices_cnt && dmaru->devices == NULL) { in dmar_parse_one_drhd()
439 return -ENOMEM; in dmar_parse_one_drhd()
444 dmar_free_dev_scope(&dmaru->devices, in dmar_parse_one_drhd()
445 &dmaru->devices_cnt); in dmar_parse_one_drhd()
460 if (dmaru->devices && dmaru->devices_cnt) in dmar_free_drhd()
461 dmar_free_dev_scope(&dmaru->devices, &dmaru->devices_cnt); in dmar_free_drhd()
462 if (dmaru->iommu) in dmar_free_drhd()
463 free_iommu(dmaru->iommu); in dmar_free_drhd()
473 if (strnlen(andd->device_name, header->length - 8) == header->length - 8) { in dmar_parse_one_andd()
475 "Your BIOS is broken; ANDD object name is not NUL-terminated\n" in dmar_parse_one_andd()
481 return -EINVAL; in dmar_parse_one_andd()
483 pr_info("ANDD device: %x name: %s\n", andd->device_number, in dmar_parse_one_andd()
484 andd->device_name); in dmar_parse_one_andd()
497 if (drhd->reg_base_addr == rhsa->base_address) { in dmar_parse_one_rhsa()
498 int node = pxm_to_node(rhsa->proximity_domain); in dmar_parse_one_rhsa()
502 drhd->iommu->node = node; in dmar_parse_one_rhsa()
507 "Your BIOS is broken; RHSA refers to non-existent DMAR unit at %llx\n" in dmar_parse_one_rhsa()
509 rhsa->base_address, in dmar_parse_one_rhsa()
530 switch (header->type) { in dmar_table_print_dmar_entry()
535 (unsigned long long)drhd->address, drhd->flags); in dmar_table_print_dmar_entry()
541 (unsigned long long)rmrr->base_address, in dmar_table_print_dmar_entry()
542 (unsigned long long)rmrr->end_address); in dmar_table_print_dmar_entry()
546 pr_info("ATSR flags: %#x\n", atsr->flags); in dmar_table_print_dmar_entry()
551 (unsigned long long)rhsa->base_address, in dmar_table_print_dmar_entry()
552 rhsa->proximity_domain); in dmar_table_print_dmar_entry()
555 /* We don't print this here because we need to sanity-check in dmar_table_print_dmar_entry()
560 pr_info("SATC flags: 0x%x\n", satc->flags); in dmar_table_print_dmar_entry()
566 * dmar_table_detect - checks to see if the platform supports DMAR devices
580 return ACPI_SUCCESS(status) ? 0 : -ENOENT; in dmar_table_detect()
590 next = (void *)iter + iter->length; in dmar_walk_remapping_entries()
591 if (iter->length == 0) { in dmar_walk_remapping_entries()
593 pr_debug(FW_BUG "Invalid 0-length structure\n"); in dmar_walk_remapping_entries()
598 return -EINVAL; in dmar_walk_remapping_entries()
601 if (cb->print_entry) in dmar_walk_remapping_entries()
604 if (iter->type >= ACPI_DMAR_TYPE_RESERVED) { in dmar_walk_remapping_entries()
607 iter->type); in dmar_walk_remapping_entries()
608 } else if (cb->cb[iter->type]) { in dmar_walk_remapping_entries()
611 ret = cb->cb[iter->type](iter, cb->arg[iter->type]); in dmar_walk_remapping_entries()
614 } else if (!cb->ignore_unhandled) { in dmar_walk_remapping_entries()
615 pr_warn("No handler for DMAR structure type %d\n", in dmar_walk_remapping_entries()
616 iter->type); in dmar_walk_remapping_entries()
617 return -EINVAL; in dmar_walk_remapping_entries()
628 dmar->header.length - sizeof(*dmar), cb); in dmar_walk_dmar_table()
632 * parse_dmar_table - parses the DMA reporting table
666 return -ENODEV; in parse_dmar_table()
668 if (dmar->width < PAGE_SHIFT - 1) { in parse_dmar_table()
670 return -EINVAL; in parse_dmar_table()
673 pr_info("Host address width %d\n", dmar->width + 1); in parse_dmar_table()
676 pr_warn(FW_BUG "No DRHD structure found in DMAR table\n"); in parse_dmar_table()
693 dev = dev->bus->self; in dmar_pci_device_match()
709 drhd = container_of(dmaru->hdr, in dmar_find_matched_drhd_unit()
713 if (dmaru->include_all && in dmar_find_matched_drhd_unit()
714 drhd->segment == pci_domain_nr(dev->bus)) in dmar_find_matched_drhd_unit()
717 if (dmar_pci_device_match(dmaru->devices, in dmar_find_matched_drhd_unit()
718 dmaru->devices_cnt, dev)) in dmar_find_matched_drhd_unit()
739 drhd = container_of(dmaru->hdr, in dmar_acpi_insert_dev_scope()
744 (unsigned long)scope < ((unsigned long)drhd) + drhd->header.length; in dmar_acpi_insert_dev_scope()
745 scope = ((void *)scope) + scope->length) { in dmar_acpi_insert_dev_scope()
746 if (scope->entry_type != ACPI_DMAR_SCOPE_TYPE_NAMESPACE) in dmar_acpi_insert_dev_scope()
748 if (scope->enumeration_id != device_number) in dmar_acpi_insert_dev_scope()
753 dev_name(&adev->dev), dmaru->reg_base_addr, in dmar_acpi_insert_dev_scope()
754 scope->bus, path->device, path->function); in dmar_acpi_insert_dev_scope()
755 for_each_dev_scope(dmaru->devices, dmaru->devices_cnt, i, tmp) in dmar_acpi_insert_dev_scope()
757 dmaru->devices[i].bus = scope->bus; in dmar_acpi_insert_dev_scope()
758 dmaru->devices[i].devfn = PCI_DEVFN(path->device, in dmar_acpi_insert_dev_scope()
759 path->function); in dmar_acpi_insert_dev_scope()
760 rcu_assign_pointer(dmaru->devices[i].dev, in dmar_acpi_insert_dev_scope()
761 get_device(&adev->dev)); in dmar_acpi_insert_dev_scope()
764 BUG_ON(i >= dmaru->devices_cnt); in dmar_acpi_insert_dev_scope()
767 pr_warn("No IOMMU scope found for ANDD enumeration ID %d (%s)\n", in dmar_acpi_insert_dev_scope()
768 device_number, dev_name(&adev->dev)); in dmar_acpi_insert_dev_scope()
776 return -ENODEV; in dmar_acpi_dev_scope_init()
779 ((unsigned long)andd) < ((unsigned long)dmar_tbl) + dmar_tbl->length; in dmar_acpi_dev_scope_init()
780 andd = ((void *)andd) + andd->header.length) { in dmar_acpi_dev_scope_init()
781 if (andd->header.type == ACPI_DMAR_TYPE_NAMESPACE) { in dmar_acpi_dev_scope_init()
786 andd->device_name, in dmar_acpi_dev_scope_init()
789 andd->device_name); in dmar_acpi_dev_scope_init()
795 andd->device_name); in dmar_acpi_dev_scope_init()
798 dmar_acpi_insert_dev_scope(andd->device_number, adev); in dmar_acpi_dev_scope_init()
813 dmar_dev_scope_status = -ENODEV; in dmar_dev_scope_init()
820 if (dev->is_virtfn) in dmar_dev_scope_init()
852 if (ret != -ENODEV) in dmar_table_init()
855 pr_info("No DMAR devices found\n"); in dmar_table_init()
856 ret = -ENODEV; in dmar_table_init()
888 if (!drhd->address) { in dmar_validate_one_drhd()
890 return -EINVAL; in dmar_validate_one_drhd()
894 addr = ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
896 addr = early_ioremap(drhd->address, VTD_PAGE_SIZE); in dmar_validate_one_drhd()
898 pr_warn("Can't validate DRHD address: %llx\n", drhd->address); in dmar_validate_one_drhd()
899 return -EINVAL; in dmar_validate_one_drhd()
910 if (cap == (uint64_t)-1 && ecap == (uint64_t)-1) { in dmar_validate_one_drhd()
911 warn_invalid_dmar(drhd->address, " returns all ones"); in dmar_validate_one_drhd()
912 return -EINVAL; in dmar_validate_one_drhd()
955 iounmap(iommu->reg); in unmap_iommu()
956 release_mem_region(iommu->reg_phys, iommu->reg_size); in unmap_iommu()
969 u64 phys_addr = drhd->reg_base_addr; in map_iommu()
972 iommu->reg_phys = phys_addr; in map_iommu()
973 iommu->reg_size = drhd->reg_size; in map_iommu()
975 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, iommu->name)) { in map_iommu()
977 err = -EBUSY; in map_iommu()
981 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
982 if (!iommu->reg) { in map_iommu()
984 err = -ENOMEM; in map_iommu()
988 iommu->cap = dmar_readq(iommu->reg + DMAR_CAP_REG); in map_iommu()
989 iommu->ecap = dmar_readq(iommu->reg + DMAR_ECAP_REG); in map_iommu()
991 if (iommu->cap == (uint64_t)-1 && iommu->ecap == (uint64_t)-1) { in map_iommu()
992 err = -EINVAL; in map_iommu()
998 map_size = max_t(int, ecap_max_iotlb_offset(iommu->ecap), in map_iommu()
999 cap_max_fault_reg_offset(iommu->cap)); in map_iommu()
1001 if (map_size > iommu->reg_size) { in map_iommu()
1002 iounmap(iommu->reg); in map_iommu()
1003 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1004 iommu->reg_size = map_size; in map_iommu()
1005 if (!request_mem_region(iommu->reg_phys, iommu->reg_size, in map_iommu()
1006 iommu->name)) { in map_iommu()
1008 err = -EBUSY; in map_iommu()
1011 iommu->reg = ioremap(iommu->reg_phys, iommu->reg_size); in map_iommu()
1012 if (!iommu->reg) { in map_iommu()
1014 err = -ENOMEM; in map_iommu()
1019 if (cap_ecmds(iommu->cap)) { in map_iommu()
1023 iommu->ecmdcap[i] = dmar_readq(iommu->reg + DMAR_ECCAP_REG + in map_iommu()
1032 iounmap(iommu->reg); in map_iommu()
1034 release_mem_region(iommu->reg_phys, iommu->reg_size); in map_iommu()
1043 int agaw = -1; in alloc_iommu()
1044 int msagaw = -1; in alloc_iommu()
1047 if (!drhd->reg_base_addr) { in alloc_iommu()
1049 return -EINVAL; in alloc_iommu()
1054 return -ENOMEM; in alloc_iommu()
1056 iommu->seq_id = ida_alloc_range(&dmar_seq_ids, 0, in alloc_iommu()
1057 DMAR_UNITS_SUPPORTED - 1, GFP_KERNEL); in alloc_iommu()
1058 if (iommu->seq_id < 0) { in alloc_iommu()
1060 err = iommu->seq_id; in alloc_iommu()
1063 sprintf(iommu->name, "dmar%d", iommu->seq_id); in alloc_iommu()
1067 pr_err("Failed to map %s\n", iommu->name); in alloc_iommu()
1071 if (!cap_sagaw(iommu->cap) && in alloc_iommu()
1072 (!ecap_smts(iommu->ecap) || ecap_slts(iommu->ecap))) { in alloc_iommu()
1073 pr_info("%s: No supported address widths. Not attempting DMA translation.\n", in alloc_iommu()
1074 iommu->name); in alloc_iommu()
1075 drhd->ignored = 1; in alloc_iommu()
1078 if (!drhd->ignored) { in alloc_iommu()
1082 iommu->seq_id); in alloc_iommu()
1083 drhd->ignored = 1; in alloc_iommu()
1086 if (!drhd->ignored) { in alloc_iommu()
1090 iommu->seq_id); in alloc_iommu()
1091 drhd->ignored = 1; in alloc_iommu()
1092 agaw = -1; in alloc_iommu()
1095 iommu->agaw = agaw; in alloc_iommu()
1096 iommu->msagaw = msagaw; in alloc_iommu()
1097 iommu->segment = drhd->segment; in alloc_iommu()
1098 iommu->device_rbtree = RB_ROOT; in alloc_iommu()
1099 spin_lock_init(&iommu->device_rbtree_lock); in alloc_iommu()
1100 mutex_init(&iommu->iopf_lock); in alloc_iommu()
1101 iommu->node = NUMA_NO_NODE; in alloc_iommu()
1103 ver = readl(iommu->reg + DMAR_VER_REG); in alloc_iommu()
1105 iommu->name, in alloc_iommu()
1106 (unsigned long long)drhd->reg_base_addr, in alloc_iommu()
1108 (unsigned long long)iommu->cap, in alloc_iommu()
1109 (unsigned long long)iommu->ecap); in alloc_iommu()
1112 sts = readl(iommu->reg + DMAR_GSTS_REG); in alloc_iommu()
1114 iommu->gcmd |= DMA_GCMD_IRE; in alloc_iommu()
1116 iommu->gcmd |= DMA_GCMD_TE; in alloc_iommu()
1118 iommu->gcmd |= DMA_GCMD_QIE; in alloc_iommu()
1121 pr_debug("Cannot alloc PMU for iommu (seq_id = %d)\n", iommu->seq_id); in alloc_iommu()
1123 raw_spin_lock_init(&iommu->register_lock); in alloc_iommu()
1130 iommu->iommu.max_pasids = 2UL << ecap_pss(iommu->ecap); in alloc_iommu()
1137 if (intel_iommu_enabled && !drhd->ignored) { in alloc_iommu()
1138 err = iommu_device_sysfs_add(&iommu->iommu, NULL, in alloc_iommu()
1140 "%s", iommu->name); in alloc_iommu()
1144 err = iommu_device_register(&iommu->iommu, &intel_iommu_ops, NULL); in alloc_iommu()
1151 drhd->iommu = iommu; in alloc_iommu()
1152 iommu->drhd = drhd; in alloc_iommu()
1157 iommu_device_sysfs_remove(&iommu->iommu); in alloc_iommu()
1162 ida_free(&dmar_seq_ids, iommu->seq_id); in alloc_iommu()
1170 if (intel_iommu_enabled && !iommu->drhd->ignored) { in free_iommu()
1172 iommu_device_unregister(&iommu->iommu); in free_iommu()
1173 iommu_device_sysfs_remove(&iommu->iommu); in free_iommu()
1178 if (iommu->irq) { in free_iommu()
1179 if (iommu->pr_irq) { in free_iommu()
1180 free_irq(iommu->pr_irq, iommu); in free_iommu()
1181 dmar_free_hwirq(iommu->pr_irq); in free_iommu()
1182 iommu->pr_irq = 0; in free_iommu()
1184 free_irq(iommu->irq, iommu); in free_iommu()
1185 dmar_free_hwirq(iommu->irq); in free_iommu()
1186 iommu->irq = 0; in free_iommu()
1189 if (iommu->qi) { in free_iommu()
1190 iommu_free_page(iommu->qi->desc); in free_iommu()
1191 kfree(iommu->qi->desc_status); in free_iommu()
1192 kfree(iommu->qi); in free_iommu()
1195 if (iommu->reg) in free_iommu()
1198 ida_free(&dmar_seq_ids, iommu->seq_id); in free_iommu()
1207 while (qi->desc_status[qi->free_tail] == QI_FREE && qi->free_tail != qi->free_head) { in reclaim_free_desc()
1208 qi->free_tail = (qi->free_tail + 1) % QI_LENGTH; in reclaim_free_desc()
1209 qi->free_cnt++; in reclaim_free_desc()
1217 return "Context-cache Invalidation"; in qi_type_string()
1221 return "Device-TLB Invalidation"; in qi_type_string()
1227 return "PASID-based IOTLB Invalidation"; in qi_type_string()
1229 return "PASID-cache Invalidation"; in qi_type_string()
1231 return "PASID-based Device-TLB Invalidation"; in qi_type_string()
1241 unsigned int head = dmar_readl(iommu->reg + DMAR_IQH_REG); in qi_dump_fault()
1242 u64 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); in qi_dump_fault()
1243 struct qi_desc *desc = iommu->qi->desc + head; in qi_dump_fault()
1246 pr_err("VT-d detected Invalidation Queue Error: Reason %llx", in qi_dump_fault()
1249 pr_err("VT-d detected Invalidation Time-out Error: SID %llx", in qi_dump_fault()
1252 pr_err("VT-d detected Invalidation Completion Error: SID %llx", in qi_dump_fault()
1256 qi_type_string(desc->qw0 & 0xf), in qi_dump_fault()
1257 (unsigned long long)desc->qw0, in qi_dump_fault()
1258 (unsigned long long)desc->qw1); in qi_dump_fault()
1260 head = ((head >> qi_shift(iommu)) + QI_LENGTH - 1) % QI_LENGTH; in qi_dump_fault()
1262 desc = iommu->qi->desc + head; in qi_dump_fault()
1265 qi_type_string(desc->qw0 & 0xf), in qi_dump_fault()
1266 (unsigned long long)desc->qw0, in qi_dump_fault()
1267 (unsigned long long)desc->qw1); in qi_dump_fault()
1276 struct q_inval *qi = iommu->qi; in qi_check_fault()
1279 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1280 return -EAGAIN; in qi_check_fault()
1282 fault = readl(iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1288 * with the error. No new descriptors are fetched until the IQE in qi_check_fault()
1292 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1294 struct qi_desc *desc = qi->desc + head; in qi_check_fault()
1297 * desc->qw2 and desc->qw3 are either reserved or in qi_check_fault()
1301 memcpy(desc, qi->desc + (wait_index << shift), in qi_check_fault()
1303 writel(DMA_FSTS_IQE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1305 return -EINVAL; in qi_check_fault()
1311 * No new descriptors are fetched until the ITE is cleared. in qi_check_fault()
1314 head = readl(iommu->reg + DMAR_IQH_REG); in qi_check_fault()
1315 head = ((head >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1317 tail = readl(iommu->reg + DMAR_IQT_REG); in qi_check_fault()
1318 tail = ((tail >> shift) - 1 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1322 * see Intel VT-d spec r4.1, section 11.4.9.9 in qi_check_fault()
1324 iqe_err = dmar_readq(iommu->reg + DMAR_IQER_REG); in qi_check_fault()
1327 writel(DMA_FSTS_ITE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1328 pr_info("Invalidation Time-out Error (ITE) cleared\n"); in qi_check_fault()
1331 if (qi->desc_status[head] == QI_IN_USE) in qi_check_fault()
1332 qi->desc_status[head] = QI_ABORT; in qi_check_fault()
1333 head = (head - 2 + QI_LENGTH) % QI_LENGTH; in qi_check_fault()
1337 * If device was released or isn't present, no need to retry in qi_check_fault()
1340 * 0 value of ite_sid means old VT-d device, no ite_sid value. in qi_check_fault()
1341 * see Intel VT-d spec r4.1, section 11.4.9.9 in qi_check_fault()
1347 return -ETIMEDOUT; in qi_check_fault()
1349 if (qi->desc_status[wait_index] == QI_ABORT) in qi_check_fault()
1350 return -EAGAIN; in qi_check_fault()
1354 writel(DMA_FSTS_ICE, iommu->reg + DMAR_FSTS_REG); in qi_check_fault()
1371 struct q_inval *qi = iommu->qi; in qi_submit_sync()
1385 type = desc->qw0 & GENMASK_ULL(3, 0); in qi_submit_sync()
1402 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1408 while (qi->free_cnt < count + 2) { in qi_submit_sync()
1409 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1411 raw_spin_lock_irqsave(&qi->q_lock, flags); in qi_submit_sync()
1414 index = qi->free_head; in qi_submit_sync()
1420 memcpy(qi->desc + offset, &desc[i], 1 << shift); in qi_submit_sync()
1421 qi->desc_status[(index + i) % QI_LENGTH] = QI_IN_USE; in qi_submit_sync()
1425 qi->desc_status[wait_index] = QI_IN_USE; in qi_submit_sync()
1431 wait_desc.qw1 = virt_to_phys(&qi->desc_status[wait_index]); in qi_submit_sync()
1436 memcpy(qi->desc + offset, &wait_desc, 1 << shift); in qi_submit_sync()
1438 qi->free_head = (qi->free_head + count + 1) % QI_LENGTH; in qi_submit_sync()
1439 qi->free_cnt -= count + 1; in qi_submit_sync()
1445 writel(qi->free_head << shift, iommu->reg + DMAR_IQT_REG); in qi_submit_sync()
1447 while (READ_ONCE(qi->desc_status[wait_index]) != QI_DONE) { in qi_submit_sync()
1459 raw_spin_unlock(&qi->q_lock); in qi_submit_sync()
1461 raw_spin_lock(&qi->q_lock); in qi_submit_sync()
1473 qi->desc_status[(index + i) % QI_LENGTH] = QI_FREE; in qi_submit_sync()
1476 raw_spin_unlock_irqrestore(&qi->q_lock, flags); in qi_submit_sync()
1478 if (rc == -EAGAIN) in qi_submit_sync()
1483 ktime_to_ns(ktime_get()) - iotlb_start_ktime); in qi_submit_sync()
1487 ktime_to_ns(ktime_get()) - devtlb_start_ktime); in qi_submit_sync()
1491 ktime_to_ns(ktime_get()) - iec_start_ktime); in qi_submit_sync()
1541 * VT-d spec, section 4.3: in qi_flush_dev_iotlb()
1543 * Software is recommended to not submit any Device-TLB invalidation in qi_flush_dev_iotlb()
1546 if (!(iommu->gcmd & DMA_GCMD_TE)) in qi_flush_dev_iotlb()
1553 /* PASID-based IOTLB invalidation */
1560 * npages == -1 means a PASID-selective invalidation, otherwise, in qi_flush_piotlb()
1561 * a positive value for Page-selective-within-PASID invalidation. in qi_flush_piotlb()
1573 /* PASID-based device IOTLB Invalidate */
1580 * VT-d spec, section 4.3: in qi_flush_dev_iotlb_pasid()
1582 * Software is recommended to not submit any Device-TLB invalidation in qi_flush_dev_iotlb_pasid()
1585 if (!(iommu->gcmd & DMA_GCMD_TE)) in qi_flush_dev_iotlb_pasid()
1613 if (!ecap_qis(iommu->ecap)) in dmar_disable_qi()
1616 raw_spin_lock_irqsave(&iommu->register_lock, flags); in dmar_disable_qi()
1618 sts = readl(iommu->reg + DMAR_GSTS_REG); in dmar_disable_qi()
1625 while ((readl(iommu->reg + DMAR_IQT_REG) != in dmar_disable_qi()
1626 readl(iommu->reg + DMAR_IQH_REG)) && in dmar_disable_qi()
1627 (DMAR_OPERATION_TIMEOUT > (get_cycles() - start_time))) in dmar_disable_qi()
1630 iommu->gcmd &= ~DMA_GCMD_QIE; in dmar_disable_qi()
1631 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in dmar_disable_qi()
1636 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in dmar_disable_qi()
1646 struct q_inval *qi = iommu->qi; in __dmar_enable_qi()
1647 u64 val = virt_to_phys(qi->desc); in __dmar_enable_qi()
1649 qi->free_head = qi->free_tail = 0; in __dmar_enable_qi()
1650 qi->free_cnt = QI_LENGTH; in __dmar_enable_qi()
1656 if (ecap_smts(iommu->ecap)) in __dmar_enable_qi()
1659 raw_spin_lock_irqsave(&iommu->register_lock, flags); in __dmar_enable_qi()
1662 writel(0, iommu->reg + DMAR_IQT_REG); in __dmar_enable_qi()
1664 dmar_writeq(iommu->reg + DMAR_IQA_REG, val); in __dmar_enable_qi()
1666 iommu->gcmd |= DMA_GCMD_QIE; in __dmar_enable_qi()
1667 writel(iommu->gcmd, iommu->reg + DMAR_GCMD_REG); in __dmar_enable_qi()
1672 raw_spin_unlock_irqrestore(&iommu->register_lock, flags); in __dmar_enable_qi()
1677 * interrupt-remapping. Also used by DMA-remapping, which replaces
1686 if (!ecap_qis(iommu->ecap)) in dmar_enable_qi()
1687 return -ENOENT; in dmar_enable_qi()
1692 if (iommu->qi) in dmar_enable_qi()
1695 iommu->qi = kmalloc(sizeof(*qi), GFP_ATOMIC); in dmar_enable_qi()
1696 if (!iommu->qi) in dmar_enable_qi()
1697 return -ENOMEM; in dmar_enable_qi()
1699 qi = iommu->qi; in dmar_enable_qi()
1705 order = ecap_smts(iommu->ecap) ? 1 : 0; in dmar_enable_qi()
1706 desc = iommu_alloc_pages_node(iommu->node, GFP_ATOMIC, order); in dmar_enable_qi()
1709 iommu->qi = NULL; in dmar_enable_qi()
1710 return -ENOMEM; in dmar_enable_qi()
1713 qi->desc = desc; in dmar_enable_qi()
1715 qi->desc_status = kcalloc(QI_LENGTH, sizeof(int), GFP_ATOMIC); in dmar_enable_qi()
1716 if (!qi->desc_status) { in dmar_enable_qi()
1717 iommu_free_page(qi->desc); in dmar_enable_qi()
1719 iommu->qi = NULL; in dmar_enable_qi()
1720 return -ENOMEM; in dmar_enable_qi()
1723 raw_spin_lock_init(&qi->q_lock); in dmar_enable_qi()
1730 /* iommu interrupt handling. Most stuff are MSI-like. */
1750 "non-zero reserved fields in RTP",
1751 "non-zero reserved fields in CTP",
1752 "non-zero reserved fields in PTE",
1760 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x33-0x37 */
1763 "SM: Non-zero reserved field set in Root Entry",
1764 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x3B-0x3F */
1767 "SM: Non-zero reserved field set in the Context Entry",
1772 "SM: PRE field in Context-Entry is clear",
1773 "SM: RID_PASID field error in Context-Entry",
1774 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x49-0x4F */
1777 "SM: Non-zero reserved field set in PASID Directory Entry",
1778 "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x53-0x57 */
1781 "SM: Non-zero reserved field set in PASID Table Entry",
1782 "SM: Invalid Scalable-Mode PASID Table Entry",
1785 "Unknown", "Unknown",/* 0x5E-0x5F */
1786 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x60-0x…
1787 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x68-0x…
1788 "SM: Error attempting to access first-level paging entry",
1789 "SM: Present bit in first-level paging entry is clear",
1790 "SM: Non-zero reserved field set in first-level paging entry",
1791 "SM: Error attempting to access FL-PML4 entry",
1792 "SM: First-level entry address beyond MGAW in Nested translation",
1793 "SM: Read permission error in FL-PML4 entry in Nested translation",
1794 "SM: Read permission error in first-level paging entry in Nested translation",
1795 "SM: Write permission error in first-level paging entry in Nested translation",
1796 "SM: Error attempting to access second-level paging entry",
1797 "SM: Read/Write permission error in second-level paging entry",
1798 "SM: Non-zero reserved field set in second-level paging entry",
1799 "SM: Invalid second-level page table pointer",
1800 "SM: A/D bit update needed in second-level entry when set up in no snoop",
1801 "Unknown", "Unknown", "Unknown", /* 0x7D-0x7F */
1802 "SM: Address in first-level translation is not canonical",
1803 "SM: U/S set 0 for first-level translation with user privilege",
1804 "SM: No execute permission for request with PASID and ER=1",
1806 "SM: Second-level entry address beyond the max",
1807 "SM: No write permission for Write/AtomicOp request",
1808 "SM: No read permission for Read/AtomicOp request",
1809 "SM: Invalid address-interrupt address",
1810 …"Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", "Unknown", /* 0x88-0x…
1811 "SM: A/D bit update needed in first-level entry when set up in no snoop",
1816 "Detected reserved fields in the decoded interrupt-remapped request",
1817 "Interrupt index exceeded the interrupt-remapping table size",
1819 "Error accessing interrupt-remapping table pointed by IRTA_REG",
1822 "Blocked an interrupt request due to source-id verification failure",
1827 if (fault_reason >= 0x20 && (fault_reason - 0x20 < in dmar_get_fault_reason()
1830 return irq_remap_fault_reasons[fault_reason - 0x20]; in dmar_get_fault_reason()
1831 } else if (fault_reason >= 0x30 && (fault_reason - 0x30 < in dmar_get_fault_reason()
1834 return dma_remap_sm_fault_reasons[fault_reason - 0x30]; in dmar_get_fault_reason()
1847 if (iommu->irq == irq) in dmar_msi_reg()
1849 else if (iommu->pr_irq == irq) in dmar_msi_reg()
1851 else if (iommu->perf_irq == irq) in dmar_msi_reg()
1860 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_unmask()
1864 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_unmask()
1865 writel(0, iommu->reg + reg); in dmar_msi_unmask()
1867 readl(iommu->reg + reg); in dmar_msi_unmask()
1868 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_unmask()
1874 int reg = dmar_msi_reg(iommu, data->irq); in dmar_msi_mask()
1878 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_mask()
1879 writel(DMA_FECTL_IM, iommu->reg + reg); in dmar_msi_mask()
1881 readl(iommu->reg + reg); in dmar_msi_mask()
1882 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_mask()
1891 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_write()
1892 writel(msg->data, iommu->reg + reg + 4); in dmar_msi_write()
1893 writel(msg->address_lo, iommu->reg + reg + 8); in dmar_msi_write()
1894 writel(msg->address_hi, iommu->reg + reg + 12); in dmar_msi_write()
1895 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_write()
1904 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_msi_read()
1905 msg->data = readl(iommu->reg + reg + 4); in dmar_msi_read()
1906 msg->address_lo = readl(iommu->reg + reg + 8); in dmar_msi_read()
1907 msg->address_hi = readl(iommu->reg + reg + 12); in dmar_msi_read()
1908 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_msi_read()
1921 pr_err("[INTR-REMAP] Request device [%02x:%02x.%d] fault index 0x%llx [fault reason 0x%02x] %s\n", in dmar_fault_do_one()
1958 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
1959 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in dmar_fault()
1968 reg = cap_fault_reg_offset(iommu->cap); in dmar_fault()
1981 data = readl(iommu->reg + reg + in dmar_fault()
1991 data = readl(iommu->reg + reg + in dmar_fault()
1996 guest_addr = dmar_readq(iommu->reg + reg + in dmar_fault()
2002 writel(DMA_FRCD_F, iommu->reg + reg + in dmar_fault()
2005 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2008 /* Using pasid -1 if pasid is not present */ in dmar_fault()
2014 if (fault_index >= cap_num_fault_regs(iommu->cap)) in dmar_fault()
2016 raw_spin_lock_irqsave(&iommu->register_lock, flag); in dmar_fault()
2020 iommu->reg + DMAR_FSTS_REG); in dmar_fault()
2023 raw_spin_unlock_irqrestore(&iommu->register_lock, flag); in dmar_fault()
2034 if (iommu->irq) in dmar_set_interrupt()
2037 irq = dmar_alloc_hwirq(iommu->seq_id, iommu->node, iommu); in dmar_set_interrupt()
2039 iommu->irq = irq; in dmar_set_interrupt()
2041 pr_err("No free IRQ vectors\n"); in dmar_set_interrupt()
2042 return -EINVAL; in dmar_set_interrupt()
2045 ret = request_irq(irq, dmar_fault, IRQF_NO_THREAD, iommu->name, iommu); in dmar_set_interrupt()
2063 if (iommu->irq || iommu->node != cpu_to_node(cpu)) in enable_drhd_fault_handling()
2070 (unsigned long long)drhd->reg_base_addr, ret); in enable_drhd_fault_handling()
2071 return -1; in enable_drhd_fault_handling()
2077 dmar_fault(iommu->irq, iommu); in enable_drhd_fault_handling()
2078 fault_status = readl(iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2079 writel(fault_status, iommu->reg + DMAR_FSTS_REG); in enable_drhd_fault_handling()
2086 * Re-enable Queued Invalidation interface.
2090 if (!ecap_qis(iommu->ecap)) in dmar_reenable_qi()
2091 return -ENOENT; in dmar_reenable_qi()
2093 if (!iommu->qi) in dmar_reenable_qi()
2094 return -ENOENT; in dmar_reenable_qi()
2101 * Then enable queued invalidation again. Since there is no pending in dmar_reenable_qi()
2102 * invalidation requests now, it's safe to re-enable queued in dmar_reenable_qi()
2119 return dmar->flags & 0x1; in dmar_ir_support()
2140 list_del(&dmaru->list); in dmar_free_unused_resources()
2153 * for Directed-IO Architecture Specifiction, Rev 2.2, Section 8.8
2178 int ret = -ENODEV; in dmar_walk_dsm_resource()
2195 return -ENODEV; in dmar_walk_dsm_resource()
2200 start = (struct acpi_dmar_header *)obj->buffer.pointer; in dmar_walk_dsm_resource()
2201 ret = dmar_walk_remapping_entries(start, obj->buffer.length, &callback); in dmar_walk_dsm_resource()
2215 return -ENODEV; in dmar_hp_add_drhd()
2237 if (!dmaru->include_all && dmaru->devices && dmaru->devices_cnt) { in dmar_hp_remove_drhd()
2238 for_each_active_dev_scope(dmaru->devices, in dmar_hp_remove_drhd()
2239 dmaru->devices_cnt, i, dev) in dmar_hp_remove_drhd()
2240 return -EBUSY; in dmar_hp_remove_drhd()
2256 list_del_rcu(&dmaru->list); in dmar_hp_release_drhd()
2277 pr_warn(FW_BUG "No DRHD structures in buffer returned by _DSM method\n"); in dmar_hotplug_insert()
2365 return -ENXIO; in dmar_device_hotplug()
2392 * dmar_platform_optin - Is %DMA_CTRL_PLATFORM_OPT_IN_FLAG set in DMAR table
2396 * sure no device can issue DMA outside of RMRR regions.
2409 ret = !!(dmar->flags & DMAR_PLATFORM_OPT_IN); in dmar_platform_optin()