45 			   ((*(sent) & 3) == 0) || ((*(sent) & 3) == 3))
52 #define lv2ent_fault(pent) ((*(pent) & 3) == 0)
58  * v5.0 introduced support for 36bit physical address space by shifting
62  * value (0 or 4).
65 #define SYSMMU_PG_ENT_SHIFT 0
70 	((0 << 15) | (0 << 10)), /* no access */
72 	((0 << 15) | (1 << 10)), /* IOMMU_WRITE not supported, use read/write */
73 	((0 << 15) | (1 << 10)), /* IOMMU_READ | IOMMU_WRITE */
76 	(0 << 4), /* no access */
84 	((0 << 9) | (0 << 4)), /* no access */
86 	((0 << 9) | (1 << 4)), /* IOMMU_WRITE not supported, use read/write */
87 	((0 << 9) | (1 << 4)), /* IOMMU_READ | IOMMU_WRITE */
90 	(0 << 2), /* no access */
123 #define lv2table_base(sent) (sect_to_phys(*(sent) & 0xFFFFFFC0))
130 #define CTRL_ENABLE	0x5
131 #define CTRL_BLOCK	0x7
132 #define CTRL_DISABLE	0x0
134 #define CFG_LRU		0x1
136 #define CFG_QOS(n)	((n & 0xF) << 7)
141 #define CTRL_VM_ENABLE			BIT(0)
147 #define REG_MMU_CTRL		0x000
148 #define REG_MMU_CFG		0x004
149 #define REG_MMU_STATUS		0x008
150 #define REG_MMU_VERSION		0x034
153 #define MMU_MIN_VER(val)	((val) & 0x7F)
156 #define MAKE_MMU_VER(maj, min)	((((maj) & 0xF) << 7) | ((min) & 0x7F))
159 #define REG_PAGE_FAULT_ADDR	0x024
160 #define REG_AW_FAULT_ADDR	0x028
161 #define REG_AR_FAULT_ADDR	0x02C
162 #define REG_DEFAULT_SLAVE_ADDR	0x030
165 #define REG_V5_FAULT_AR_VA	0x070
166 #define REG_V5_FAULT_AW_VA	0x080
169 #define REG_V7_CAPA0		0x870
170 #define REG_V7_CAPA1		0x874
171 #define REG_V7_CTRL_VM		0x8000
214 /* SysMMU v5 has the same faults for AR (0..4 bits) and AW (16..20 bits) */
326 	return 0;  in exynos_sysmmu_v1_get_fault_info()
349 	return 0;  in exynos_sysmmu_v5_get_fault_info()
362 	return 0;  in exynos_sysmmu_v7_get_fault_info()
367 	.flush_all	= 0x0c,
368 	.flush_entry	= 0x10,
369 	.pt_base	= 0x14,
370 	.int_status	= 0x18,
371 	.int_clear	= 0x1c,
378 	.pt_base	= 0x0c,
379 	.flush_all	= 0x10,
380 	.flush_entry	= 0x14,
381 	.flush_range	= 0x18,
382 	.flush_start	= 0x20,
383 	.flush_end	= 0x24,
384 	.int_status	= 0x60,
385 	.int_clear	= 0x64,
392 	.pt_base	= 0x0c,
393 	.flush_all	= 0x10,
394 	.flush_entry	= 0x14,
395 	.flush_range	= 0x18,
396 	.flush_start	= 0x20,
397 	.flush_end	= 0x24,
398 	.int_status	= 0x60,
399 	.int_clear	= 0x64,
400 	.fault_va	= 0x70,
401 	.fault_info	= 0x78,
408 	.pt_base	= 0x800c,
409 	.flush_all	= 0x8010,
410 	.flush_entry	= 0x8014,
411 	.flush_range	= 0x8018,
412 	.flush_start	= 0x8020,
413 	.flush_end	= 0x8024,
414 	.int_status	= 0x60,
415 	.int_clear	= 0x64,
416 	.fault_va	= 0x1000,
417 	.fault_info	= 0x1004,
437 	while ((i > 0) && !(readl(data->sfrbase + REG_MMU_STATUS) & 1))  in sysmmu_block()
450 	writel(0x1, SYSMMU_REG(data, flush_all));  in __sysmmu_tlb_invalidate()
459 		for (i = 0; i < num_inv; i++) {  in __sysmmu_tlb_invalidate_entry()
468 		writel(0x1, SYSMMU_REG(data, flush_range));  in __sysmmu_tlb_invalidate_entry()
524 	if (ver == 0x80000001u)  in __sysmmu_get_version()
525 		data->version = MAKE_MMU_VER(1, 0);  in __sysmmu_get_version()
612 	writel(0, data->sfrbase + REG_MMU_CFG);  in __sysmmu_disable()
680 			if (data->version >= MAKE_MMU_VER(5, 0))  in sysmmu_tlb_invalidate_flpdcache()
737 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);  in exynos_sysmmu_probe()
742 	irq = platform_get_irq(pdev, 0);  in exynos_sysmmu_probe()
743 	if (irq <= 0)  in exynos_sysmmu_probe()
746 	ret = devm_request_irq(dev, irq, exynos_sysmmu_irq, 0,  in exynos_sysmmu_probe()
786 	if (PG_ENT_SHIFT < 0) {  in exynos_sysmmu_probe()
819 	return 0;  in exynos_sysmmu_probe()
841 	return 0;  in exynos_sysmmu_suspend()
859 	return 0;  in exynos_sysmmu_resume()
899 	BUG_ON(PG_ENT_SHIFT < 0 || !dma_dev);  in exynos_iommu_domain_alloc_paging()
914 	for (i = 0; i < NUM_LV1ENTRIES; i++)  in exynos_iommu_domain_alloc_paging()
928 	domain->domain.geometry.aperture_start = 0;  in exynos_iommu_domain_alloc_paging()
929 	domain->domain.geometry.aperture_end   = ~0UL;  in exynos_iommu_domain_alloc_paging()
957 		data->pgtable = 0;  in exynos_iommu_domain_free()
968 	for (i = 0; i < NUM_LV1ENTRIES; i++)  in exynos_iommu_domain_free()
993 		return 0;  in exynos_iommu_identity_attach()
1010 		data->pgtable = 0;  in exynos_iommu_identity_attach()
1022 	return 0;  in exynos_iommu_identity_attach()
1073 	return 0;  in exynos_iommu_attach_device()
1151 		kmem_cache_free(lv2table_kmem_cache, page_entry(sent, 0));  in lv1set_section()
1152 		*pgcnt = 0;  in lv1set_section()
1169 	return 0;  in lv1set_section()
1188 		for (i = 0; i < SPAGES_PER_LPAGE; i++, pent++) {  in lv2set_page()
1190 				if (i > 0)  in lv2set_page()
1191 					memset(pent - i, 0, sizeof(*pent) * i);  in lv2set_page()
1203 	return 0;  in lv2set_page()
1334 		exynos_iommu_set_pte(ent, 0);  in exynos_iommu_unmap()
1349 	memset(ent, 0, sizeof(*ent) * SPAGES_PER_LPAGE);  in exynos_iommu_unmap()
1367 	return 0;  in exynos_iommu_unmap()
1376 	phys_addr_t phys = 0;  in exynos_iommu_iova_to_phys()
1466 			return 0;  in exynos_iommu_of_xlate()
1471 	return 0;  in exynos_iommu_of_xlate()
1498 		return 0;  in exynos_iommu_init()
1503 				LV2TABLE_SIZE, LV2TABLE_SIZE, 0, NULL);  in exynos_iommu_init()
1523 	return 0;  in exynos_iommu_init()