Lines Matching full:smmu
3 * IOMMU API for ARM architected SMMU implementations.
13 * - Non-secure access to the SMMU
18 #define pr_fmt(fmt) "arm-smmu: " fmt
40 #include "arm-smmu.h"
44 * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
58 …"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' f…
63 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
71 static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) in arm_smmu_rpm_get() argument
73 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_get()
74 return pm_runtime_resume_and_get(smmu->dev); in arm_smmu_rpm_get()
79 static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) in arm_smmu_rpm_put() argument
81 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_put()
82 pm_runtime_put_autosuspend(smmu->dev); in arm_smmu_rpm_put()
85 static void arm_smmu_rpm_use_autosuspend(struct arm_smmu_device *smmu) in arm_smmu_rpm_use_autosuspend() argument
98 pm_runtime_set_autosuspend_delay(smmu->dev, 20); in arm_smmu_rpm_use_autosuspend()
99 pm_runtime_use_autosuspend(smmu->dev); in arm_smmu_rpm_use_autosuspend()
147 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
189 *smmu = dev_get_drvdata(smmu_dev); in arm_smmu_register_legacy_master()
197 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
209 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in __arm_smmu_tlb_sync() argument
215 if (smmu->impl && unlikely(smmu->impl->tlb_sync)) in __arm_smmu_tlb_sync()
216 return smmu->impl->tlb_sync(smmu, page, sync, status); in __arm_smmu_tlb_sync()
218 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in __arm_smmu_tlb_sync()
221 reg = arm_smmu_readl(smmu, page, status); in __arm_smmu_tlb_sync()
228 dev_err_ratelimited(smmu->dev, in __arm_smmu_tlb_sync()
229 "TLB sync timed out -- SMMU may be deadlocked\n"); in __arm_smmu_tlb_sync()
232 static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu) in arm_smmu_tlb_sync_global() argument
236 spin_lock_irqsave(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
237 __arm_smmu_tlb_sync(smmu, ARM_SMMU_GR0, ARM_SMMU_GR0_sTLBGSYNC, in arm_smmu_tlb_sync_global()
239 spin_unlock_irqrestore(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
244 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_sync_context() local
248 __arm_smmu_tlb_sync(smmu, ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx), in arm_smmu_tlb_sync_context()
261 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
269 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context_s2() local
273 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_inv_context_s2()
274 arm_smmu_tlb_sync_global(smmu); in arm_smmu_tlb_inv_context_s2()
281 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s1() local
285 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s1()
292 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
299 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
309 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s2() local
312 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s2()
318 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
320 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
381 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_add_page_s2_v1() local
383 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_add_page_s2_v1()
386 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_add_page_s2_v1()
408 void arm_smmu_read_context_fault_info(struct arm_smmu_device *smmu, int idx, in arm_smmu_read_context_fault_info() argument
411 cfi->iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); in arm_smmu_read_context_fault_info()
412 cfi->fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); in arm_smmu_read_context_fault_info()
413 cfi->fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); in arm_smmu_read_context_fault_info()
414 cfi->cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); in arm_smmu_read_context_fault_info()
417 void arm_smmu_print_context_fault_info(struct arm_smmu_device *smmu, int idx, in arm_smmu_print_context_fault_info() argument
420 dev_err(smmu->dev, in arm_smmu_print_context_fault_info()
424 dev_err(smmu->dev, "FSR = %08x [%s%sFormat=%u%s%s%s%s%s%s%s%s], SID=0x%x\n", in arm_smmu_print_context_fault_info()
439 dev_err(smmu->dev, "FSYNR0 = %08x [S1CBNDX=%u%s%s%s%s%s%s PLVL=%u]\n", in arm_smmu_print_context_fault_info()
455 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_context_fault() local
461 arm_smmu_read_context_fault_info(smmu, idx, &cfi); in arm_smmu_context_fault()
470 arm_smmu_print_context_fault_info(smmu, idx, &cfi); in arm_smmu_context_fault()
472 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, cfi.fsr); in arm_smmu_context_fault()
479 struct arm_smmu_device *smmu = dev; in arm_smmu_global_fault() local
483 gfsr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
484 gfsynr0 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); in arm_smmu_global_fault()
485 gfsynr1 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); in arm_smmu_global_fault()
486 gfsynr2 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); in arm_smmu_global_fault()
494 dev_err(smmu->dev, in arm_smmu_global_fault()
495 …"Blocked unknown Stream ID 0x%hx; boot with \"arm-smmu.disable_bypass=0\" to allow, but this may h… in arm_smmu_global_fault()
498 dev_err(smmu->dev, in arm_smmu_global_fault()
500 dev_err(smmu->dev, in arm_smmu_global_fault()
505 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); in arm_smmu_global_fault()
513 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in arm_smmu_init_context_bank()
566 void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_context_bank() argument
570 struct arm_smmu_cb *cb = &smmu->cbs[idx]; in arm_smmu_write_context_bank()
575 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
582 if (smmu->version > ARM_SMMU_V1) { in arm_smmu_write_context_bank()
588 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_write_context_bank()
591 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBA2R(idx), reg); in arm_smmu_write_context_bank()
596 if (smmu->version < ARM_SMMU_V2) in arm_smmu_write_context_bank()
608 } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { in arm_smmu_write_context_bank()
612 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(idx), reg); in arm_smmu_write_context_bank()
619 if (stage1 && smmu->version > ARM_SMMU_V1) in arm_smmu_write_context_bank()
620 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
621 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
625 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_CONTEXTIDR, cfg->asid); in arm_smmu_write_context_bank()
626 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
627 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
629 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
631 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR1, in arm_smmu_write_context_bank()
637 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR0, cb->mair[0]); in arm_smmu_write_context_bank()
638 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR1, cb->mair[1]); in arm_smmu_write_context_bank()
649 if (smmu->impl && smmu->impl->write_sctlr) in arm_smmu_write_context_bank()
650 smmu->impl->write_sctlr(smmu, idx, reg); in arm_smmu_write_context_bank()
652 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
656 struct arm_smmu_device *smmu, in arm_smmu_alloc_context_bank() argument
659 if (smmu->impl && smmu->impl->alloc_context_bank) in arm_smmu_alloc_context_bank()
660 return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_alloc_context_bank()
662 return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); in arm_smmu_alloc_context_bank()
666 struct arm_smmu_device *smmu, in arm_smmu_init_domain_context() argument
679 if (smmu_domain->smmu) in arm_smmu_init_domain_context()
700 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_init_domain_context()
702 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_init_domain_context()
713 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) in arm_smmu_init_domain_context()
717 (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && in arm_smmu_init_domain_context()
721 (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | in arm_smmu_init_domain_context()
734 start = smmu->num_s2_context_banks; in arm_smmu_init_domain_context()
735 ias = smmu->va_size; in arm_smmu_init_domain_context()
736 oas = smmu->ipa_size; in arm_smmu_init_domain_context()
758 ias = smmu->ipa_size; in arm_smmu_init_domain_context()
759 oas = smmu->pa_size; in arm_smmu_init_domain_context()
767 if (smmu->version == ARM_SMMU_V2) in arm_smmu_init_domain_context()
777 ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_init_domain_context()
782 smmu_domain->smmu = smmu; in arm_smmu_init_domain_context()
785 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_init_domain_context()
786 cfg->irptndx = atomic_inc_return(&smmu->irptndx); in arm_smmu_init_domain_context()
787 cfg->irptndx %= smmu->num_context_irqs; in arm_smmu_init_domain_context()
798 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_init_domain_context()
801 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK, in arm_smmu_init_domain_context()
803 .iommu_dev = smmu->dev, in arm_smmu_init_domain_context()
806 if (smmu->impl && smmu->impl->init_context) { in arm_smmu_init_domain_context()
807 ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev); in arm_smmu_init_domain_context()
835 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_init_domain_context()
841 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_init_domain_context()
843 if (smmu->impl && smmu->impl->context_fault) in arm_smmu_init_domain_context()
844 context_fault = smmu->impl->context_fault; in arm_smmu_init_domain_context()
848 if (smmu->impl && smmu->impl->context_fault_needs_threaded_irq) in arm_smmu_init_domain_context()
849 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_init_domain_context()
852 "arm-smmu-context-fault", in arm_smmu_init_domain_context()
855 ret = devm_request_irq(smmu->dev, irq, context_fault, IRQF_SHARED, in arm_smmu_init_domain_context()
856 "arm-smmu-context-fault", smmu_domain); in arm_smmu_init_domain_context()
859 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", in arm_smmu_init_domain_context()
871 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_init_domain_context()
872 smmu_domain->smmu = NULL; in arm_smmu_init_domain_context()
880 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_destroy_domain_context() local
884 if (!smmu) in arm_smmu_destroy_domain_context()
887 ret = arm_smmu_rpm_get(smmu); in arm_smmu_destroy_domain_context()
895 smmu->cbs[cfg->cbndx].cfg = NULL; in arm_smmu_destroy_domain_context()
896 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_destroy_domain_context()
899 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_destroy_domain_context()
900 devm_free_irq(smmu->dev, irq, smmu_domain); in arm_smmu_destroy_domain_context()
904 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_destroy_domain_context()
906 arm_smmu_rpm_put(smmu); in arm_smmu_destroy_domain_context()
940 static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_smr() argument
942 struct arm_smmu_smr *smr = smmu->smrs + idx; in arm_smmu_write_smr()
946 if (!(smmu->features & ARM_SMMU_FEAT_EXIDS) && smr->valid) in arm_smmu_write_smr()
948 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), reg); in arm_smmu_write_smr()
951 static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_s2cr() argument
953 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in arm_smmu_write_s2cr()
956 if (smmu->impl && smmu->impl->write_s2cr) { in arm_smmu_write_s2cr()
957 smmu->impl->write_s2cr(smmu, idx); in arm_smmu_write_s2cr()
965 if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs && in arm_smmu_write_s2cr()
966 smmu->smrs[idx].valid) in arm_smmu_write_s2cr()
968 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in arm_smmu_write_s2cr()
971 static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_sme() argument
973 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_write_sme()
974 if (smmu->smrs) in arm_smmu_write_sme()
975 arm_smmu_write_smr(smmu, idx); in arm_smmu_write_sme()
982 static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) in arm_smmu_test_smr_masks() argument
987 if (!smmu->smrs) in arm_smmu_test_smr_masks()
997 for (i = 0; i < smmu->num_mapping_groups; i++) in arm_smmu_test_smr_masks()
998 if (!smmu->smrs[i].valid) in arm_smmu_test_smr_masks()
1007 smr = FIELD_PREP(ARM_SMMU_SMR_ID, smmu->streamid_mask); in arm_smmu_test_smr_masks()
1008 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
1009 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
1010 smmu->streamid_mask = FIELD_GET(ARM_SMMU_SMR_ID, smr); in arm_smmu_test_smr_masks()
1012 smr = FIELD_PREP(ARM_SMMU_SMR_MASK, smmu->streamid_mask); in arm_smmu_test_smr_masks()
1013 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
1014 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
1015 smmu->smr_mask_mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in arm_smmu_test_smr_masks()
1018 static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) in arm_smmu_find_sme() argument
1020 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_find_sme()
1028 for (i = 0; i < smmu->num_mapping_groups; ++i) { in arm_smmu_find_sme()
1060 static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_free_sme() argument
1062 if (--smmu->s2crs[idx].count) in arm_smmu_free_sme()
1065 smmu->s2crs[idx] = s2cr_init_val; in arm_smmu_free_sme()
1066 if (smmu->smrs) in arm_smmu_free_sme()
1067 smmu->smrs[idx].valid = false; in arm_smmu_free_sme()
1076 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_alloc_smes() local
1077 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_master_alloc_smes()
1080 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1091 ret = arm_smmu_find_sme(smmu, sid, mask); in arm_smmu_master_alloc_smes()
1096 if (smrs && smmu->s2crs[idx].count == 0) { in arm_smmu_master_alloc_smes()
1101 smmu->s2crs[idx].count++; in arm_smmu_master_alloc_smes()
1107 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_alloc_smes()
1109 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1114 arm_smmu_free_sme(smmu, cfg->smendx[i]); in arm_smmu_master_alloc_smes()
1117 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1124 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_free_smes() local
1127 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1129 if (arm_smmu_free_sme(smmu, idx)) in arm_smmu_master_free_smes()
1130 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_free_smes()
1133 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1140 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_install_s2crs() local
1141 struct arm_smmu_s2cr *s2cr = smmu->s2crs; in arm_smmu_master_install_s2crs()
1151 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_master_install_s2crs()
1160 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
1174 smmu = cfg->smmu; in arm_smmu_attach_dev()
1176 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev()
1181 ret = arm_smmu_init_domain_context(smmu_domain, smmu, dev); in arm_smmu_attach_dev()
1189 if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
1197 arm_smmu_rpm_use_autosuspend(smmu); in arm_smmu_attach_dev()
1199 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev()
1208 struct arm_smmu_device *smmu; in arm_smmu_attach_dev_type() local
1213 smmu = cfg->smmu; in arm_smmu_attach_dev_type()
1215 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev_type()
1220 arm_smmu_rpm_use_autosuspend(smmu); in arm_smmu_attach_dev_type()
1221 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev_type()
1260 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_map_pages() local
1266 arm_smmu_rpm_get(smmu); in arm_smmu_map_pages()
1268 arm_smmu_rpm_put(smmu); in arm_smmu_map_pages()
1278 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_unmap_pages() local
1284 arm_smmu_rpm_get(smmu); in arm_smmu_unmap_pages()
1286 arm_smmu_rpm_put(smmu); in arm_smmu_unmap_pages()
1294 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_flush_iotlb_all() local
1297 arm_smmu_rpm_get(smmu); in arm_smmu_flush_iotlb_all()
1299 arm_smmu_rpm_put(smmu); in arm_smmu_flush_iotlb_all()
1307 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iotlb_sync() local
1309 if (!smmu) in arm_smmu_iotlb_sync()
1312 arm_smmu_rpm_get(smmu); in arm_smmu_iotlb_sync()
1313 if (smmu->version == ARM_SMMU_V2 || in arm_smmu_iotlb_sync()
1317 arm_smmu_tlb_sync_global(smmu); in arm_smmu_iotlb_sync()
1318 arm_smmu_rpm_put(smmu); in arm_smmu_iotlb_sync()
1325 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iova_to_phys_hard() local
1328 struct device *dev = smmu->dev; in arm_smmu_iova_to_phys_hard()
1336 ret = arm_smmu_rpm_get(smmu); in arm_smmu_iova_to_phys_hard()
1343 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1345 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1347 reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR; in arm_smmu_iova_to_phys_hard()
1354 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1358 phys = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_PAR); in arm_smmu_iova_to_phys_hard()
1368 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1382 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && in arm_smmu_iova_to_phys()
1401 return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK || in arm_smmu_capable()
1422 struct arm_smmu_device *smmu = NULL; in arm_smmu_probe_device() local
1428 ret = arm_smmu_register_legacy_master(dev, &smmu); in arm_smmu_probe_device()
1439 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
1447 if (sid & ~smmu->streamid_mask) { in arm_smmu_probe_device()
1448 dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1449 sid, smmu->streamid_mask); in arm_smmu_probe_device()
1452 if (mask & ~smmu->smr_mask_mask) { in arm_smmu_probe_device()
1453 dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1454 mask, smmu->smr_mask_mask); in arm_smmu_probe_device()
1465 cfg->smmu = smmu; in arm_smmu_probe_device()
1470 ret = arm_smmu_rpm_get(smmu); in arm_smmu_probe_device()
1475 arm_smmu_rpm_put(smmu); in arm_smmu_probe_device()
1480 device_link_add(dev, smmu->dev, in arm_smmu_probe_device()
1483 return &smmu->iommu; in arm_smmu_probe_device()
1498 ret = arm_smmu_rpm_get(cfg->smmu); in arm_smmu_release_device()
1504 arm_smmu_rpm_put(cfg->smmu); in arm_smmu_release_device()
1512 struct arm_smmu_device *smmu; in arm_smmu_probe_finalize() local
1515 smmu = cfg->smmu; in arm_smmu_probe_finalize()
1517 if (smmu->impl && smmu->impl->probe_finalize) in arm_smmu_probe_finalize()
1518 smmu->impl->probe_finalize(smmu, dev); in arm_smmu_probe_finalize()
1525 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_device_group() local
1529 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1531 if (group && smmu->s2crs[idx].group && in arm_smmu_device_group()
1532 group != smmu->s2crs[idx].group) { in arm_smmu_device_group()
1533 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1537 group = smmu->s2crs[idx].group; in arm_smmu_device_group()
1541 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1555 smmu->s2crs[idx].group = group; in arm_smmu_device_group()
1557 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1567 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
1583 if (smmu_domain->smmu) in arm_smmu_set_pgtable_quirks()
1627 const struct arm_smmu_impl *impl = cfg->smmu->impl; in arm_smmu_def_domain_type()
1665 static void arm_smmu_device_reset(struct arm_smmu_device *smmu) in arm_smmu_device_reset() argument
1671 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_device_reset()
1672 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); in arm_smmu_device_reset()
1678 for (i = 0; i < smmu->num_mapping_groups; ++i) in arm_smmu_device_reset()
1679 arm_smmu_write_sme(smmu, i); in arm_smmu_device_reset()
1682 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_smmu_device_reset()
1683 arm_smmu_write_context_bank(smmu, i); in arm_smmu_device_reset()
1684 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_CB_FSR_FAULT); in arm_smmu_device_reset()
1688 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1689 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLNSNH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1691 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_device_reset()
1713 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_device_reset()
1716 if (smmu->features & ARM_SMMU_FEAT_EXIDS) in arm_smmu_device_reset()
1719 if (smmu->impl && smmu->impl->reset) in arm_smmu_device_reset()
1720 smmu->impl->reset(smmu); in arm_smmu_device_reset()
1723 arm_smmu_tlb_sync_global(smmu); in arm_smmu_device_reset()
1724 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_device_reset()
1746 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) in arm_smmu_device_cfg_probe() argument
1750 bool cttw_reg, cttw_fw = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_cfg_probe()
1753 dev_notice(smmu->dev, "probing hardware configuration...\n"); in arm_smmu_device_cfg_probe()
1754 dev_notice(smmu->dev, "SMMUv%d with:\n", in arm_smmu_device_cfg_probe()
1755 smmu->version == ARM_SMMU_V2 ? 2 : 1); in arm_smmu_device_cfg_probe()
1758 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID0); in arm_smmu_device_cfg_probe()
1767 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_cfg_probe()
1768 dev_notice(smmu->dev, "\tstage 1 translation\n"); in arm_smmu_device_cfg_probe()
1772 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_cfg_probe()
1773 dev_notice(smmu->dev, "\tstage 2 translation\n"); in arm_smmu_device_cfg_probe()
1777 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; in arm_smmu_device_cfg_probe()
1778 dev_notice(smmu->dev, "\tnested translation\n"); in arm_smmu_device_cfg_probe()
1781 if (!(smmu->features & in arm_smmu_device_cfg_probe()
1783 dev_err(smmu->dev, "\tno translation support!\n"); in arm_smmu_device_cfg_probe()
1788 ((smmu->version < ARM_SMMU_V2) || !(id & ARM_SMMU_ID0_ATOSNS))) { in arm_smmu_device_cfg_probe()
1789 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; in arm_smmu_device_cfg_probe()
1790 dev_notice(smmu->dev, "\taddress translation ops\n"); in arm_smmu_device_cfg_probe()
1801 dev_notice(smmu->dev, "\t%scoherent table walk\n", in arm_smmu_device_cfg_probe()
1804 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1808 if (smmu->version == ARM_SMMU_V2 && id & ARM_SMMU_ID0_EXIDS) { in arm_smmu_device_cfg_probe()
1809 smmu->features |= ARM_SMMU_FEAT_EXIDS; in arm_smmu_device_cfg_probe()
1814 smmu->streamid_mask = size - 1; in arm_smmu_device_cfg_probe()
1816 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; in arm_smmu_device_cfg_probe()
1819 dev_err(smmu->dev, in arm_smmu_device_cfg_probe()
1825 smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs), in arm_smmu_device_cfg_probe()
1827 if (!smmu->smrs) in arm_smmu_device_cfg_probe()
1830 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1834 smmu->s2crs = devm_kmalloc_array(smmu->dev, size, sizeof(*smmu->s2crs), in arm_smmu_device_cfg_probe()
1836 if (!smmu->s2crs) in arm_smmu_device_cfg_probe()
1839 smmu->s2crs[i] = s2cr_init_val; in arm_smmu_device_cfg_probe()
1841 smmu->num_mapping_groups = size; in arm_smmu_device_cfg_probe()
1842 mutex_init(&smmu->stream_map_mutex); in arm_smmu_device_cfg_probe()
1843 spin_lock_init(&smmu->global_sync_lock); in arm_smmu_device_cfg_probe()
1845 if (smmu->version < ARM_SMMU_V2 || in arm_smmu_device_cfg_probe()
1847 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L; in arm_smmu_device_cfg_probe()
1849 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S; in arm_smmu_device_cfg_probe()
1853 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID1); in arm_smmu_device_cfg_probe()
1854 smmu->pgshift = (id & ARM_SMMU_ID1_PAGESIZE) ? 16 : 12; in arm_smmu_device_cfg_probe()
1856 /* Check for size mismatch of SMMU address space from mapped region */ in arm_smmu_device_cfg_probe()
1858 if (smmu->numpage != 2 * size << smmu->pgshift) in arm_smmu_device_cfg_probe()
1859 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1860 "SMMU address space size (0x%x) differs from mapped region size (0x%x)!\n", in arm_smmu_device_cfg_probe()
1861 2 * size << smmu->pgshift, smmu->numpage); in arm_smmu_device_cfg_probe()
1863 smmu->numpage = size; in arm_smmu_device_cfg_probe()
1865 smmu->num_s2_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMS2CB, id); in arm_smmu_device_cfg_probe()
1866 smmu->num_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMCB, id); in arm_smmu_device_cfg_probe()
1867 if (smmu->num_s2_context_banks > smmu->num_context_banks) { in arm_smmu_device_cfg_probe()
1868 dev_err(smmu->dev, "impossible number of S2 context banks!\n"); in arm_smmu_device_cfg_probe()
1871 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", in arm_smmu_device_cfg_probe()
1872 smmu->num_context_banks, smmu->num_s2_context_banks); in arm_smmu_device_cfg_probe()
1873 smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks, in arm_smmu_device_cfg_probe()
1874 sizeof(*smmu->cbs), GFP_KERNEL); in arm_smmu_device_cfg_probe()
1875 if (!smmu->cbs) in arm_smmu_device_cfg_probe()
1879 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID2); in arm_smmu_device_cfg_probe()
1881 smmu->ipa_size = size; in arm_smmu_device_cfg_probe()
1885 smmu->pa_size = size; in arm_smmu_device_cfg_probe()
1888 smmu->features |= ARM_SMMU_FEAT_VMID16; in arm_smmu_device_cfg_probe()
1895 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size))) in arm_smmu_device_cfg_probe()
1896 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1899 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_device_cfg_probe()
1900 smmu->va_size = smmu->ipa_size; in arm_smmu_device_cfg_probe()
1901 if (smmu->version == ARM_SMMU_V1_64K) in arm_smmu_device_cfg_probe()
1902 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1905 smmu->va_size = arm_smmu_id_size_to_bits(size); in arm_smmu_device_cfg_probe()
1907 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K; in arm_smmu_device_cfg_probe()
1909 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K; in arm_smmu_device_cfg_probe()
1911 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1914 if (smmu->impl && smmu->impl->cfg_probe) { in arm_smmu_device_cfg_probe()
1915 ret = smmu->impl->cfg_probe(smmu); in arm_smmu_device_cfg_probe()
1921 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) in arm_smmu_device_cfg_probe()
1922 smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; in arm_smmu_device_cfg_probe()
1923 if (smmu->features & in arm_smmu_device_cfg_probe()
1925 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_cfg_probe()
1926 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K) in arm_smmu_device_cfg_probe()
1927 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_cfg_probe()
1928 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K) in arm_smmu_device_cfg_probe()
1929 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_cfg_probe()
1932 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1934 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1935 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", in arm_smmu_device_cfg_probe()
1936 smmu->pgsize_bitmap); in arm_smmu_device_cfg_probe()
1939 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) in arm_smmu_device_cfg_probe()
1940 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", in arm_smmu_device_cfg_probe()
1941 smmu->va_size, smmu->ipa_size); in arm_smmu_device_cfg_probe()
1943 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) in arm_smmu_device_cfg_probe()
1944 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", in arm_smmu_device_cfg_probe()
1945 smmu->ipa_size, smmu->pa_size); in arm_smmu_device_cfg_probe()
1966 { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
1967 { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
1971 { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
1972 { .compatible = "nvidia,smmu-500", .data = &arm_mmu500 },
1973 { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
1979 static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_data() argument
1986 smmu->version = ARM_SMMU_V1; in acpi_smmu_get_data()
1987 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1990 smmu->version = ARM_SMMU_V1_64K; in acpi_smmu_get_data()
1991 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1994 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1995 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1998 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1999 smmu->model = ARM_MMU500; in acpi_smmu_get_data()
2002 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
2003 smmu->model = CAVIUM_SMMUV2; in acpi_smmu_get_data()
2012 static int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
2015 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
2024 ret = acpi_smmu_get_data(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
2033 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_acpi_probe()
2038 static inline int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
2045 static int arm_smmu_device_dt_probe(struct arm_smmu_device *smmu, in arm_smmu_device_dt_probe() argument
2049 struct device *dev = smmu->dev; in arm_smmu_device_dt_probe()
2058 smmu->version = data->version; in arm_smmu_device_dt_probe()
2059 smmu->model = data->model; in arm_smmu_device_dt_probe()
2065 IS_ENABLED(CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS) ? "DMA API" : "SMMU"); in arm_smmu_device_dt_probe()
2076 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_dt_probe()
2081 static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu) in arm_smmu_rmr_install_bypass_smr() argument
2089 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2095 * SMMU until it gets enabled again in the reset routine. in arm_smmu_rmr_install_bypass_smr()
2097 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_rmr_install_bypass_smr()
2099 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_rmr_install_bypass_smr()
2107 idx = arm_smmu_find_sme(smmu, rmr->sids[i], ~0); in arm_smmu_rmr_install_bypass_smr()
2111 if (smmu->s2crs[idx].count == 0) { in arm_smmu_rmr_install_bypass_smr()
2112 smmu->smrs[idx].id = rmr->sids[i]; in arm_smmu_rmr_install_bypass_smr()
2113 smmu->smrs[idx].mask = 0; in arm_smmu_rmr_install_bypass_smr()
2114 smmu->smrs[idx].valid = true; in arm_smmu_rmr_install_bypass_smr()
2116 smmu->s2crs[idx].count++; in arm_smmu_rmr_install_bypass_smr()
2117 smmu->s2crs[idx].type = S2CR_TYPE_BYPASS; in arm_smmu_rmr_install_bypass_smr()
2118 smmu->s2crs[idx].privcfg = S2CR_PRIVCFG_DEFAULT; in arm_smmu_rmr_install_bypass_smr()
2124 dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt, in arm_smmu_rmr_install_bypass_smr()
2126 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2132 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
2138 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
2139 if (!smmu) { in arm_smmu_device_probe()
2143 smmu->dev = dev; in arm_smmu_device_probe()
2146 err = arm_smmu_device_dt_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2148 err = arm_smmu_device_acpi_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2152 smmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in arm_smmu_device_probe()
2153 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
2154 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
2155 smmu->ioaddr = res->start; in arm_smmu_device_probe()
2161 smmu->numpage = resource_size(res); in arm_smmu_device_probe()
2163 smmu = arm_smmu_impl_init(smmu); in arm_smmu_device_probe()
2164 if (IS_ERR(smmu)) in arm_smmu_device_probe()
2165 return PTR_ERR(smmu); in arm_smmu_device_probe()
2169 smmu->num_context_irqs = num_irqs - global_irqs - pmu_irqs; in arm_smmu_device_probe()
2170 if (smmu->num_context_irqs <= 0) in arm_smmu_device_probe()
2175 smmu->irqs = devm_kcalloc(dev, smmu->num_context_irqs, in arm_smmu_device_probe()
2176 sizeof(*smmu->irqs), GFP_KERNEL); in arm_smmu_device_probe()
2177 if (!smmu->irqs) in arm_smmu_device_probe()
2179 smmu->num_context_irqs); in arm_smmu_device_probe()
2181 for (i = 0; i < smmu->num_context_irqs; i++) { in arm_smmu_device_probe()
2186 smmu->irqs[i] = irq; in arm_smmu_device_probe()
2189 err = devm_clk_bulk_get_all(dev, &smmu->clks); in arm_smmu_device_probe()
2194 smmu->num_clks = err; in arm_smmu_device_probe()
2196 err = clk_bulk_prepare_enable(smmu->num_clks, smmu->clks); in arm_smmu_device_probe()
2200 err = arm_smmu_device_cfg_probe(smmu); in arm_smmu_device_probe()
2204 if (smmu->version == ARM_SMMU_V2) { in arm_smmu_device_probe()
2205 if (smmu->num_context_banks > smmu->num_context_irqs) { in arm_smmu_device_probe()
2208 smmu->num_context_irqs, smmu->num_context_banks); in arm_smmu_device_probe()
2213 smmu->num_context_irqs = smmu->num_context_banks; in arm_smmu_device_probe()
2216 if (smmu->impl && smmu->impl->global_fault) in arm_smmu_device_probe()
2217 global_fault = smmu->impl->global_fault; in arm_smmu_device_probe()
2228 "arm-smmu global fault", smmu); in arm_smmu_device_probe()
2235 err = iommu_device_sysfs_add(&smmu->iommu, smmu->dev, NULL, in arm_smmu_device_probe()
2236 "smmu.%pa", &smmu->ioaddr); in arm_smmu_device_probe()
2242 err = iommu_device_register(&smmu->iommu, &arm_smmu_ops, in arm_smmu_device_probe()
2246 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
2250 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
2253 arm_smmu_rmr_install_bypass_smr(smmu); in arm_smmu_device_probe()
2255 arm_smmu_device_reset(smmu); in arm_smmu_device_probe()
2256 arm_smmu_test_smr_masks(smmu); in arm_smmu_device_probe()
2274 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_shutdown() local
2276 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) in arm_smmu_device_shutdown()
2279 arm_smmu_rpm_get(smmu); in arm_smmu_device_shutdown()
2281 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, ARM_SMMU_sCR0_CLIENTPD); in arm_smmu_device_shutdown()
2282 arm_smmu_rpm_put(smmu); in arm_smmu_device_shutdown()
2284 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_device_shutdown()
2285 pm_runtime_force_suspend(smmu->dev); in arm_smmu_device_shutdown()
2287 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2289 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2294 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
2296 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
2297 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
2304 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_resume() local
2307 ret = clk_bulk_enable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_resume()
2311 arm_smmu_device_reset(smmu); in arm_smmu_runtime_resume()
2318 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_suspend() local
2320 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_suspend()
2328 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_resume() local
2330 ret = clk_bulk_prepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2339 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2347 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_suspend() local
2357 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_suspend()
2369 .name = "arm-smmu",
2380 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2382 MODULE_ALIAS("platform:arm-smmu");