Lines Matching full:smmu
32 #include "arm-smmu-v3.h"
87 struct arm_smmu_device *smmu, u32 flags);
90 static void parse_driver_options(struct arm_smmu_device *smmu) in parse_driver_options() argument
95 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
97 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
98 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
193 static void queue_poll_init(struct arm_smmu_device *smmu, in queue_poll_init() argument
198 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
349 static struct arm_smmu_cmdq *arm_smmu_get_cmdq(struct arm_smmu_device *smmu, in arm_smmu_get_cmdq() argument
354 if (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq) in arm_smmu_get_cmdq()
355 cmdq = smmu->impl_ops->get_secondary_cmdq(smmu, ent); in arm_smmu_get_cmdq()
357 return cmdq ?: &smmu->cmdq; in arm_smmu_get_cmdq()
360 static bool arm_smmu_cmdq_needs_busy_polling(struct arm_smmu_device *smmu, in arm_smmu_cmdq_needs_busy_polling() argument
363 if (cmdq == &smmu->cmdq) in arm_smmu_cmdq_needs_busy_polling()
366 return smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV; in arm_smmu_cmdq_needs_busy_polling()
369 static void arm_smmu_cmdq_build_sync_cmd(u64 *cmd, struct arm_smmu_device *smmu, in arm_smmu_cmdq_build_sync_cmd() argument
381 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { in arm_smmu_cmdq_build_sync_cmd()
387 if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) in arm_smmu_cmdq_build_sync_cmd()
391 void __arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_skip_err() argument
410 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, in __arm_smmu_cmdq_skip_err()
415 dev_err(smmu->dev, "retrying command fetch\n"); in __arm_smmu_cmdq_skip_err()
437 dev_err(smmu->dev, "skipping command in error state:\n"); in __arm_smmu_cmdq_skip_err()
439 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
443 if (arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) in __arm_smmu_cmdq_skip_err()
449 static void arm_smmu_cmdq_skip_err(struct arm_smmu_device *smmu) in arm_smmu_cmdq_skip_err() argument
451 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); in arm_smmu_cmdq_skip_err()
545 * a. If we have MSIs, the SMMU can write back into the CMD_SYNC
615 static int arm_smmu_cmdq_poll_until_not_full(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_not_full() argument
634 queue_poll_init(smmu, &qp); in arm_smmu_cmdq_poll_until_not_full()
647 * Wait until the SMMU signals a CMD_SYNC completion MSI.
650 static int __arm_smmu_cmdq_poll_until_msi(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_msi() argument
658 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_msi()
671 * Wait until the SMMU cons index passes llq->prod.
674 static int __arm_smmu_cmdq_poll_until_consumed(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_poll_until_consumed() argument
682 queue_poll_init(smmu, &qp); in __arm_smmu_cmdq_poll_until_consumed()
724 static int arm_smmu_cmdq_poll_until_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_poll_until_sync() argument
728 if (smmu->options & ARM_SMMU_OPT_MSIPOLL && in arm_smmu_cmdq_poll_until_sync()
729 !arm_smmu_cmdq_needs_busy_polling(smmu, cmdq)) in arm_smmu_cmdq_poll_until_sync()
730 return __arm_smmu_cmdq_poll_until_msi(smmu, cmdq, llq); in arm_smmu_cmdq_poll_until_sync()
732 return __arm_smmu_cmdq_poll_until_consumed(smmu, cmdq, llq); in arm_smmu_cmdq_poll_until_sync()
768 static int arm_smmu_cmdq_issue_cmdlist(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmdlist() argument
789 if (arm_smmu_cmdq_poll_until_not_full(smmu, cmdq, &llq)) in arm_smmu_cmdq_issue_cmdlist()
790 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); in arm_smmu_cmdq_issue_cmdlist()
815 arm_smmu_cmdq_build_sync_cmd(cmd_sync, smmu, cmdq, prod); in arm_smmu_cmdq_issue_cmdlist()
831 /* 4. If we are the owner, take control of the SMMU hardware */ in arm_smmu_cmdq_issue_cmdlist()
865 ret = arm_smmu_cmdq_poll_until_sync(smmu, cmdq, &llq); in arm_smmu_cmdq_issue_cmdlist()
867 dev_err_ratelimited(smmu->dev, in arm_smmu_cmdq_issue_cmdlist()
888 static int __arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in __arm_smmu_cmdq_issue_cmd() argument
895 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in __arm_smmu_cmdq_issue_cmd()
901 smmu, arm_smmu_get_cmdq(smmu, ent), cmd, 1, sync); in __arm_smmu_cmdq_issue_cmd()
904 static int arm_smmu_cmdq_issue_cmd(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd() argument
907 return __arm_smmu_cmdq_issue_cmd(smmu, ent, false); in arm_smmu_cmdq_issue_cmd()
910 static int arm_smmu_cmdq_issue_cmd_with_sync(struct arm_smmu_device *smmu, in arm_smmu_cmdq_issue_cmd_with_sync() argument
913 return __arm_smmu_cmdq_issue_cmd(smmu, ent, true); in arm_smmu_cmdq_issue_cmd_with_sync()
916 static void arm_smmu_cmdq_batch_init(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_init() argument
921 cmds->cmdq = arm_smmu_get_cmdq(smmu, ent); in arm_smmu_cmdq_batch_init()
924 static void arm_smmu_cmdq_batch_add(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_add() argument
930 (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC); in arm_smmu_cmdq_batch_add()
934 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_add()
936 arm_smmu_cmdq_batch_init(smmu, cmds, cmd); in arm_smmu_cmdq_batch_add()
940 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_add()
942 arm_smmu_cmdq_batch_init(smmu, cmds, cmd); in arm_smmu_cmdq_batch_add()
947 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in arm_smmu_cmdq_batch_add()
955 static int arm_smmu_cmdq_batch_submit(struct arm_smmu_device *smmu, in arm_smmu_cmdq_batch_submit() argument
958 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_submit()
987 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
997 void arm_smmu_tlb_inv_asid(struct arm_smmu_device *smmu, u16 asid) in arm_smmu_tlb_inv_asid() argument
1000 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_asid()
1005 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_asid()
1202 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_sync_cd() local
1211 arm_smmu_cmdq_batch_init(smmu, &cmds, &cmd); in arm_smmu_sync_cd()
1214 arm_smmu_cmdq_batch_add(smmu, &cmds, &cmd); in arm_smmu_sync_cd()
1217 arm_smmu_cmdq_batch_submit(smmu, &cmds); in arm_smmu_sync_cd()
1256 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_alloc_cd_ptr() local
1273 *l2ptr = dma_alloc_coherent(smmu->dev, sizeof(**l2ptr), in arm_smmu_alloc_cd_ptr()
1412 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_alloc_cd_tables() local
1418 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || in arm_smmu_alloc_cd_tables()
1424 cd_table->linear.table = dma_alloc_coherent(smmu->dev, l1size, in arm_smmu_alloc_cd_tables()
1441 cd_table->l2.l1tab = dma_alloc_coherent(smmu->dev, l1size, in arm_smmu_alloc_cd_tables()
1460 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_free_cd_tables() local
1468 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1475 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1480 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1517 arm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd); in arm_smmu_ste_writer_sync_entry()
1529 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_write_ste() local
1541 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) { in arm_smmu_write_ste()
1548 arm_smmu_cmdq_issue_cmd(smmu, &prefetch_cmd); in arm_smmu_write_ste()
1563 void arm_smmu_make_bypass_ste(struct arm_smmu_device *smmu, in arm_smmu_make_bypass_ste() argument
1571 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) in arm_smmu_make_bypass_ste()
1583 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_make_cdtable_ste() local
1598 ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_make_cdtable_ste()
1605 if ((smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) && in arm_smmu_make_cdtable_ste()
1610 if (smmu->features & ARM_SMMU_FEAT_E2H) { in arm_smmu_make_cdtable_ste()
1647 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_make_s2_domain_ste() local
1658 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) in arm_smmu_make_s2_domain_ste()
1687 * because the STE table has not been installed in the SMMU yet.
1700 static int arm_smmu_init_l2_strtab(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_init_l2_strtab() argument
1703 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l2_strtab()
1710 *l2table = dmam_alloc_coherent(smmu->dev, sizeof(**l2table), in arm_smmu_init_l2_strtab()
1713 dev_err(smmu->dev, in arm_smmu_init_l2_strtab()
1747 arm_smmu_find_master(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_find_master() argument
1751 lockdep_assert_held(&smmu->streams_mutex); in arm_smmu_find_master()
1753 node = rb_find(&sid, &smmu->streams, arm_smmu_streams_cmp_key); in arm_smmu_find_master()
1760 static int arm_smmu_handle_evt(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_evt() argument
1807 mutex_lock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1808 master = arm_smmu_find_master(smmu, sid); in arm_smmu_handle_evt()
1816 mutex_unlock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1823 struct arm_smmu_device *smmu = dev; in arm_smmu_evtq_thread() local
1824 struct arm_smmu_queue *q = &smmu->evtq.q; in arm_smmu_evtq_thread()
1834 ret = arm_smmu_handle_evt(smmu, evt); in arm_smmu_evtq_thread()
1838 dev_info(smmu->dev, "event 0x%02x received:\n", id); in arm_smmu_evtq_thread()
1840 dev_info(smmu->dev, "\t0x%016llx\n", in arm_smmu_evtq_thread()
1851 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); in arm_smmu_evtq_thread()
1859 static void arm_smmu_handle_ppr(struct arm_smmu_device *smmu, u64 *evt) in arm_smmu_handle_ppr() argument
1871 dev_info(smmu->dev, "unexpected PRI request received:\n"); in arm_smmu_handle_ppr()
1872 dev_info(smmu->dev, in arm_smmu_handle_ppr()
1893 arm_smmu_cmdq_issue_cmd(smmu, &cmd); in arm_smmu_handle_ppr()
1899 struct arm_smmu_device *smmu = dev; in arm_smmu_priq_thread() local
1900 struct arm_smmu_queue *q = &smmu->priq.q; in arm_smmu_priq_thread()
1906 arm_smmu_handle_ppr(smmu, evt); in arm_smmu_priq_thread()
1909 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); in arm_smmu_priq_thread()
1917 static int arm_smmu_device_disable(struct arm_smmu_device *smmu);
1922 struct arm_smmu_device *smmu = dev; in arm_smmu_gerror_handler() local
1924 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); in arm_smmu_gerror_handler()
1925 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1931 dev_warn(smmu->dev, in arm_smmu_gerror_handler()
1936 dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); in arm_smmu_gerror_handler()
1937 arm_smmu_device_disable(smmu); in arm_smmu_gerror_handler()
1941 dev_warn(smmu->dev, "GERROR MSI write aborted\n"); in arm_smmu_gerror_handler()
1944 dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1947 dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1950 dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1953 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1956 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1959 arm_smmu_cmdq_skip_err(smmu); in arm_smmu_gerror_handler()
1961 writel(gerror, smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1967 struct arm_smmu_device *smmu = dev; in arm_smmu_combined_irq_thread() local
1970 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_combined_irq_thread()
2058 arm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
2061 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
2064 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); in arm_smmu_atc_inv_master()
2078 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_atc_inv_domain()
2098 arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
2112 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
2117 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); in arm_smmu_atc_inv_domain()
2124 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context() local
2130 * to the SMMU. We are relying on the dma_wmb() implicit during cmd in arm_smmu_tlb_inv_context()
2135 arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); in arm_smmu_tlb_inv_context()
2139 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_tlb_inv_context()
2149 struct arm_smmu_device *smmu = smmu_domain->smmu; in __arm_smmu_tlb_inv_range() local
2157 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
2180 arm_smmu_cmdq_batch_init(smmu, &cmds, cmd); in __arm_smmu_tlb_inv_range()
2183 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
2209 arm_smmu_cmdq_batch_add(smmu, &cmds, cmd); in __arm_smmu_tlb_inv_range()
2212 arm_smmu_cmdq_batch_submit(smmu, &cmds); in __arm_smmu_tlb_inv_range()
2226 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
2247 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_asid()
2280 static bool arm_smmu_dbm_capable(struct arm_smmu_device *smmu) in arm_smmu_dbm_capable() argument
2284 return (smmu->features & features) == features; in arm_smmu_dbm_capable()
2295 return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_capable()
2300 return arm_smmu_dbm_capable(master->smmu); in arm_smmu_capable()
2338 ret = arm_smmu_domain_finalise(smmu_domain, master->smmu, 0); in arm_smmu_domain_alloc_paging()
2350 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_free_paging() local
2363 ida_free(&smmu->vmid_map, cfg->vmid); in arm_smmu_domain_free_paging()
2369 static int arm_smmu_domain_finalise_s1(struct arm_smmu_device *smmu, in arm_smmu_domain_finalise_s1() argument
2379 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_domain_finalise_s1()
2385 static int arm_smmu_domain_finalise_s2(struct arm_smmu_device *smmu, in arm_smmu_domain_finalise_s2() argument
2392 vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, in arm_smmu_domain_finalise_s2()
2402 struct arm_smmu_device *smmu, u32 flags) in arm_smmu_domain_finalise() argument
2408 int (*finalise_stage_fn)(struct arm_smmu_device *smmu, in arm_smmu_domain_finalise()
2413 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_domain_finalise()
2415 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_domain_finalise()
2419 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_domain_finalise()
2420 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, in arm_smmu_domain_finalise()
2422 .iommu_dev = smmu->dev, in arm_smmu_domain_finalise()
2427 unsigned long ias = (smmu->features & in arm_smmu_domain_finalise()
2431 pgtbl_cfg.oas = smmu->ias; in arm_smmu_domain_finalise()
2441 pgtbl_cfg.ias = smmu->ias; in arm_smmu_domain_finalise()
2442 pgtbl_cfg.oas = smmu->oas; in arm_smmu_domain_finalise()
2460 ret = finalise_stage_fn(smmu, smmu_domain); in arm_smmu_domain_finalise()
2467 smmu_domain->smmu = smmu; in arm_smmu_domain_finalise()
2472 arm_smmu_get_step_for_sid(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_get_step_for_sid() argument
2474 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_get_step_for_sid()
2476 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_get_step_for_sid()
2490 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_install_ste_for_dev() local
2502 arm_smmu_get_step_for_sid(smmu, sid); in arm_smmu_install_ste_for_dev()
2518 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_ats_supported() local
2521 if (!(smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_ats_supported()
2534 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_enable_ats() local
2537 stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_enable_ats()
2575 master->smmu->ssid_bits); in arm_smmu_enable_pasid()
2700 * The SMMU does not support enabling ATS with bypass/abort. in arm_smmu_attach_prepare()
2768 * SMMU is translating for the new domain and both the old&new in arm_smmu_attach_commit()
2786 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
2799 smmu = master->smmu; in arm_smmu_attach_dev()
2803 if (!smmu_domain->smmu) { in arm_smmu_attach_dev()
2804 ret = arm_smmu_domain_finalise(smmu_domain, smmu, 0); in arm_smmu_attach_dev()
2805 } else if (smmu_domain->smmu != smmu) in arm_smmu_attach_dev()
2863 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_s1_set_dev_pasid() local
2868 if (!smmu_domain->smmu) in arm_smmu_s1_set_dev_pasid()
2869 ret = arm_smmu_domain_finalise(smmu_domain, smmu, 0); in arm_smmu_s1_set_dev_pasid()
2870 else if (smmu_domain->smmu != smmu) in arm_smmu_s1_set_dev_pasid()
2931 if (smmu_domain->smmu != master->smmu) in arm_smmu_set_pasid()
3047 arm_smmu_make_bypass_ste(master->smmu, &ste); in arm_smmu_attach_dev_identity()
3102 ret = arm_smmu_domain_finalise(smmu_domain, master->smmu, flags); in arm_smmu_domain_alloc_user()
3141 if (smmu_domain->smmu) in arm_smmu_flush_iotlb_all()
3180 static bool arm_smmu_sid_in_range(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_sid_in_range() argument
3182 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_sid_in_range()
3183 return arm_smmu_strtab_l1_idx(sid) < smmu->strtab_cfg.l2.num_l1_ents; in arm_smmu_sid_in_range()
3184 return sid < smmu->strtab_cfg.linear.num_ents; in arm_smmu_sid_in_range()
3187 static int arm_smmu_init_sid_strtab(struct arm_smmu_device *smmu, u32 sid) in arm_smmu_init_sid_strtab() argument
3189 /* Check the SIDs are in range of the SMMU and our stream table */ in arm_smmu_init_sid_strtab()
3190 if (!arm_smmu_sid_in_range(smmu, sid)) in arm_smmu_init_sid_strtab()
3194 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_sid_strtab()
3195 return arm_smmu_init_l2_strtab(smmu, sid); in arm_smmu_init_sid_strtab()
3200 static int arm_smmu_insert_master(struct arm_smmu_device *smmu, in arm_smmu_insert_master() argument
3213 mutex_lock(&smmu->streams_mutex); in arm_smmu_insert_master()
3221 ret = arm_smmu_init_sid_strtab(smmu, sid); in arm_smmu_insert_master()
3226 if (rb_find_add(&new_stream->node, &smmu->streams, in arm_smmu_insert_master()
3237 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_insert_master()
3240 mutex_unlock(&smmu->streams_mutex); in arm_smmu_insert_master()
3248 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_remove_master() local
3251 if (!smmu || !master->streams) in arm_smmu_remove_master()
3254 mutex_lock(&smmu->streams_mutex); in arm_smmu_remove_master()
3256 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_remove_master()
3257 mutex_unlock(&smmu->streams_mutex); in arm_smmu_remove_master()
3265 struct arm_smmu_device *smmu; in arm_smmu_probe_device() local
3272 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
3273 if (!smmu) in arm_smmu_probe_device()
3281 master->smmu = smmu; in arm_smmu_probe_device()
3284 ret = arm_smmu_insert_master(smmu, master); in arm_smmu_probe_device()
3289 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); in arm_smmu_probe_device()
3301 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) in arm_smmu_probe_device()
3305 if ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_probe_device()
3307 smmu->features & ARM_SMMU_FEAT_STALL_FORCE) in arm_smmu_probe_device()
3311 unsigned int stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_probe_device()
3316 return &smmu->iommu; in arm_smmu_probe_device()
3328 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); in arm_smmu_release_device()
3387 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
3528 int arm_smmu_init_one_queue(struct arm_smmu_device *smmu, in arm_smmu_init_one_queue() argument
3537 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue()
3546 dev_err(smmu->dev, in arm_smmu_init_one_queue()
3553 dev_info(smmu->dev, "allocated %u entries for %s\n", in arm_smmu_init_one_queue()
3569 int arm_smmu_cmdq_init(struct arm_smmu_device *smmu, in arm_smmu_cmdq_init() argument
3577 cmdq->valid_map = (atomic_long_t *)devm_bitmap_zalloc(smmu->dev, nents, in arm_smmu_cmdq_init()
3585 static int arm_smmu_init_queues(struct arm_smmu_device *smmu) in arm_smmu_init_queues() argument
3590 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, in arm_smmu_init_queues()
3596 ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq); in arm_smmu_init_queues()
3601 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, in arm_smmu_init_queues()
3607 if ((smmu->features & ARM_SMMU_FEAT_SVA) && in arm_smmu_init_queues()
3608 (smmu->features & ARM_SMMU_FEAT_STALLS)) { in arm_smmu_init_queues()
3609 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); in arm_smmu_init_queues()
3610 if (!smmu->evtq.iopf) in arm_smmu_init_queues()
3615 if (!(smmu->features & ARM_SMMU_FEAT_PRI)) in arm_smmu_init_queues()
3618 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, in arm_smmu_init_queues()
3623 static int arm_smmu_init_strtab_2lvl(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_2lvl() argument
3626 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_2lvl()
3628 arm_smmu_strtab_l1_idx((1ULL << smmu->sid_bits) - 1); in arm_smmu_init_strtab_2lvl()
3633 dev_warn(smmu->dev, in arm_smmu_init_strtab_2lvl()
3636 smmu->sid_bits); in arm_smmu_init_strtab_2lvl()
3639 cfg->l2.l1tab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->l2.l1_dma, in arm_smmu_init_strtab_2lvl()
3642 dev_err(smmu->dev, in arm_smmu_init_strtab_2lvl()
3648 cfg->l2.l2ptrs = devm_kcalloc(smmu->dev, cfg->l2.num_l1_ents, in arm_smmu_init_strtab_2lvl()
3656 static int arm_smmu_init_strtab_linear(struct arm_smmu_device *smmu) in arm_smmu_init_strtab_linear() argument
3659 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_linear()
3661 size = (1 << smmu->sid_bits) * sizeof(struct arm_smmu_ste); in arm_smmu_init_strtab_linear()
3662 cfg->linear.table = dmam_alloc_coherent(smmu->dev, size, in arm_smmu_init_strtab_linear()
3666 dev_err(smmu->dev, in arm_smmu_init_strtab_linear()
3671 cfg->linear.num_ents = 1 << smmu->sid_bits; in arm_smmu_init_strtab_linear()
3677 static int arm_smmu_init_strtab(struct arm_smmu_device *smmu) in arm_smmu_init_strtab() argument
3681 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_strtab()
3682 ret = arm_smmu_init_strtab_2lvl(smmu); in arm_smmu_init_strtab()
3684 ret = arm_smmu_init_strtab_linear(smmu); in arm_smmu_init_strtab()
3688 ida_init(&smmu->vmid_map); in arm_smmu_init_strtab()
3693 static int arm_smmu_init_structures(struct arm_smmu_device *smmu) in arm_smmu_init_structures() argument
3697 mutex_init(&smmu->streams_mutex); in arm_smmu_init_structures()
3698 smmu->streams = RB_ROOT; in arm_smmu_init_structures()
3700 ret = arm_smmu_init_queues(smmu); in arm_smmu_init_structures()
3704 ret = arm_smmu_init_strtab(smmu); in arm_smmu_init_structures()
3708 if (smmu->impl_ops && smmu->impl_ops->init_structures) in arm_smmu_init_structures()
3709 return smmu->impl_ops->init_structures(smmu); in arm_smmu_init_structures()
3714 static int arm_smmu_write_reg_sync(struct arm_smmu_device *smmu, u32 val, in arm_smmu_write_reg_sync() argument
3719 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()
3720 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, in arm_smmu_write_reg_sync()
3725 static int arm_smmu_update_gbpa(struct arm_smmu_device *smmu, u32 set, u32 clr) in arm_smmu_update_gbpa() argument
3728 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; in arm_smmu_update_gbpa()
3742 dev_err(smmu->dev, "GBPA not responding to update\n"); in arm_smmu_update_gbpa()
3757 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_write_msi_msg() local
3763 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3764 writel_relaxed(msg->data, smmu->base + cfg[1]); in arm_smmu_write_msi_msg()
3765 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); in arm_smmu_write_msi_msg()
3768 static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) in arm_smmu_setup_msis() argument
3771 struct device *dev = smmu->dev; in arm_smmu_setup_msis()
3774 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3775 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3777 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_msis()
3778 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3782 if (!(smmu->features & ARM_SMMU_FEAT_MSI)) in arm_smmu_setup_msis()
3786 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3797 smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); in arm_smmu_setup_msis()
3798 smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); in arm_smmu_setup_msis()
3799 smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); in arm_smmu_setup_msis()
3805 static void arm_smmu_setup_unique_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_unique_irqs() argument
3809 arm_smmu_setup_msis(smmu); in arm_smmu_setup_unique_irqs()
3812 irq = smmu->evtq.q.irq; in arm_smmu_setup_unique_irqs()
3814 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3817 "arm-smmu-v3-evtq", smmu); in arm_smmu_setup_unique_irqs()
3819 dev_warn(smmu->dev, "failed to enable evtq irq\n"); in arm_smmu_setup_unique_irqs()
3821 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3824 irq = smmu->gerr_irq; in arm_smmu_setup_unique_irqs()
3826 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, in arm_smmu_setup_unique_irqs()
3827 0, "arm-smmu-v3-gerror", smmu); in arm_smmu_setup_unique_irqs()
3829 dev_warn(smmu->dev, "failed to enable gerror irq\n"); in arm_smmu_setup_unique_irqs()
3831 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3834 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_setup_unique_irqs()
3835 irq = smmu->priq.q.irq; in arm_smmu_setup_unique_irqs()
3837 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3840 "arm-smmu-v3-priq", in arm_smmu_setup_unique_irqs()
3841 smmu); in arm_smmu_setup_unique_irqs()
3843 dev_warn(smmu->dev, in arm_smmu_setup_unique_irqs()
3846 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); in arm_smmu_setup_unique_irqs()
3851 static int arm_smmu_setup_irqs(struct arm_smmu_device *smmu) in arm_smmu_setup_irqs() argument
3857 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_IRQ_CTRL, in arm_smmu_setup_irqs()
3860 dev_err(smmu->dev, "failed to disable irqs\n"); in arm_smmu_setup_irqs()
3864 irq = smmu->combined_irq; in arm_smmu_setup_irqs()
3870 ret = devm_request_threaded_irq(smmu->dev, irq, in arm_smmu_setup_irqs()
3874 "arm-smmu-v3-combined-irq", smmu); in arm_smmu_setup_irqs()
3876 dev_warn(smmu->dev, "failed to enable combined irq\n"); in arm_smmu_setup_irqs()
3878 arm_smmu_setup_unique_irqs(smmu); in arm_smmu_setup_irqs()
3880 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_irqs()
3883 /* Enable interrupt generation on the SMMU */ in arm_smmu_setup_irqs()
3884 ret = arm_smmu_write_reg_sync(smmu, irqen_flags, in arm_smmu_setup_irqs()
3887 dev_warn(smmu->dev, "failed to enable irqs\n"); in arm_smmu_setup_irqs()
3892 static int arm_smmu_device_disable(struct arm_smmu_device *smmu) in arm_smmu_device_disable() argument
3896 ret = arm_smmu_write_reg_sync(smmu, 0, ARM_SMMU_CR0, ARM_SMMU_CR0ACK); in arm_smmu_device_disable()
3898 dev_err(smmu->dev, "failed to clear cr0\n"); in arm_smmu_device_disable()
3903 static void arm_smmu_write_strtab(struct arm_smmu_device *smmu) in arm_smmu_write_strtab() argument
3905 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_write_strtab()
3909 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_write_strtab()
3919 FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); in arm_smmu_write_strtab()
3923 smmu->base + ARM_SMMU_STRTAB_BASE); in arm_smmu_write_strtab()
3924 writel_relaxed(reg, smmu->base + ARM_SMMU_STRTAB_BASE_CFG); in arm_smmu_write_strtab()
3927 static int arm_smmu_device_reset(struct arm_smmu_device *smmu) in arm_smmu_device_reset() argument
3933 /* Clear CR0 and sync (disables SMMU and queue processing) */ in arm_smmu_device_reset()
3934 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); in arm_smmu_device_reset()
3936 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); in arm_smmu_device_reset()
3937 arm_smmu_update_gbpa(smmu, GBPA_ABORT, 0); in arm_smmu_device_reset()
3940 ret = arm_smmu_device_disable(smmu); in arm_smmu_device_reset()
3951 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); in arm_smmu_device_reset()
3956 if (smmu->features & ARM_SMMU_FEAT_E2H) in arm_smmu_device_reset()
3959 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); in arm_smmu_device_reset()
3962 arm_smmu_write_strtab(smmu); in arm_smmu_device_reset()
3965 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
3966 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); in arm_smmu_device_reset()
3967 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); in arm_smmu_device_reset()
3970 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3973 dev_err(smmu->dev, "failed to enable command queue\n"); in arm_smmu_device_reset()
3979 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3982 if (smmu->features & ARM_SMMU_FEAT_HYP) { in arm_smmu_device_reset()
3984 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3988 arm_smmu_cmdq_issue_cmd_with_sync(smmu, &cmd); in arm_smmu_device_reset()
3991 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
3992 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); in arm_smmu_device_reset()
3993 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); in arm_smmu_device_reset()
3996 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
3999 dev_err(smmu->dev, "failed to enable event queue\n"); in arm_smmu_device_reset()
4004 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_device_reset()
4005 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
4006 smmu->base + ARM_SMMU_PRIQ_BASE); in arm_smmu_device_reset()
4007 writel_relaxed(smmu->priq.q.llq.prod, in arm_smmu_device_reset()
4008 smmu->page1 + ARM_SMMU_PRIQ_PROD); in arm_smmu_device_reset()
4009 writel_relaxed(smmu->priq.q.llq.cons, in arm_smmu_device_reset()
4010 smmu->page1 + ARM_SMMU_PRIQ_CONS); in arm_smmu_device_reset()
4013 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
4016 dev_err(smmu->dev, "failed to enable PRI queue\n"); in arm_smmu_device_reset()
4021 if (smmu->features & ARM_SMMU_FEAT_ATS) { in arm_smmu_device_reset()
4023 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
4026 dev_err(smmu->dev, "failed to enable ATS check\n"); in arm_smmu_device_reset()
4031 ret = arm_smmu_setup_irqs(smmu); in arm_smmu_device_reset()
4033 dev_err(smmu->dev, "failed to setup irqs\n"); in arm_smmu_device_reset()
4040 /* Enable the SMMU interface */ in arm_smmu_device_reset()
4042 ret = arm_smmu_write_reg_sync(smmu, enables, ARM_SMMU_CR0, in arm_smmu_device_reset()
4045 dev_err(smmu->dev, "failed to enable SMMU interface\n"); in arm_smmu_device_reset()
4049 if (smmu->impl_ops && smmu->impl_ops->device_reset) { in arm_smmu_device_reset()
4050 ret = smmu->impl_ops->device_reset(smmu); in arm_smmu_device_reset()
4052 dev_err(smmu->dev, "failed to reset impl\n"); in arm_smmu_device_reset()
4064 static void arm_smmu_device_iidr_probe(struct arm_smmu_device *smmu) in arm_smmu_device_iidr_probe() argument
4069 reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR); in arm_smmu_device_iidr_probe()
4081 smmu->features &= ~ARM_SMMU_FEAT_SEV; in arm_smmu_device_iidr_probe()
4084 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
4088 smmu->features &= ~ARM_SMMU_FEAT_BTM; in arm_smmu_device_iidr_probe()
4089 smmu->options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC; in arm_smmu_device_iidr_probe()
4091 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
4098 static void arm_smmu_get_httu(struct arm_smmu_device *smmu, u32 reg) in arm_smmu_get_httu() argument
4100 u32 fw_features = smmu->features & (ARM_SMMU_FEAT_HA | ARM_SMMU_FEAT_HD); in arm_smmu_get_httu()
4111 if (smmu->dev->of_node) in arm_smmu_get_httu()
4112 smmu->features |= hw_features; in arm_smmu_get_httu()
4115 dev_warn(smmu->dev, in arm_smmu_get_httu()
4120 static int arm_smmu_device_hw_probe(struct arm_smmu_device *smmu) in arm_smmu_device_hw_probe() argument
4123 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_hw_probe()
4126 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); in arm_smmu_device_hw_probe()
4130 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
4133 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; in arm_smmu_device_hw_probe()
4142 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
4146 smmu->features |= ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
4150 smmu->features |= ARM_SMMU_FEAT_TT_LE; in arm_smmu_device_hw_probe()
4154 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); in arm_smmu_device_hw_probe()
4160 smmu->features |= ARM_SMMU_FEAT_PRI; in arm_smmu_device_hw_probe()
4163 smmu->features |= ARM_SMMU_FEAT_ATS; in arm_smmu_device_hw_probe()
4166 smmu->features |= ARM_SMMU_FEAT_SEV; in arm_smmu_device_hw_probe()
4169 smmu->features |= ARM_SMMU_FEAT_MSI; in arm_smmu_device_hw_probe()
4171 smmu->options |= ARM_SMMU_OPT_MSIPOLL; in arm_smmu_device_hw_probe()
4175 smmu->features |= ARM_SMMU_FEAT_HYP; in arm_smmu_device_hw_probe()
4177 smmu->features |= ARM_SMMU_FEAT_E2H; in arm_smmu_device_hw_probe()
4180 arm_smmu_get_httu(smmu, reg); in arm_smmu_device_hw_probe()
4187 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", in arm_smmu_device_hw_probe()
4192 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; in arm_smmu_device_hw_probe()
4195 smmu->features |= ARM_SMMU_FEAT_STALLS; in arm_smmu_device_hw_probe()
4199 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_hw_probe()
4202 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_hw_probe()
4205 dev_err(smmu->dev, "no translation support!\n"); in arm_smmu_device_hw_probe()
4212 smmu->ias = 40; in arm_smmu_device_hw_probe()
4217 dev_err(smmu->dev, "AArch64 table format not supported!\n"); in arm_smmu_device_hw_probe()
4222 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; in arm_smmu_device_hw_probe()
4223 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; in arm_smmu_device_hw_probe()
4226 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); in arm_smmu_device_hw_probe()
4228 dev_err(smmu->dev, "embedded implementation not supported\n"); in arm_smmu_device_hw_probe()
4233 smmu->features |= ARM_SMMU_FEAT_ATTR_TYPES_OVR; in arm_smmu_device_hw_probe()
4236 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4238 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { in arm_smmu_device_hw_probe()
4245 dev_err(smmu->dev, "command queue size <= %d entries not supported\n", in arm_smmu_device_hw_probe()
4250 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4252 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4256 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); in arm_smmu_device_hw_probe()
4257 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); in arm_smmu_device_hw_probe()
4258 smmu->iommu.max_pasids = 1UL << smmu->ssid_bits; in arm_smmu_device_hw_probe()
4261 * If the SMMU supports fewer bits than would fill a single L2 stream in arm_smmu_device_hw_probe()
4264 if (smmu->sid_bits <= STRTAB_SPLIT) in arm_smmu_device_hw_probe()
4265 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
4268 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); in arm_smmu_device_hw_probe()
4270 smmu->features |= ARM_SMMU_FEAT_RANGE_INV; in arm_smmu_device_hw_probe()
4273 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); in arm_smmu_device_hw_probe()
4276 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); in arm_smmu_device_hw_probe()
4280 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_hw_probe()
4282 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_hw_probe()
4284 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_hw_probe()
4288 smmu->features |= ARM_SMMU_FEAT_VAX; in arm_smmu_device_hw_probe()
4293 smmu->oas = 32; in arm_smmu_device_hw_probe()
4296 smmu->oas = 36; in arm_smmu_device_hw_probe()
4299 smmu->oas = 40; in arm_smmu_device_hw_probe()
4302 smmu->oas = 42; in arm_smmu_device_hw_probe()
4305 smmu->oas = 44; in arm_smmu_device_hw_probe()
4308 smmu->oas = 52; in arm_smmu_device_hw_probe()
4309 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ in arm_smmu_device_hw_probe()
4312 dev_info(smmu->dev, in arm_smmu_device_hw_probe()
4316 smmu->oas = 48; in arm_smmu_device_hw_probe()
4320 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
4322 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
4325 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) in arm_smmu_device_hw_probe()
4326 dev_warn(smmu->dev, in arm_smmu_device_hw_probe()
4329 smmu->ias = max(smmu->ias, smmu->oas); in arm_smmu_device_hw_probe()
4331 if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) && in arm_smmu_device_hw_probe()
4332 (smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_device_hw_probe()
4333 smmu->features |= ARM_SMMU_FEAT_NESTING; in arm_smmu_device_hw_probe()
4335 arm_smmu_device_iidr_probe(smmu); in arm_smmu_device_hw_probe()
4337 if (arm_smmu_sva_supported(smmu)) in arm_smmu_device_hw_probe()
4338 smmu->features |= ARM_SMMU_FEAT_SVA; in arm_smmu_device_hw_probe()
4340 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", in arm_smmu_device_hw_probe()
4341 smmu->ias, smmu->oas, smmu->features); in arm_smmu_device_hw_probe()
4348 struct arm_smmu_device *smmu) in acpi_smmu_dsdt_probe_tegra241_cmdqv() argument
4353 /* Look for an NVDA200C node whose _UID matches the SMMU node ID */ in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4357 smmu->impl_dev = &adev->dev; in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4358 smmu->options |= ARM_SMMU_OPT_TEGRA241_CMDQV; in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4359 dev_info(smmu->dev, "found companion CMDQV device: %s\n", in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4360 dev_name(smmu->impl_dev)); in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4366 struct arm_smmu_device *smmu) in acpi_smmu_dsdt_probe_tegra241_cmdqv() argument
4372 struct arm_smmu_device *smmu) in acpi_smmu_iort_probe_model() argument
4379 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; in acpi_smmu_iort_probe_model()
4382 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; in acpi_smmu_iort_probe_model()
4386 * Tegra241 implementation stores its SMMU options and impl_dev in acpi_smmu_iort_probe_model()
4389 acpi_smmu_dsdt_probe_tegra241_cmdqv(node, smmu); in acpi_smmu_iort_probe_model()
4393 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); in acpi_smmu_iort_probe_model()
4398 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
4401 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
4410 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_acpi_probe()
4414 smmu->features |= ARM_SMMU_FEAT_HD; in arm_smmu_device_acpi_probe()
4417 smmu->features |= ARM_SMMU_FEAT_HA; in arm_smmu_device_acpi_probe()
4420 return acpi_smmu_iort_probe_model(node, smmu); in arm_smmu_device_acpi_probe()
4424 struct arm_smmu_device *smmu) in arm_smmu_device_acpi_probe() argument
4431 struct arm_smmu_device *smmu) in arm_smmu_device_dt_probe() argument
4444 parse_driver_options(smmu); in arm_smmu_device_dt_probe()
4447 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_dt_probe()
4452 static unsigned long arm_smmu_resource_size(struct arm_smmu_device *smmu) in arm_smmu_resource_size() argument
4454 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) in arm_smmu_resource_size()
4468 static void arm_smmu_rmr_install_bypass_ste(struct arm_smmu_device *smmu) in arm_smmu_rmr_install_bypass_ste() argument
4474 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
4482 ret = arm_smmu_init_sid_strtab(smmu, rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
4484 dev_err(smmu->dev, "RMR SID(0x%x) bypass failed\n", in arm_smmu_rmr_install_bypass_ste()
4493 arm_smmu_make_bypass_ste(smmu, in arm_smmu_rmr_install_bypass_ste()
4494 arm_smmu_get_step_for_sid(smmu, rmr->sids[i])); in arm_smmu_rmr_install_bypass_ste()
4498 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
4503 struct arm_smmu_device *smmu = data; in arm_smmu_impl_remove() local
4505 if (smmu->impl_ops && smmu->impl_ops->device_remove) in arm_smmu_impl_remove()
4506 smmu->impl_ops->device_remove(smmu); in arm_smmu_impl_remove()
4514 static struct arm_smmu_device *arm_smmu_impl_probe(struct arm_smmu_device *smmu) in arm_smmu_impl_probe() argument
4519 if (smmu->impl_dev && (smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV)) in arm_smmu_impl_probe()
4520 new_smmu = tegra241_cmdqv_probe(smmu); in arm_smmu_impl_probe()
4523 return smmu; in arm_smmu_impl_probe()
4539 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
4542 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
4543 if (!smmu) in arm_smmu_device_probe()
4545 smmu->dev = dev; in arm_smmu_device_probe()
4548 ret = arm_smmu_device_dt_probe(pdev, smmu); in arm_smmu_device_probe()
4550 ret = arm_smmu_device_acpi_probe(pdev, smmu); in arm_smmu_device_probe()
4555 smmu = arm_smmu_impl_probe(smmu); in arm_smmu_device_probe()
4556 if (IS_ERR(smmu)) in arm_smmu_device_probe()
4557 return PTR_ERR(smmu); in arm_smmu_device_probe()
4563 if (resource_size(res) < arm_smmu_resource_size(smmu)) { in arm_smmu_device_probe()
4573 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); in arm_smmu_device_probe()
4574 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
4575 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
4577 if (arm_smmu_resource_size(smmu) > SZ_64K) { in arm_smmu_device_probe()
4578 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, in arm_smmu_device_probe()
4580 if (IS_ERR(smmu->page1)) in arm_smmu_device_probe()
4581 return PTR_ERR(smmu->page1); in arm_smmu_device_probe()
4583 smmu->page1 = smmu->base; in arm_smmu_device_probe()
4590 smmu->combined_irq = irq; in arm_smmu_device_probe()
4594 smmu->evtq.q.irq = irq; in arm_smmu_device_probe()
4598 smmu->priq.q.irq = irq; in arm_smmu_device_probe()
4602 smmu->gerr_irq = irq; in arm_smmu_device_probe()
4605 ret = arm_smmu_device_hw_probe(smmu); in arm_smmu_device_probe()
4610 ret = arm_smmu_init_structures(smmu); in arm_smmu_device_probe()
4615 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
4618 arm_smmu_rmr_install_bypass_ste(smmu); in arm_smmu_device_probe()
4621 ret = arm_smmu_device_reset(smmu); in arm_smmu_device_probe()
4626 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, in arm_smmu_device_probe()
4631 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
4634 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
4643 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
4645 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
4646 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
4647 arm_smmu_device_disable(smmu); in arm_smmu_device_remove()
4648 iopf_queue_free(smmu->evtq.iopf); in arm_smmu_device_remove()
4649 ida_destroy(&smmu->vmid_map); in arm_smmu_device_remove()
4654 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_shutdown() local
4656 arm_smmu_device_disable(smmu); in arm_smmu_device_shutdown()
4660 { .compatible = "arm,smmu-v3", },
4673 .name = "arm-smmu-v3",
4686 MODULE_ALIAS("platform:arm-smmu-v3");