Lines Matching +full:mixed +full:- +full:signals
1 // SPDX-License-Identifier: GPL-2.0
19 #include <linux/io-pgtable.h>
27 #include <linux/pci-ats.h>
32 #include "arm-smmu-v3.h"
33 #include "../../dma-iommu.h"
38 "Disable MSI-based polling for CMD_SYNC completion.");
81 { ARM_SMMU_OPT_SKIP_PREFETCH, "hisilicon,broken-prefetch-cmd" },
82 { ARM_SMMU_OPT_PAGE0_REGS_ONLY, "cavium,cn9900-broken-page1-regspace"},
95 if (of_property_read_bool(smmu->dev->of_node, in parse_driver_options()
97 smmu->options |= arm_smmu_options[i].opt; in parse_driver_options()
98 dev_notice(smmu->dev, "option %s\n", in parse_driver_options()
104 /* Low-level queue manipulation functions */
109 prod = Q_IDX(q, q->prod); in queue_has_space()
110 cons = Q_IDX(q, q->cons); in queue_has_space()
112 if (Q_WRP(q, q->prod) == Q_WRP(q, q->cons)) in queue_has_space()
113 space = (1 << q->max_n_shift) - (prod - cons); in queue_has_space()
115 space = cons - prod; in queue_has_space()
122 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && in queue_full()
123 Q_WRP(q, q->prod) != Q_WRP(q, q->cons); in queue_full()
128 return Q_IDX(q, q->prod) == Q_IDX(q, q->cons) && in queue_empty()
129 Q_WRP(q, q->prod) == Q_WRP(q, q->cons); in queue_empty()
134 return ((Q_WRP(q, q->cons) == Q_WRP(q, prod)) && in queue_consumed()
135 (Q_IDX(q, q->cons) > Q_IDX(q, prod))) || in queue_consumed()
136 ((Q_WRP(q, q->cons) != Q_WRP(q, prod)) && in queue_consumed()
137 (Q_IDX(q, q->cons) <= Q_IDX(q, prod))); in queue_consumed()
147 writel_relaxed(q->llq.cons, q->cons_reg); in queue_sync_cons_out()
152 u32 cons = (Q_WRP(q, q->cons) | Q_IDX(q, q->cons)) + 1; in queue_inc_cons()
153 q->cons = Q_OVF(q->cons) | Q_WRP(q, cons) | Q_IDX(q, cons); in queue_inc_cons()
158 struct arm_smmu_ll_queue *llq = &q->llq; in queue_sync_cons_ovf()
160 if (likely(Q_OVF(llq->prod) == Q_OVF(llq->cons))) in queue_sync_cons_ovf()
163 llq->cons = Q_OVF(llq->prod) | Q_WRP(llq, llq->cons) | in queue_sync_cons_ovf()
164 Q_IDX(llq, llq->cons); in queue_sync_cons_ovf()
178 prod = readl(q->prod_reg); in queue_sync_prod_in()
180 if (Q_OVF(prod) != Q_OVF(q->llq.prod)) in queue_sync_prod_in()
181 ret = -EOVERFLOW; in queue_sync_prod_in()
183 q->llq.prod = prod; in queue_sync_prod_in()
189 u32 prod = (Q_WRP(q, q->prod) | Q_IDX(q, q->prod)) + n; in queue_inc_prod_n()
190 return Q_OVF(q->prod) | Q_WRP(q, prod) | Q_IDX(q, prod); in queue_inc_prod_n()
196 qp->delay = 1; in queue_poll_init()
197 qp->spin_cnt = 0; in queue_poll_init()
198 qp->wfe = !!(smmu->features & ARM_SMMU_FEAT_SEV); in queue_poll_init()
199 qp->timeout = ktime_add_us(ktime_get(), ARM_SMMU_POLL_TIMEOUT_US); in queue_poll_init()
204 if (ktime_compare(ktime_get(), qp->timeout) > 0) in queue_poll()
205 return -ETIMEDOUT; in queue_poll()
207 if (qp->wfe) { in queue_poll()
209 } else if (++qp->spin_cnt < ARM_SMMU_POLL_SPIN_COUNT) { in queue_poll()
212 udelay(qp->delay); in queue_poll()
213 qp->delay *= 2; in queue_poll()
214 qp->spin_cnt = 0; in queue_poll()
238 if (queue_empty(&q->llq)) in queue_remove_raw()
239 return -EAGAIN; in queue_remove_raw()
241 queue_read(ent, Q_ENT(q, q->llq.cons), q->ent_dwords); in queue_remove_raw()
242 queue_inc_cons(&q->llq); in queue_remove_raw()
247 /* High-level queue accessors */
251 cmd[0] |= FIELD_PREP(CMDQ_0_OP, ent->opcode); in arm_smmu_cmdq_build_cmd()
253 switch (ent->opcode) { in arm_smmu_cmdq_build_cmd()
258 cmd[0] |= FIELD_PREP(CMDQ_PREFETCH_0_SID, ent->prefetch.sid); in arm_smmu_cmdq_build_cmd()
261 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SSID, ent->cfgi.ssid); in arm_smmu_cmdq_build_cmd()
264 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
265 cmd[1] |= FIELD_PREP(CMDQ_CFGI_1_LEAF, ent->cfgi.leaf); in arm_smmu_cmdq_build_cmd()
268 cmd[0] |= FIELD_PREP(CMDQ_CFGI_0_SID, ent->cfgi.sid); in arm_smmu_cmdq_build_cmd()
275 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
278 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
279 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
280 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
281 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
282 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
283 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
284 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_VA_MASK; in arm_smmu_cmdq_build_cmd()
287 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_NUM, ent->tlbi.num); in arm_smmu_cmdq_build_cmd()
288 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_SCALE, ent->tlbi.scale); in arm_smmu_cmdq_build_cmd()
289 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
290 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_LEAF, ent->tlbi.leaf); in arm_smmu_cmdq_build_cmd()
291 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TTL, ent->tlbi.ttl); in arm_smmu_cmdq_build_cmd()
292 cmd[1] |= FIELD_PREP(CMDQ_TLBI_1_TG, ent->tlbi.tg); in arm_smmu_cmdq_build_cmd()
293 cmd[1] |= ent->tlbi.addr & CMDQ_TLBI_1_IPA_MASK; in arm_smmu_cmdq_build_cmd()
296 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
299 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_VMID, ent->tlbi.vmid); in arm_smmu_cmdq_build_cmd()
302 cmd[0] |= FIELD_PREP(CMDQ_TLBI_0_ASID, ent->tlbi.asid); in arm_smmu_cmdq_build_cmd()
305 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
306 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_GLOBAL, ent->atc.global); in arm_smmu_cmdq_build_cmd()
307 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SSID, ent->atc.ssid); in arm_smmu_cmdq_build_cmd()
308 cmd[0] |= FIELD_PREP(CMDQ_ATC_0_SID, ent->atc.sid); in arm_smmu_cmdq_build_cmd()
309 cmd[1] |= FIELD_PREP(CMDQ_ATC_1_SIZE, ent->atc.size); in arm_smmu_cmdq_build_cmd()
310 cmd[1] |= ent->atc.addr & CMDQ_ATC_1_ADDR_MASK; in arm_smmu_cmdq_build_cmd()
313 cmd[0] |= FIELD_PREP(CMDQ_0_SSV, ent->substream_valid); in arm_smmu_cmdq_build_cmd()
314 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SSID, ent->pri.ssid); in arm_smmu_cmdq_build_cmd()
315 cmd[0] |= FIELD_PREP(CMDQ_PRI_0_SID, ent->pri.sid); in arm_smmu_cmdq_build_cmd()
316 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_GRPID, ent->pri.grpid); in arm_smmu_cmdq_build_cmd()
317 switch (ent->pri.resp) { in arm_smmu_cmdq_build_cmd()
323 return -EINVAL; in arm_smmu_cmdq_build_cmd()
325 cmd[1] |= FIELD_PREP(CMDQ_PRI_1_RESP, ent->pri.resp); in arm_smmu_cmdq_build_cmd()
328 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_SID, ent->resume.sid); in arm_smmu_cmdq_build_cmd()
329 cmd[0] |= FIELD_PREP(CMDQ_RESUME_0_RESP, ent->resume.resp); in arm_smmu_cmdq_build_cmd()
330 cmd[1] |= FIELD_PREP(CMDQ_RESUME_1_STAG, ent->resume.stag); in arm_smmu_cmdq_build_cmd()
333 if (ent->sync.msiaddr) { in arm_smmu_cmdq_build_cmd()
335 cmd[1] |= ent->sync.msiaddr & CMDQ_SYNC_1_MSIADDR_MASK; in arm_smmu_cmdq_build_cmd()
343 return -ENOENT; in arm_smmu_cmdq_build_cmd()
354 if (smmu->impl_ops && smmu->impl_ops->get_secondary_cmdq) in arm_smmu_get_cmdq()
355 cmdq = smmu->impl_ops->get_secondary_cmdq(smmu, ent); in arm_smmu_get_cmdq()
357 return cmdq ?: &smmu->cmdq; in arm_smmu_get_cmdq()
363 if (cmdq == &smmu->cmdq) in arm_smmu_cmdq_needs_busy_polling()
366 return smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV; in arm_smmu_cmdq_needs_busy_polling()
372 struct arm_smmu_queue *q = &cmdq->q; in arm_smmu_cmdq_build_sync_cmd()
381 if (smmu->options & ARM_SMMU_OPT_MSIPOLL) { in arm_smmu_cmdq_build_sync_cmd()
382 ent.sync.msiaddr = q->base_dma + Q_IDX(&q->llq, prod) * in arm_smmu_cmdq_build_sync_cmd()
383 q->ent_dwords * 8; in arm_smmu_cmdq_build_sync_cmd()
400 struct arm_smmu_queue *q = &cmdq->q; in __arm_smmu_cmdq_skip_err()
404 u32 cons = readl_relaxed(q->cons_reg); in __arm_smmu_cmdq_skip_err()
410 dev_err(smmu->dev, "CMDQ error (cons 0x%08x): %s\n", cons, in __arm_smmu_cmdq_skip_err()
415 dev_err(smmu->dev, "retrying command fetch\n"); in __arm_smmu_cmdq_skip_err()
436 queue_read(cmd, Q_ENT(q, cons), q->ent_dwords); in __arm_smmu_cmdq_skip_err()
437 dev_err(smmu->dev, "skipping command in error state:\n"); in __arm_smmu_cmdq_skip_err()
439 dev_err(smmu->dev, "\t0x%016llx\n", (unsigned long long)cmd[i]); in __arm_smmu_cmdq_skip_err()
446 queue_write(Q_ENT(q, cons), cmd, q->ent_dwords); in __arm_smmu_cmdq_skip_err()
451 __arm_smmu_cmdq_skip_err(smmu, &smmu->cmdq); in arm_smmu_cmdq_skip_err()
458 * - The only LOCK routines are exclusive_trylock() and shared_lock().
462 * - The UNLOCK routines are supplemented with shared_tryunlock(), which
476 if (atomic_fetch_inc_relaxed(&cmdq->lock) >= 0) in arm_smmu_cmdq_shared_lock()
480 val = atomic_cond_read_relaxed(&cmdq->lock, VAL >= 0); in arm_smmu_cmdq_shared_lock()
481 } while (atomic_cmpxchg_relaxed(&cmdq->lock, val, val + 1) != val); in arm_smmu_cmdq_shared_lock()
486 (void)atomic_dec_return_release(&cmdq->lock); in arm_smmu_cmdq_shared_unlock()
491 if (atomic_read(&cmdq->lock) == 1) in arm_smmu_cmdq_shared_tryunlock()
502 __ret = !atomic_cmpxchg_relaxed(&cmdq->lock, 0, INT_MIN); \
510 atomic_set_release(&cmdq->lock, 0); \
519 * you like mixed-size concurrency, dependency ordering and relaxed atomics,
559 .max_n_shift = cmdq->q.llq.max_n_shift, in __arm_smmu_cmdq_poll_set_valid_map()
574 ptr = &cmdq->valid_map[swidx]; in __arm_smmu_cmdq_poll_set_valid_map()
579 mask = GENMASK(limit - 1, sbidx); in __arm_smmu_cmdq_poll_set_valid_map()
583 * that a zero-initialised queue is invalid and, after marking in __arm_smmu_cmdq_poll_set_valid_map()
596 llq.prod = queue_inc_prod_n(&llq, limit - sbidx); in __arm_smmu_cmdq_poll_set_valid_map()
614 /* Wait for the command queue to become non-full */
628 WRITE_ONCE(cmdq->q.llq.cons, readl_relaxed(cmdq->q.cons_reg)); in arm_smmu_cmdq_poll_until_not_full()
630 llq->val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_poll_until_not_full()
636 llq->val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_poll_until_not_full()
647 * Wait until the SMMU signals a CMD_SYNC completion MSI.
656 u32 *cmd = (u32 *)(Q_ENT(&cmdq->q, llq->prod)); in __arm_smmu_cmdq_poll_until_msi()
666 llq->cons = ret ? llq->prod : queue_inc_prod_n(llq, 1); in __arm_smmu_cmdq_poll_until_msi()
671 * Wait until the SMMU cons index passes llq->prod.
679 u32 prod = llq->prod; in __arm_smmu_cmdq_poll_until_consumed()
683 llq->val = READ_ONCE(cmdq->q.llq.val); in __arm_smmu_cmdq_poll_until_consumed()
698 * cmdq->q.llq.cons. Roughly speaking: in __arm_smmu_cmdq_poll_until_consumed()
718 llq->cons = readl(cmdq->q.cons_reg); in __arm_smmu_cmdq_poll_until_consumed()
728 if (smmu->options & ARM_SMMU_OPT_MSIPOLL && in arm_smmu_cmdq_poll_until_sync()
740 .max_n_shift = cmdq->q.llq.max_n_shift, in arm_smmu_cmdq_write_entries()
748 queue_write(Q_ENT(&cmdq->q, prod), cmd, CMDQ_ENT_DWORDS); in arm_smmu_cmdq_write_entries()
756 * - There is a dma_wmb() before publishing any commands to the queue.
760 * - On completion of a CMD_SYNC, there is a control dependency.
764 * - Command insertion is totally ordered, so if two CPUs each race to
779 llq.max_n_shift = cmdq->q.llq.max_n_shift; in arm_smmu_cmdq_issue_cmdlist()
783 llq.val = READ_ONCE(cmdq->q.llq.val); in arm_smmu_cmdq_issue_cmdlist()
790 dev_err_ratelimited(smmu->dev, "CMDQ timeout\n"); in arm_smmu_cmdq_issue_cmdlist()
798 old = cmpxchg_relaxed(&cmdq->q.llq.val, llq.val, head.val); in arm_smmu_cmdq_issue_cmdlist()
816 queue_write(Q_ENT(&cmdq->q, prod), cmd_sync, CMDQ_ENT_DWORDS); in arm_smmu_cmdq_issue_cmdlist()
834 atomic_cond_read_relaxed(&cmdq->owner_prod, VAL == llq.prod); in arm_smmu_cmdq_issue_cmdlist()
838 &cmdq->q.llq.atomic.prod); in arm_smmu_cmdq_issue_cmdlist()
852 writel_relaxed(prod, cmdq->q.prod_reg); in arm_smmu_cmdq_issue_cmdlist()
859 atomic_set_release(&cmdq->owner_prod, prod); in arm_smmu_cmdq_issue_cmdlist()
867 dev_err_ratelimited(smmu->dev, in arm_smmu_cmdq_issue_cmdlist()
870 readl_relaxed(cmdq->q.prod_reg), in arm_smmu_cmdq_issue_cmdlist()
871 readl_relaxed(cmdq->q.cons_reg)); in arm_smmu_cmdq_issue_cmdlist()
876 * reader, in which case we can safely update cmdq->q.llq.cons in arm_smmu_cmdq_issue_cmdlist()
879 WRITE_ONCE(cmdq->q.llq.cons, llq.cons); in arm_smmu_cmdq_issue_cmdlist()
895 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in __arm_smmu_cmdq_issue_cmd()
896 ent->opcode); in __arm_smmu_cmdq_issue_cmd()
897 return -EINVAL; in __arm_smmu_cmdq_issue_cmd()
920 cmds->num = 0; in arm_smmu_cmdq_batch_init()
921 cmds->cmdq = arm_smmu_get_cmdq(smmu, ent); in arm_smmu_cmdq_batch_init()
928 bool unsupported_cmd = !arm_smmu_cmdq_supports_cmd(cmds->cmdq, cmd); in arm_smmu_cmdq_batch_add()
929 bool force_sync = (cmds->num == CMDQ_BATCH_ENTRIES - 1) && in arm_smmu_cmdq_batch_add()
930 (smmu->options & ARM_SMMU_OPT_CMDQ_FORCE_SYNC); in arm_smmu_cmdq_batch_add()
934 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_add()
935 cmds->num, true); in arm_smmu_cmdq_batch_add()
939 if (cmds->num == CMDQ_BATCH_ENTRIES) { in arm_smmu_cmdq_batch_add()
940 arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_add()
941 cmds->num, false); in arm_smmu_cmdq_batch_add()
945 index = cmds->num * CMDQ_ENT_DWORDS; in arm_smmu_cmdq_batch_add()
946 if (unlikely(arm_smmu_cmdq_build_cmd(&cmds->cmds[index], cmd))) { in arm_smmu_cmdq_batch_add()
947 dev_warn(smmu->dev, "ignoring unknown CMDQ opcode 0x%x\n", in arm_smmu_cmdq_batch_add()
948 cmd->opcode); in arm_smmu_cmdq_batch_add()
952 cmds->num++; in arm_smmu_cmdq_batch_add()
958 return arm_smmu_cmdq_issue_cmdlist(smmu, cmds->cmdq, cmds->cmds, in arm_smmu_cmdq_batch_submit()
959 cmds->num, true); in arm_smmu_cmdq_batch_submit()
967 int sid = master->streams[0].id; in arm_smmu_page_response()
969 if (WARN_ON(!master->stall_enabled)) in arm_smmu_page_response()
974 cmd.resume.stag = resp->grpid; in arm_smmu_page_response()
975 switch (resp->code) { in arm_smmu_page_response()
987 arm_smmu_cmdq_issue_cmd(master->smmu, &cmd); in arm_smmu_page_response()
1000 .opcode = smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_asid()
1077 writer->ops->get_used(entry, cur_used); in arm_smmu_entry_qword_diff()
1078 writer->ops->get_used(target, target_used); in arm_smmu_entry_qword_diff()
1108 for (i = start; len != 0; len--, i++) { in entry_set()
1116 writer->ops->sync(writer); in entry_set()
1129 * determine which of three updates are required - disruptive, hitless or no
1133 * - Disrupting the entry (V=0)
1134 * - Fill now unused qwords, execpt qword 0 which contains V
1135 * - Make qword 0 have the final value and valid (V=1) with a single 64
1163 unsigned int critical_qword_index = ffs(used_qword_diff) - 1; in arm_smmu_write_entry()
1183 entry_set(writer, entry, target, 1, NUM_ENTRY_QWORDS - 1); in arm_smmu_write_entry()
1202 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_sync_cd()
1212 for (i = 0; i < master->num_streams; i++) { in arm_smmu_sync_cd()
1213 cmd.cfgi.sid = master->streams[i].id; in arm_smmu_sync_cd()
1226 WRITE_ONCE(dst->l2ptr, cpu_to_le64(val)); in arm_smmu_write_cd_l1_desc()
1231 return le64_to_cpu(src->l2ptr) & CTXDESC_L1_DESC_L2PTR_MASK; in arm_smmu_cd_l1_get_desc()
1238 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_get_cd_ptr()
1243 if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_LINEAR) in arm_smmu_get_cd_ptr()
1244 return &cd_table->linear.table[ssid]; in arm_smmu_get_cd_ptr()
1246 l2 = cd_table->l2.l2ptrs[arm_smmu_cdtab_l1_idx(ssid)]; in arm_smmu_get_cd_ptr()
1249 return &l2->cds[arm_smmu_cdtab_l2_idx(ssid)]; in arm_smmu_get_cd_ptr()
1255 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_alloc_cd_ptr()
1256 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_alloc_cd_ptr()
1259 iommu_group_mutex_assert(master->dev); in arm_smmu_alloc_cd_ptr()
1266 if (cd_table->s1fmt == STRTAB_STE_0_S1FMT_64K_L2) { in arm_smmu_alloc_cd_ptr()
1268 struct arm_smmu_cdtab_l2 **l2ptr = &cd_table->l2.l2ptrs[idx]; in arm_smmu_alloc_cd_ptr()
1273 *l2ptr = dma_alloc_coherent(smmu->dev, sizeof(**l2ptr), in arm_smmu_alloc_cd_ptr()
1278 arm_smmu_write_cd_l1_desc(&cd_table->l2.l1tab[idx], in arm_smmu_alloc_cd_ptr()
1319 arm_smmu_sync_cd(writer->master, cd_writer->ssid, true); in arm_smmu_cd_writer_sync_entry()
1331 bool target_valid = target->data[0] & cpu_to_le64(CTXDESC_CD_0_V); in arm_smmu_write_cd_entry()
1332 bool cur_valid = cdptr->data[0] & cpu_to_le64(CTXDESC_CD_0_V); in arm_smmu_write_cd_entry()
1343 master->cd_table.used_ssids--; in arm_smmu_write_cd_entry()
1345 master->cd_table.used_ssids++; in arm_smmu_write_cd_entry()
1348 arm_smmu_write_entry(&cd_writer.writer, cdptr->data, target->data); in arm_smmu_write_cd_entry()
1355 struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; in arm_smmu_make_s1_cd()
1357 &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; in arm_smmu_make_s1_cd()
1358 typeof(&pgtbl_cfg->arm_lpae_s1_cfg.tcr) tcr = in arm_smmu_make_s1_cd()
1359 &pgtbl_cfg->arm_lpae_s1_cfg.tcr; in arm_smmu_make_s1_cd()
1363 target->data[0] = cpu_to_le64( in arm_smmu_make_s1_cd()
1364 FIELD_PREP(CTXDESC_CD_0_TCR_T0SZ, tcr->tsz) | in arm_smmu_make_s1_cd()
1365 FIELD_PREP(CTXDESC_CD_0_TCR_TG0, tcr->tg) | in arm_smmu_make_s1_cd()
1366 FIELD_PREP(CTXDESC_CD_0_TCR_IRGN0, tcr->irgn) | in arm_smmu_make_s1_cd()
1367 FIELD_PREP(CTXDESC_CD_0_TCR_ORGN0, tcr->orgn) | in arm_smmu_make_s1_cd()
1368 FIELD_PREP(CTXDESC_CD_0_TCR_SH0, tcr->sh) | in arm_smmu_make_s1_cd()
1374 FIELD_PREP(CTXDESC_CD_0_TCR_IPS, tcr->ips) | in arm_smmu_make_s1_cd()
1376 (master->stall_enabled ? CTXDESC_CD_0_S : 0) | in arm_smmu_make_s1_cd()
1380 FIELD_PREP(CTXDESC_CD_0_ASID, cd->asid) in arm_smmu_make_s1_cd()
1384 if (pgtbl_cfg->quirks & IO_PGTABLE_QUIRK_ARM_HD) in arm_smmu_make_s1_cd()
1385 target->data[0] |= cpu_to_le64(CTXDESC_CD_0_TCR_HA | in arm_smmu_make_s1_cd()
1388 target->data[1] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.ttbr & in arm_smmu_make_s1_cd()
1390 target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s1_cfg.mair); in arm_smmu_make_s1_cd()
1399 if (!arm_smmu_cdtab_allocated(&master->cd_table)) in arm_smmu_clear_cd()
1412 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_alloc_cd_tables()
1413 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_alloc_cd_tables()
1415 cd_table->s1cdmax = master->ssid_bits; in arm_smmu_alloc_cd_tables()
1416 max_contexts = 1 << cd_table->s1cdmax; in arm_smmu_alloc_cd_tables()
1418 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB) || in arm_smmu_alloc_cd_tables()
1420 cd_table->s1fmt = STRTAB_STE_0_S1FMT_LINEAR; in arm_smmu_alloc_cd_tables()
1421 cd_table->linear.num_ents = max_contexts; in arm_smmu_alloc_cd_tables()
1424 cd_table->linear.table = dma_alloc_coherent(smmu->dev, l1size, in arm_smmu_alloc_cd_tables()
1425 &cd_table->cdtab_dma, in arm_smmu_alloc_cd_tables()
1427 if (!cd_table->linear.table) in arm_smmu_alloc_cd_tables()
1428 return -ENOMEM; in arm_smmu_alloc_cd_tables()
1430 cd_table->s1fmt = STRTAB_STE_0_S1FMT_64K_L2; in arm_smmu_alloc_cd_tables()
1431 cd_table->l2.num_l1_ents = in arm_smmu_alloc_cd_tables()
1434 cd_table->l2.l2ptrs = kcalloc(cd_table->l2.num_l1_ents, in arm_smmu_alloc_cd_tables()
1435 sizeof(*cd_table->l2.l2ptrs), in arm_smmu_alloc_cd_tables()
1437 if (!cd_table->l2.l2ptrs) in arm_smmu_alloc_cd_tables()
1438 return -ENOMEM; in arm_smmu_alloc_cd_tables()
1440 l1size = cd_table->l2.num_l1_ents * sizeof(struct arm_smmu_cdtab_l1); in arm_smmu_alloc_cd_tables()
1441 cd_table->l2.l1tab = dma_alloc_coherent(smmu->dev, l1size, in arm_smmu_alloc_cd_tables()
1442 &cd_table->cdtab_dma, in arm_smmu_alloc_cd_tables()
1444 if (!cd_table->l2.l2ptrs) { in arm_smmu_alloc_cd_tables()
1445 ret = -ENOMEM; in arm_smmu_alloc_cd_tables()
1452 kfree(cd_table->l2.l2ptrs); in arm_smmu_alloc_cd_tables()
1453 cd_table->l2.l2ptrs = NULL; in arm_smmu_alloc_cd_tables()
1460 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_free_cd_tables()
1461 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_free_cd_tables()
1463 if (cd_table->s1fmt != STRTAB_STE_0_S1FMT_LINEAR) { in arm_smmu_free_cd_tables()
1464 for (i = 0; i < cd_table->l2.num_l1_ents; i++) { in arm_smmu_free_cd_tables()
1465 if (!cd_table->l2.l2ptrs[i]) in arm_smmu_free_cd_tables()
1468 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1469 sizeof(*cd_table->l2.l2ptrs[i]), in arm_smmu_free_cd_tables()
1470 cd_table->l2.l2ptrs[i], in arm_smmu_free_cd_tables()
1471 arm_smmu_cd_l1_get_desc(&cd_table->l2.l1tab[i])); in arm_smmu_free_cd_tables()
1473 kfree(cd_table->l2.l2ptrs); in arm_smmu_free_cd_tables()
1475 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1476 cd_table->l2.num_l1_ents * in arm_smmu_free_cd_tables()
1478 cd_table->l2.l1tab, cd_table->cdtab_dma); in arm_smmu_free_cd_tables()
1480 dma_free_coherent(smmu->dev, in arm_smmu_free_cd_tables()
1481 cd_table->linear.num_ents * in arm_smmu_free_cd_tables()
1483 cd_table->linear.table, cd_table->cdtab_dma); in arm_smmu_free_cd_tables()
1497 WRITE_ONCE(dst->l2ptr, cpu_to_le64(val)); in arm_smmu_write_strtab_l1_desc()
1512 .sid = ste_writer->sid, in arm_smmu_ste_writer_sync_entry()
1517 arm_smmu_cmdq_issue_cmd_with_sync(writer->master->smmu, &cmd); in arm_smmu_ste_writer_sync_entry()
1529 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_write_ste()
1538 arm_smmu_write_entry(&ste_writer.writer, ste->data, target->data); in arm_smmu_write_ste()
1541 if (!(smmu->options & ARM_SMMU_OPT_SKIP_PREFETCH)) { in arm_smmu_write_ste()
1556 target->data[0] = cpu_to_le64( in arm_smmu_make_abort_ste()
1567 target->data[0] = cpu_to_le64( in arm_smmu_make_bypass_ste()
1571 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) in arm_smmu_make_bypass_ste()
1572 target->data[1] = cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, in arm_smmu_make_bypass_ste()
1582 struct arm_smmu_ctx_desc_cfg *cd_table = &master->cd_table; in arm_smmu_make_cdtable_ste()
1583 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_make_cdtable_ste()
1586 target->data[0] = cpu_to_le64( in arm_smmu_make_cdtable_ste()
1589 FIELD_PREP(STRTAB_STE_0_S1FMT, cd_table->s1fmt) | in arm_smmu_make_cdtable_ste()
1590 (cd_table->cdtab_dma & STRTAB_STE_0_S1CTXPTR_MASK) | in arm_smmu_make_cdtable_ste()
1591 FIELD_PREP(STRTAB_STE_0_S1CDMAX, cd_table->s1cdmax)); in arm_smmu_make_cdtable_ste()
1593 target->data[1] = cpu_to_le64( in arm_smmu_make_cdtable_ste()
1598 ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_make_cdtable_ste()
1599 !master->stall_enabled) ? in arm_smmu_make_cdtable_ste()
1605 if ((smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) && in arm_smmu_make_cdtable_ste()
1607 target->data[1] |= cpu_to_le64(FIELD_PREP( in arm_smmu_make_cdtable_ste()
1610 if (smmu->features & ARM_SMMU_FEAT_E2H) { in arm_smmu_make_cdtable_ste()
1614 * properly matched. This means either S/NS-EL2-E2H (hypervisor) in arm_smmu_make_cdtable_ste()
1615 * or NS-EL1 (guest). Since an SVA domain can be installed in a in arm_smmu_make_cdtable_ste()
1619 target->data[1] |= cpu_to_le64( in arm_smmu_make_cdtable_ste()
1622 target->data[1] |= cpu_to_le64( in arm_smmu_make_cdtable_ste()
1626 * VMID 0 is reserved for stage-2 bypass EL1 STEs, see in arm_smmu_make_cdtable_ste()
1629 target->data[2] = in arm_smmu_make_cdtable_ste()
1641 struct arm_smmu_s2_cfg *s2_cfg = &smmu_domain->s2_cfg; in arm_smmu_make_s2_domain_ste()
1643 &io_pgtable_ops_to_pgtable(smmu_domain->pgtbl_ops)->cfg; in arm_smmu_make_s2_domain_ste()
1644 typeof(&pgtbl_cfg->arm_lpae_s2_cfg.vtcr) vtcr = in arm_smmu_make_s2_domain_ste()
1645 &pgtbl_cfg->arm_lpae_s2_cfg.vtcr; in arm_smmu_make_s2_domain_ste()
1647 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_make_s2_domain_ste()
1650 target->data[0] = cpu_to_le64( in arm_smmu_make_s2_domain_ste()
1654 target->data[1] = cpu_to_le64( in arm_smmu_make_s2_domain_ste()
1658 if (smmu->features & ARM_SMMU_FEAT_ATTR_TYPES_OVR) in arm_smmu_make_s2_domain_ste()
1659 target->data[1] |= cpu_to_le64(FIELD_PREP(STRTAB_STE_1_SHCFG, in arm_smmu_make_s2_domain_ste()
1662 vtcr_val = FIELD_PREP(STRTAB_STE_2_VTCR_S2T0SZ, vtcr->tsz) | in arm_smmu_make_s2_domain_ste()
1663 FIELD_PREP(STRTAB_STE_2_VTCR_S2SL0, vtcr->sl) | in arm_smmu_make_s2_domain_ste()
1664 FIELD_PREP(STRTAB_STE_2_VTCR_S2IR0, vtcr->irgn) | in arm_smmu_make_s2_domain_ste()
1665 FIELD_PREP(STRTAB_STE_2_VTCR_S2OR0, vtcr->orgn) | in arm_smmu_make_s2_domain_ste()
1666 FIELD_PREP(STRTAB_STE_2_VTCR_S2SH0, vtcr->sh) | in arm_smmu_make_s2_domain_ste()
1667 FIELD_PREP(STRTAB_STE_2_VTCR_S2TG, vtcr->tg) | in arm_smmu_make_s2_domain_ste()
1668 FIELD_PREP(STRTAB_STE_2_VTCR_S2PS, vtcr->ps); in arm_smmu_make_s2_domain_ste()
1669 target->data[2] = cpu_to_le64( in arm_smmu_make_s2_domain_ste()
1670 FIELD_PREP(STRTAB_STE_2_S2VMID, s2_cfg->vmid) | in arm_smmu_make_s2_domain_ste()
1677 (master->stall_enabled ? STRTAB_STE_2_S2S : 0) | in arm_smmu_make_s2_domain_ste()
1680 target->data[3] = cpu_to_le64(pgtbl_cfg->arm_lpae_s2_cfg.vttbr & in arm_smmu_make_s2_domain_ste()
1703 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_l2_strtab()
1706 l2table = &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)]; in arm_smmu_init_l2_strtab()
1710 *l2table = dmam_alloc_coherent(smmu->dev, sizeof(**l2table), in arm_smmu_init_l2_strtab()
1713 dev_err(smmu->dev, in arm_smmu_init_l2_strtab()
1716 return -ENOMEM; in arm_smmu_init_l2_strtab()
1719 arm_smmu_init_initial_stes((*l2table)->stes, in arm_smmu_init_l2_strtab()
1720 ARRAY_SIZE((*l2table)->stes)); in arm_smmu_init_l2_strtab()
1721 arm_smmu_write_strtab_l1_desc(&cfg->l2.l1tab[arm_smmu_strtab_l1_idx(sid)], in arm_smmu_init_l2_strtab()
1732 if (*sid_lhs < stream_rhs->id) in arm_smmu_streams_cmp_key()
1733 return -1; in arm_smmu_streams_cmp_key()
1734 if (*sid_lhs > stream_rhs->id) in arm_smmu_streams_cmp_key()
1743 &rb_entry(lhs, struct arm_smmu_stream, node)->id, rhs); in arm_smmu_streams_cmp_node()
1751 lockdep_assert_held(&smmu->streams_mutex); in arm_smmu_find_master()
1753 node = rb_find(&sid, &smmu->streams, arm_smmu_streams_cmp_key); in arm_smmu_find_master()
1756 return rb_entry(node, struct arm_smmu_stream, node)->master; in arm_smmu_find_master()
1777 return -EOPNOTSUPP; in arm_smmu_handle_evt()
1781 return -EOPNOTSUPP; in arm_smmu_handle_evt()
1794 flt->type = IOMMU_FAULT_PAGE_REQ; in arm_smmu_handle_evt()
1795 flt->prm = (struct iommu_fault_page_request) { in arm_smmu_handle_evt()
1803 flt->prm.flags |= IOMMU_FAULT_PAGE_REQUEST_PASID_VALID; in arm_smmu_handle_evt()
1804 flt->prm.pasid = FIELD_GET(EVTQ_0_SSID, evt[0]); in arm_smmu_handle_evt()
1807 mutex_lock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1810 ret = -EINVAL; in arm_smmu_handle_evt()
1814 ret = iommu_report_device_fault(master->dev, &fault_evt); in arm_smmu_handle_evt()
1816 mutex_unlock(&smmu->streams_mutex); in arm_smmu_handle_evt()
1824 struct arm_smmu_queue *q = &smmu->evtq.q; in arm_smmu_evtq_thread()
1825 struct arm_smmu_ll_queue *llq = &q->llq; in arm_smmu_evtq_thread()
1838 dev_info(smmu->dev, "event 0x%02x received:\n", id); in arm_smmu_evtq_thread()
1840 dev_info(smmu->dev, "\t0x%016llx\n", in arm_smmu_evtq_thread()
1850 if (queue_sync_prod_in(q) == -EOVERFLOW) in arm_smmu_evtq_thread()
1851 dev_err(smmu->dev, "EVTQ overflow detected -- events lost\n"); in arm_smmu_evtq_thread()
1871 dev_info(smmu->dev, "unexpected PRI request received:\n"); in arm_smmu_handle_ppr()
1872 dev_info(smmu->dev, in arm_smmu_handle_ppr()
1900 struct arm_smmu_queue *q = &smmu->priq.q; in arm_smmu_priq_thread()
1901 struct arm_smmu_ll_queue *llq = &q->llq; in arm_smmu_priq_thread()
1908 if (queue_sync_prod_in(q) == -EOVERFLOW) in arm_smmu_priq_thread()
1909 dev_err(smmu->dev, "PRIQ overflow detected -- requests lost\n"); in arm_smmu_priq_thread()
1924 gerror = readl_relaxed(smmu->base + ARM_SMMU_GERROR); in arm_smmu_gerror_handler()
1925 gerrorn = readl_relaxed(smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1931 dev_warn(smmu->dev, in arm_smmu_gerror_handler()
1936 dev_err(smmu->dev, "device has entered Service Failure Mode!\n"); in arm_smmu_gerror_handler()
1941 dev_warn(smmu->dev, "GERROR MSI write aborted\n"); in arm_smmu_gerror_handler()
1944 dev_warn(smmu->dev, "PRIQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1947 dev_warn(smmu->dev, "EVTQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1950 dev_warn(smmu->dev, "CMDQ MSI write aborted\n"); in arm_smmu_gerror_handler()
1953 dev_err(smmu->dev, "PRIQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1956 dev_err(smmu->dev, "EVTQ write aborted -- events may have been lost\n"); in arm_smmu_gerror_handler()
1961 writel(gerror, smmu->base + ARM_SMMU_GERRORN); in arm_smmu_gerror_handler()
1970 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_combined_irq_thread()
1988 /* ATC invalidates are always on 4096-bytes pages */ in arm_smmu_atc_inv_to_cmd()
2000 * When using STRTAB_STE_1_S1DSS_SSID0 (reserving CD 0 for non-PASID in arm_smmu_atc_inv_to_cmd()
2003 * This has the unpleasant side-effect of invalidating all PASID-tagged in arm_smmu_atc_inv_to_cmd()
2013 cmd->atc.size = ATC_INV_SIZE_ALL; in arm_smmu_atc_inv_to_cmd()
2018 page_end = (iova + size - 1) >> inval_grain_shift; in arm_smmu_atc_inv_to_cmd()
2023 * thus have to choose between grossly over-invalidating the region, or in arm_smmu_atc_inv_to_cmd()
2041 span_mask = (1ULL << log2_span) - 1; in arm_smmu_atc_inv_to_cmd()
2045 cmd->atc.addr = page_start << inval_grain_shift; in arm_smmu_atc_inv_to_cmd()
2046 cmd->atc.size = log2_span; in arm_smmu_atc_inv_to_cmd()
2058 arm_smmu_cmdq_batch_init(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
2059 for (i = 0; i < master->num_streams; i++) { in arm_smmu_atc_inv_master()
2060 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_master()
2061 arm_smmu_cmdq_batch_add(master->smmu, &cmds, &cmd); in arm_smmu_atc_inv_master()
2064 return arm_smmu_cmdq_batch_submit(master->smmu, &cmds); in arm_smmu_atc_inv_master()
2078 if (!(smmu_domain->smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_atc_inv_domain()
2095 if (!atomic_read(&smmu_domain->nr_ats_masters)) in arm_smmu_atc_inv_domain()
2098 arm_smmu_cmdq_batch_init(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
2100 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_atc_inv_domain()
2101 list_for_each_entry(master_domain, &smmu_domain->devices, in arm_smmu_atc_inv_domain()
2103 struct arm_smmu_master *master = master_domain->master; in arm_smmu_atc_inv_domain()
2105 if (!master->ats_enabled) in arm_smmu_atc_inv_domain()
2108 arm_smmu_atc_inv_to_cmd(master_domain->ssid, iova, size, &cmd); in arm_smmu_atc_inv_domain()
2110 for (i = 0; i < master->num_streams; i++) { in arm_smmu_atc_inv_domain()
2111 cmd.atc.sid = master->streams[i].id; in arm_smmu_atc_inv_domain()
2112 arm_smmu_cmdq_batch_add(smmu_domain->smmu, &cmds, &cmd); in arm_smmu_atc_inv_domain()
2115 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_atc_inv_domain()
2117 return arm_smmu_cmdq_batch_submit(smmu_domain->smmu, &cmds); in arm_smmu_atc_inv_domain()
2124 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context()
2128 * NOTE: when io-pgtable is in non-strict mode, we may get here with in arm_smmu_tlb_inv_context()
2134 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_tlb_inv_context()
2135 arm_smmu_tlb_inv_asid(smmu, smmu_domain->cd.asid); in arm_smmu_tlb_inv_context()
2138 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_context()
2149 struct arm_smmu_device *smmu = smmu_domain->smmu; in __arm_smmu_tlb_inv_range()
2157 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
2159 tg = __ffs(smmu_domain->domain.pgsize_bitmap); in __arm_smmu_tlb_inv_range()
2164 cmd->tlbi.tg = (tg - 10) / 2; in __arm_smmu_tlb_inv_range()
2167 * Determine what level the granule is at. For non-leaf, both in __arm_smmu_tlb_inv_range()
2168 * io-pgtable and SVA pass a nominal last-level granule because in __arm_smmu_tlb_inv_range()
2174 if (cmd->tlbi.leaf) in __arm_smmu_tlb_inv_range()
2175 cmd->tlbi.ttl = 4 - ((ilog2(granule) - 3) / (tg - 3)); in __arm_smmu_tlb_inv_range()
2183 if (smmu->features & ARM_SMMU_FEAT_RANGE_INV) { in __arm_smmu_tlb_inv_range()
2195 cmd->tlbi.scale = scale; in __arm_smmu_tlb_inv_range()
2199 cmd->tlbi.num = num - 1; in __arm_smmu_tlb_inv_range()
2205 num_pages -= num << scale; in __arm_smmu_tlb_inv_range()
2208 cmd->tlbi.addr = iova; in __arm_smmu_tlb_inv_range()
2225 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_tlb_inv_range_domain()
2226 cmd.opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_domain()
2228 cmd.tlbi.asid = smmu_domain->cd.asid; in arm_smmu_tlb_inv_range_domain()
2231 cmd.tlbi.vmid = smmu_domain->s2_cfg.vmid; in arm_smmu_tlb_inv_range_domain()
2236 * Unfortunately, this can't be leaf-only since we may have in arm_smmu_tlb_inv_range_domain()
2247 .opcode = smmu_domain->smmu->features & ARM_SMMU_FEAT_E2H ? in arm_smmu_tlb_inv_range_asid()
2263 struct iommu_domain *domain = &smmu_domain->domain; in arm_smmu_tlb_inv_page_nosync()
2284 return (smmu->features & features) == features; in arm_smmu_dbm_capable()
2295 return master->smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_capable()
2300 return arm_smmu_dbm_capable(master->smmu); in arm_smmu_capable()
2312 return ERR_PTR(-ENOMEM); in arm_smmu_domain_alloc()
2314 mutex_init(&smmu_domain->init_mutex); in arm_smmu_domain_alloc()
2315 INIT_LIST_HEAD(&smmu_domain->devices); in arm_smmu_domain_alloc()
2316 spin_lock_init(&smmu_domain->devices_lock); in arm_smmu_domain_alloc()
2338 ret = arm_smmu_domain_finalise(smmu_domain, master->smmu, 0); in arm_smmu_domain_alloc_paging()
2344 return &smmu_domain->domain; in arm_smmu_domain_alloc_paging()
2350 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_domain_free_paging()
2352 free_io_pgtable_ops(smmu_domain->pgtbl_ops); in arm_smmu_domain_free_paging()
2355 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_domain_free_paging()
2358 xa_erase(&arm_smmu_asid_xa, smmu_domain->cd.asid); in arm_smmu_domain_free_paging()
2361 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; in arm_smmu_domain_free_paging()
2362 if (cfg->vmid) in arm_smmu_domain_free_paging()
2363 ida_free(&smmu->vmid_map, cfg->vmid); in arm_smmu_domain_free_paging()
2374 struct arm_smmu_ctx_desc *cd = &smmu_domain->cd; in arm_smmu_domain_finalise_s1()
2379 XA_LIMIT(1, (1 << smmu->asid_bits) - 1), GFP_KERNEL); in arm_smmu_domain_finalise_s1()
2380 cd->asid = (u16)asid; in arm_smmu_domain_finalise_s1()
2389 struct arm_smmu_s2_cfg *cfg = &smmu_domain->s2_cfg; in arm_smmu_domain_finalise_s2()
2391 /* Reserve VMID 0 for stage-2 bypass STEs */ in arm_smmu_domain_finalise_s2()
2392 vmid = ida_alloc_range(&smmu->vmid_map, 1, (1 << smmu->vmid_bits) - 1, in arm_smmu_domain_finalise_s2()
2397 cfg->vmid = (u16)vmid; in arm_smmu_domain_finalise_s2()
2413 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_domain_finalise()
2414 smmu_domain->stage = ARM_SMMU_DOMAIN_S2; in arm_smmu_domain_finalise()
2415 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_domain_finalise()
2416 smmu_domain->stage = ARM_SMMU_DOMAIN_S1; in arm_smmu_domain_finalise()
2419 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_domain_finalise()
2420 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENCY, in arm_smmu_domain_finalise()
2422 .iommu_dev = smmu->dev, in arm_smmu_domain_finalise()
2425 switch (smmu_domain->stage) { in arm_smmu_domain_finalise()
2427 unsigned long ias = (smmu->features & in arm_smmu_domain_finalise()
2431 pgtbl_cfg.oas = smmu->ias; in arm_smmu_domain_finalise()
2440 return -EOPNOTSUPP; in arm_smmu_domain_finalise()
2441 pgtbl_cfg.ias = smmu->ias; in arm_smmu_domain_finalise()
2442 pgtbl_cfg.oas = smmu->oas; in arm_smmu_domain_finalise()
2447 return -EINVAL; in arm_smmu_domain_finalise()
2452 return -ENOMEM; in arm_smmu_domain_finalise()
2454 smmu_domain->domain.pgsize_bitmap = pgtbl_cfg.pgsize_bitmap; in arm_smmu_domain_finalise()
2455 smmu_domain->domain.geometry.aperture_end = (1UL << pgtbl_cfg.ias) - 1; in arm_smmu_domain_finalise()
2456 smmu_domain->domain.geometry.force_aperture = true; in arm_smmu_domain_finalise()
2457 if (enable_dirty && smmu_domain->stage == ARM_SMMU_DOMAIN_S1) in arm_smmu_domain_finalise()
2458 smmu_domain->domain.dirty_ops = &arm_smmu_dirty_ops; in arm_smmu_domain_finalise()
2466 smmu_domain->pgtbl_ops = pgtbl_ops; in arm_smmu_domain_finalise()
2467 smmu_domain->smmu = smmu; in arm_smmu_domain_finalise()
2474 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_get_step_for_sid()
2476 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_get_step_for_sid()
2477 /* Two-level walk */ in arm_smmu_get_step_for_sid()
2478 return &cfg->l2.l2ptrs[arm_smmu_strtab_l1_idx(sid)] in arm_smmu_get_step_for_sid()
2479 ->stes[arm_smmu_strtab_l2_idx(sid)]; in arm_smmu_get_step_for_sid()
2482 return &cfg->linear.table[sid]; in arm_smmu_get_step_for_sid()
2490 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_install_ste_for_dev()
2492 master->cd_table.in_ste = in arm_smmu_install_ste_for_dev()
2493 FIELD_GET(STRTAB_STE_0_CFG, le64_to_cpu(target->data[0])) == in arm_smmu_install_ste_for_dev()
2495 master->ste_ats_enabled = in arm_smmu_install_ste_for_dev()
2496 FIELD_GET(STRTAB_STE_1_EATS, le64_to_cpu(target->data[1])) == in arm_smmu_install_ste_for_dev()
2499 for (i = 0; i < master->num_streams; ++i) { in arm_smmu_install_ste_for_dev()
2500 u32 sid = master->streams[i].id; in arm_smmu_install_ste_for_dev()
2506 if (master->streams[j].id == sid) in arm_smmu_install_ste_for_dev()
2517 struct device *dev = master->dev; in arm_smmu_ats_supported()
2518 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_ats_supported()
2521 if (!(smmu->features & ARM_SMMU_FEAT_ATS)) in arm_smmu_ats_supported()
2524 if (!(fwspec->flags & IOMMU_FWSPEC_PCI_RC_ATS)) in arm_smmu_ats_supported()
2534 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_enable_ats()
2537 stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_enable_ats()
2538 pdev = to_pci_dev(master->dev); in arm_smmu_enable_ats()
2545 dev_err(master->dev, "Failed to enable ATS (STU %zu)\n", stu); in arm_smmu_enable_ats()
2555 if (!dev_is_pci(master->dev)) in arm_smmu_enable_pasid()
2556 return -ENODEV; in arm_smmu_enable_pasid()
2558 pdev = to_pci_dev(master->dev); in arm_smmu_enable_pasid()
2570 dev_err(&pdev->dev, "Failed to enable PASID\n"); in arm_smmu_enable_pasid()
2574 master->ssid_bits = min_t(u8, ilog2(num_pasids), in arm_smmu_enable_pasid()
2575 master->smmu->ssid_bits); in arm_smmu_enable_pasid()
2583 if (!dev_is_pci(master->dev)) in arm_smmu_disable_pasid()
2586 pdev = to_pci_dev(master->dev); in arm_smmu_disable_pasid()
2588 if (!pdev->pasid_enabled) in arm_smmu_disable_pasid()
2591 master->ssid_bits = 0; in arm_smmu_disable_pasid()
2602 lockdep_assert_held(&smmu_domain->devices_lock); in arm_smmu_find_master_domain()
2604 list_for_each_entry(master_domain, &smmu_domain->devices, in arm_smmu_find_master_domain()
2606 if (master_domain->master == master && in arm_smmu_find_master_domain()
2607 master_domain->ssid == ssid) in arm_smmu_find_master_domain()
2614 * If the domain uses the smmu_domain->devices list return the arm_smmu_domain
2624 if ((domain->type & __IOMMU_DOMAIN_PAGING) || in to_smmu_domain_devices()
2625 domain->type == IOMMU_DOMAIN_SVA) in to_smmu_domain_devices()
2641 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_remove_master_domain()
2644 list_del(&master_domain->devices_elm); in arm_smmu_remove_master_domain()
2646 if (master->ats_enabled) in arm_smmu_remove_master_domain()
2647 atomic_dec(&smmu_domain->nr_ats_masters); in arm_smmu_remove_master_domain()
2649 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_remove_master_domain()
2679 * new_domain can be a non-paging domain. In this case ATS will not be enabled,
2685 struct arm_smmu_master *master = state->master; in arm_smmu_attach_prepare()
2698 if (smmu_domain || state->cd_needs_ats) { in arm_smmu_attach_prepare()
2709 state->ats_enabled = arm_smmu_ats_supported(master); in arm_smmu_attach_prepare()
2715 return -ENOMEM; in arm_smmu_attach_prepare()
2716 master_domain->master = master; in arm_smmu_attach_prepare()
2717 master_domain->ssid = state->ssid; in arm_smmu_attach_prepare()
2729 * Notice if we are re-attaching the same domain then the list in arm_smmu_attach_prepare()
2733 spin_lock_irqsave(&smmu_domain->devices_lock, flags); in arm_smmu_attach_prepare()
2734 if (state->ats_enabled) in arm_smmu_attach_prepare()
2735 atomic_inc(&smmu_domain->nr_ats_masters); in arm_smmu_attach_prepare()
2736 list_add(&master_domain->devices_elm, &smmu_domain->devices); in arm_smmu_attach_prepare()
2737 spin_unlock_irqrestore(&smmu_domain->devices_lock, flags); in arm_smmu_attach_prepare()
2740 if (!state->ats_enabled && master->ats_enabled) { in arm_smmu_attach_prepare()
2741 pci_disable_ats(to_pci_dev(master->dev)); in arm_smmu_attach_prepare()
2755 * smmu_domain->devices list.
2759 struct arm_smmu_master *master = state->master; in arm_smmu_attach_commit()
2763 if (state->ats_enabled && !master->ats_enabled) { in arm_smmu_attach_commit()
2765 } else if (state->ats_enabled && master->ats_enabled) { in arm_smmu_attach_commit()
2771 arm_smmu_atc_inv_master(master, state->ssid); in arm_smmu_attach_commit()
2772 } else if (!state->ats_enabled && master->ats_enabled) { in arm_smmu_attach_commit()
2776 master->ats_enabled = state->ats_enabled; in arm_smmu_attach_commit()
2778 arm_smmu_remove_master_domain(master, state->old_domain, state->ssid); in arm_smmu_attach_commit()
2796 return -ENOENT; in arm_smmu_attach_dev()
2799 smmu = master->smmu; in arm_smmu_attach_dev()
2801 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_attach_dev()
2803 if (!smmu_domain->smmu) { in arm_smmu_attach_dev()
2805 } else if (smmu_domain->smmu != smmu) in arm_smmu_attach_dev()
2806 ret = -EINVAL; in arm_smmu_attach_dev()
2808 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_attach_dev()
2812 if (smmu_domain->stage == ARM_SMMU_DOMAIN_S1) { in arm_smmu_attach_dev()
2815 return -ENOMEM; in arm_smmu_attach_dev()
2816 } else if (arm_smmu_ssids_in_use(&master->cd_table)) in arm_smmu_attach_dev()
2817 return -EBUSY; in arm_smmu_attach_dev()
2822 * This allows the STE and the smmu_domain->devices list to in arm_smmu_attach_dev()
2833 switch (smmu_domain->stage) { in arm_smmu_attach_dev()
2863 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_s1_set_dev_pasid()
2867 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_s1_set_dev_pasid()
2868 if (!smmu_domain->smmu) in arm_smmu_s1_set_dev_pasid()
2870 else if (smmu_domain->smmu != smmu) in arm_smmu_s1_set_dev_pasid()
2871 ret = -EINVAL; in arm_smmu_s1_set_dev_pasid()
2872 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_s1_set_dev_pasid()
2876 if (smmu_domain->stage != ARM_SMMU_DOMAIN_S1) in arm_smmu_s1_set_dev_pasid()
2877 return -EINVAL; in arm_smmu_s1_set_dev_pasid()
2895 if (master->cd_table.in_ste && master->ste_ats_enabled == ats_enabled) in arm_smmu_update_ste()
2898 if (sid_domain->type == IOMMU_DOMAIN_IDENTITY) in arm_smmu_update_ste()
2901 WARN_ON(sid_domain->type != IOMMU_DOMAIN_BLOCKED); in arm_smmu_update_ste()
2917 struct iommu_domain *sid_domain = iommu_get_domain_for_dev(master->dev); in arm_smmu_set_pasid()
2931 if (smmu_domain->smmu != master->smmu) in arm_smmu_set_pasid()
2932 return -EINVAL; in arm_smmu_set_pasid()
2934 if (!master->cd_table.in_ste && in arm_smmu_set_pasid()
2935 sid_domain->type != IOMMU_DOMAIN_IDENTITY && in arm_smmu_set_pasid()
2936 sid_domain->type != IOMMU_DOMAIN_BLOCKED) in arm_smmu_set_pasid()
2937 return -EINVAL; in arm_smmu_set_pasid()
2941 return -ENOMEM; in arm_smmu_set_pasid()
2944 ret = arm_smmu_attach_prepare(&state, &smmu_domain->domain); in arm_smmu_set_pasid()
2952 cd->data[0] &= ~cpu_to_le64(CTXDESC_CD_0_ASID); in arm_smmu_set_pasid()
2953 cd->data[0] |= cpu_to_le64( in arm_smmu_set_pasid()
2954 FIELD_PREP(CTXDESC_CD_0_ASID, smmu_domain->cd.asid)); in arm_smmu_set_pasid()
2976 if (master->ats_enabled) in arm_smmu_remove_dev_pasid()
2978 arm_smmu_remove_master_domain(master, &smmu_domain->domain, pasid); in arm_smmu_remove_dev_pasid()
2983 * to a non-cd_table one. in arm_smmu_remove_dev_pasid()
2985 if (!arm_smmu_ssids_in_use(&master->cd_table)) { in arm_smmu_remove_dev_pasid()
2987 iommu_get_domain_for_dev(master->dev); in arm_smmu_remove_dev_pasid()
2989 if (sid_domain->type == IOMMU_DOMAIN_IDENTITY || in arm_smmu_remove_dev_pasid()
2990 sid_domain->type == IOMMU_DOMAIN_BLOCKED) in arm_smmu_remove_dev_pasid()
2991 sid_domain->ops->attach_dev(sid_domain, dev); in arm_smmu_remove_dev_pasid()
3017 if (arm_smmu_ssids_in_use(&master->cd_table)) { in arm_smmu_attach_dev_ste()
3035 * arm_smmu_domain->devices to avoid races updating the same context in arm_smmu_attach_dev_ste()
3047 arm_smmu_make_bypass_ste(master->smmu, &ste); in arm_smmu_attach_dev_identity()
3092 return ERR_PTR(-EOPNOTSUPP); in arm_smmu_domain_alloc_user()
3094 return ERR_PTR(-EOPNOTSUPP); in arm_smmu_domain_alloc_user()
3100 smmu_domain->domain.type = IOMMU_DOMAIN_UNMANAGED; in arm_smmu_domain_alloc_user()
3101 smmu_domain->domain.ops = arm_smmu_ops.default_domain_ops; in arm_smmu_domain_alloc_user()
3102 ret = arm_smmu_domain_finalise(smmu_domain, master->smmu, flags); in arm_smmu_domain_alloc_user()
3105 return &smmu_domain->domain; in arm_smmu_domain_alloc_user()
3116 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_map_pages()
3119 return -ENODEV; in arm_smmu_map_pages()
3121 return ops->map_pages(ops, iova, paddr, pgsize, pgcount, prot, gfp, mapped); in arm_smmu_map_pages()
3129 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; in arm_smmu_unmap_pages()
3134 return ops->unmap_pages(ops, iova, pgsize, pgcount, gather); in arm_smmu_unmap_pages()
3141 if (smmu_domain->smmu) in arm_smmu_flush_iotlb_all()
3150 if (!gather->pgsize) in arm_smmu_iotlb_sync()
3153 arm_smmu_tlb_inv_range_domain(gather->start, in arm_smmu_iotlb_sync()
3154 gather->end - gather->start + 1, in arm_smmu_iotlb_sync()
3155 gather->pgsize, true, smmu_domain); in arm_smmu_iotlb_sync()
3161 struct io_pgtable_ops *ops = to_smmu_domain(domain)->pgtbl_ops; in arm_smmu_iova_to_phys()
3166 return ops->iova_to_phys(ops, iova); in arm_smmu_iova_to_phys()
3182 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_sid_in_range()
3183 return arm_smmu_strtab_l1_idx(sid) < smmu->strtab_cfg.l2.num_l1_ents; in arm_smmu_sid_in_range()
3184 return sid < smmu->strtab_cfg.linear.num_ents; in arm_smmu_sid_in_range()
3191 return -ERANGE; in arm_smmu_init_sid_strtab()
3194 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_sid_strtab()
3205 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); in arm_smmu_insert_master()
3207 master->streams = kcalloc(fwspec->num_ids, sizeof(*master->streams), in arm_smmu_insert_master()
3209 if (!master->streams) in arm_smmu_insert_master()
3210 return -ENOMEM; in arm_smmu_insert_master()
3211 master->num_streams = fwspec->num_ids; in arm_smmu_insert_master()
3213 mutex_lock(&smmu->streams_mutex); in arm_smmu_insert_master()
3214 for (i = 0; i < fwspec->num_ids; i++) { in arm_smmu_insert_master()
3215 struct arm_smmu_stream *new_stream = &master->streams[i]; in arm_smmu_insert_master()
3216 u32 sid = fwspec->ids[i]; in arm_smmu_insert_master()
3218 new_stream->id = sid; in arm_smmu_insert_master()
3219 new_stream->master = master; in arm_smmu_insert_master()
3226 if (rb_find_add(&new_stream->node, &smmu->streams, in arm_smmu_insert_master()
3228 dev_warn(master->dev, "stream %u already in tree\n", in arm_smmu_insert_master()
3230 ret = -EINVAL; in arm_smmu_insert_master()
3236 for (i--; i >= 0; i--) in arm_smmu_insert_master()
3237 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_insert_master()
3238 kfree(master->streams); in arm_smmu_insert_master()
3240 mutex_unlock(&smmu->streams_mutex); in arm_smmu_insert_master()
3248 struct arm_smmu_device *smmu = master->smmu; in arm_smmu_remove_master()
3249 struct iommu_fwspec *fwspec = dev_iommu_fwspec_get(master->dev); in arm_smmu_remove_master()
3251 if (!smmu || !master->streams) in arm_smmu_remove_master()
3254 mutex_lock(&smmu->streams_mutex); in arm_smmu_remove_master()
3255 for (i = 0; i < fwspec->num_ids; i++) in arm_smmu_remove_master()
3256 rb_erase(&master->streams[i].node, &smmu->streams); in arm_smmu_remove_master()
3257 mutex_unlock(&smmu->streams_mutex); in arm_smmu_remove_master()
3259 kfree(master->streams); in arm_smmu_remove_master()
3270 return ERR_PTR(-EBUSY); in arm_smmu_probe_device()
3272 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
3274 return ERR_PTR(-ENODEV); in arm_smmu_probe_device()
3278 return ERR_PTR(-ENOMEM); in arm_smmu_probe_device()
3280 master->dev = dev; in arm_smmu_probe_device()
3281 master->smmu = smmu; in arm_smmu_probe_device()
3288 device_property_read_u32(dev, "pasid-num-bits", &master->ssid_bits); in arm_smmu_probe_device()
3289 master->ssid_bits = min(smmu->ssid_bits, master->ssid_bits); in arm_smmu_probe_device()
3293 * PCI Express Base 4.0r1.0 - 10.5.1.3 ATS Control Register in arm_smmu_probe_device()
3301 if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_CDTAB)) in arm_smmu_probe_device()
3302 master->ssid_bits = min_t(u8, master->ssid_bits, in arm_smmu_probe_device()
3305 if ((smmu->features & ARM_SMMU_FEAT_STALLS && in arm_smmu_probe_device()
3306 device_property_read_bool(dev, "dma-can-stall")) || in arm_smmu_probe_device()
3307 smmu->features & ARM_SMMU_FEAT_STALL_FORCE) in arm_smmu_probe_device()
3308 master->stall_enabled = true; in arm_smmu_probe_device()
3311 unsigned int stu = __ffs(smmu->pgsize_bitmap); in arm_smmu_probe_device()
3316 return &smmu->iommu; in arm_smmu_probe_device()
3328 iopf_queue_remove_device(master->smmu->evtq.iopf, dev); in arm_smmu_release_device()
3331 if (dev->iommu->require_direct) in arm_smmu_release_device()
3338 if (arm_smmu_cdtab_allocated(&master->cd_table)) in arm_smmu_release_device()
3349 struct io_pgtable_ops *ops = smmu_domain->pgtbl_ops; in arm_smmu_read_and_clear_dirty()
3351 return ops->read_and_clear_dirty(ops, iova, size, flags, dirty); in arm_smmu_read_and_clear_dirty()
3370 * aliases, since the necessary ID-to-device lookup becomes rather in arm_smmu_device_group()
3371 * impractical given a potential sparse 32-bit stream ID space. in arm_smmu_device_group()
3386 mutex_lock(&smmu_domain->init_mutex); in arm_smmu_enable_nesting()
3387 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
3388 ret = -EPERM; in arm_smmu_enable_nesting()
3390 smmu_domain->stage = ARM_SMMU_DOMAIN_S2; in arm_smmu_enable_nesting()
3391 mutex_unlock(&smmu_domain->init_mutex); in arm_smmu_enable_nesting()
3399 return iommu_fwspec_add_ids(dev, args->args, 1); in arm_smmu_of_xlate()
3413 list_add_tail(®ion->list, head); in arm_smmu_get_resv_regions()
3424 return -ENODEV; in arm_smmu_dev_enable_feature()
3429 return -EINVAL; in arm_smmu_dev_enable_feature()
3430 if (master->iopf_enabled) in arm_smmu_dev_enable_feature()
3431 return -EBUSY; in arm_smmu_dev_enable_feature()
3432 master->iopf_enabled = true; in arm_smmu_dev_enable_feature()
3436 return -EINVAL; in arm_smmu_dev_enable_feature()
3438 return -EBUSY; in arm_smmu_dev_enable_feature()
3441 return -EINVAL; in arm_smmu_dev_enable_feature()
3451 return -EINVAL; in arm_smmu_dev_disable_feature()
3455 if (!master->iopf_enabled) in arm_smmu_dev_disable_feature()
3456 return -EINVAL; in arm_smmu_dev_disable_feature()
3457 if (master->sva_enabled) in arm_smmu_dev_disable_feature()
3458 return -EBUSY; in arm_smmu_dev_disable_feature()
3459 master->iopf_enabled = false; in arm_smmu_dev_disable_feature()
3463 return -EINVAL; in arm_smmu_dev_disable_feature()
3466 return -EINVAL; in arm_smmu_dev_disable_feature()
3475 #define IS_HISI_PTT_DEVICE(pdev) ((pdev)->vendor == PCI_VENDOR_ID_HUAWEI && \
3476 (pdev)->device == 0xa12e)
3507 .pgsize_bitmap = -1UL, /* Restricted during device attach */
3536 qsz = ((1 << q->llq.max_n_shift) * dwords) << 3; in arm_smmu_init_one_queue()
3537 q->base = dmam_alloc_coherent(smmu->dev, qsz, &q->base_dma, in arm_smmu_init_one_queue()
3539 if (q->base || qsz < PAGE_SIZE) in arm_smmu_init_one_queue()
3542 q->llq.max_n_shift--; in arm_smmu_init_one_queue()
3545 if (!q->base) { in arm_smmu_init_one_queue()
3546 dev_err(smmu->dev, in arm_smmu_init_one_queue()
3549 return -ENOMEM; in arm_smmu_init_one_queue()
3552 if (!WARN_ON(q->base_dma & (qsz - 1))) { in arm_smmu_init_one_queue()
3553 dev_info(smmu->dev, "allocated %u entries for %s\n", in arm_smmu_init_one_queue()
3554 1 << q->llq.max_n_shift, name); in arm_smmu_init_one_queue()
3557 q->prod_reg = page + prod_off; in arm_smmu_init_one_queue()
3558 q->cons_reg = page + cons_off; in arm_smmu_init_one_queue()
3559 q->ent_dwords = dwords; in arm_smmu_init_one_queue()
3561 q->q_base = Q_BASE_RWA; in arm_smmu_init_one_queue()
3562 q->q_base |= q->base_dma & Q_BASE_ADDR_MASK; in arm_smmu_init_one_queue()
3563 q->q_base |= FIELD_PREP(Q_BASE_LOG2SIZE, q->llq.max_n_shift); in arm_smmu_init_one_queue()
3565 q->llq.prod = q->llq.cons = 0; in arm_smmu_init_one_queue()
3572 unsigned int nents = 1 << cmdq->q.llq.max_n_shift; in arm_smmu_cmdq_init()
3574 atomic_set(&cmdq->owner_prod, 0); in arm_smmu_cmdq_init()
3575 atomic_set(&cmdq->lock, 0); in arm_smmu_cmdq_init()
3577 cmdq->valid_map = (atomic_long_t *)devm_bitmap_zalloc(smmu->dev, nents, in arm_smmu_cmdq_init()
3579 if (!cmdq->valid_map) in arm_smmu_cmdq_init()
3580 return -ENOMEM; in arm_smmu_cmdq_init()
3590 ret = arm_smmu_init_one_queue(smmu, &smmu->cmdq.q, smmu->base, in arm_smmu_init_queues()
3596 ret = arm_smmu_cmdq_init(smmu, &smmu->cmdq); in arm_smmu_init_queues()
3601 ret = arm_smmu_init_one_queue(smmu, &smmu->evtq.q, smmu->page1, in arm_smmu_init_queues()
3607 if ((smmu->features & ARM_SMMU_FEAT_SVA) && in arm_smmu_init_queues()
3608 (smmu->features & ARM_SMMU_FEAT_STALLS)) { in arm_smmu_init_queues()
3609 smmu->evtq.iopf = iopf_queue_alloc(dev_name(smmu->dev)); in arm_smmu_init_queues()
3610 if (!smmu->evtq.iopf) in arm_smmu_init_queues()
3611 return -ENOMEM; in arm_smmu_init_queues()
3615 if (!(smmu->features & ARM_SMMU_FEAT_PRI)) in arm_smmu_init_queues()
3618 return arm_smmu_init_one_queue(smmu, &smmu->priq.q, smmu->page1, in arm_smmu_init_queues()
3626 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_2lvl()
3628 arm_smmu_strtab_l1_idx((1ULL << smmu->sid_bits) - 1); in arm_smmu_init_strtab_2lvl()
3631 cfg->l2.num_l1_ents = min(last_sid_idx + 1, STRTAB_MAX_L1_ENTRIES); in arm_smmu_init_strtab_2lvl()
3632 if (cfg->l2.num_l1_ents <= last_sid_idx) in arm_smmu_init_strtab_2lvl()
3633 dev_warn(smmu->dev, in arm_smmu_init_strtab_2lvl()
3634 "2-level strtab only covers %u/%u bits of SID\n", in arm_smmu_init_strtab_2lvl()
3635 ilog2(cfg->l2.num_l1_ents * STRTAB_NUM_L2_STES), in arm_smmu_init_strtab_2lvl()
3636 smmu->sid_bits); in arm_smmu_init_strtab_2lvl()
3638 l1size = cfg->l2.num_l1_ents * sizeof(struct arm_smmu_strtab_l1); in arm_smmu_init_strtab_2lvl()
3639 cfg->l2.l1tab = dmam_alloc_coherent(smmu->dev, l1size, &cfg->l2.l1_dma, in arm_smmu_init_strtab_2lvl()
3641 if (!cfg->l2.l1tab) { in arm_smmu_init_strtab_2lvl()
3642 dev_err(smmu->dev, in arm_smmu_init_strtab_2lvl()
3645 return -ENOMEM; in arm_smmu_init_strtab_2lvl()
3648 cfg->l2.l2ptrs = devm_kcalloc(smmu->dev, cfg->l2.num_l1_ents, in arm_smmu_init_strtab_2lvl()
3649 sizeof(*cfg->l2.l2ptrs), GFP_KERNEL); in arm_smmu_init_strtab_2lvl()
3650 if (!cfg->l2.l2ptrs) in arm_smmu_init_strtab_2lvl()
3651 return -ENOMEM; in arm_smmu_init_strtab_2lvl()
3659 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_init_strtab_linear()
3661 size = (1 << smmu->sid_bits) * sizeof(struct arm_smmu_ste); in arm_smmu_init_strtab_linear()
3662 cfg->linear.table = dmam_alloc_coherent(smmu->dev, size, in arm_smmu_init_strtab_linear()
3663 &cfg->linear.ste_dma, in arm_smmu_init_strtab_linear()
3665 if (!cfg->linear.table) { in arm_smmu_init_strtab_linear()
3666 dev_err(smmu->dev, in arm_smmu_init_strtab_linear()
3669 return -ENOMEM; in arm_smmu_init_strtab_linear()
3671 cfg->linear.num_ents = 1 << smmu->sid_bits; in arm_smmu_init_strtab_linear()
3673 arm_smmu_init_initial_stes(cfg->linear.table, cfg->linear.num_ents); in arm_smmu_init_strtab_linear()
3681 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) in arm_smmu_init_strtab()
3688 ida_init(&smmu->vmid_map); in arm_smmu_init_strtab()
3697 mutex_init(&smmu->streams_mutex); in arm_smmu_init_structures()
3698 smmu->streams = RB_ROOT; in arm_smmu_init_structures()
3708 if (smmu->impl_ops && smmu->impl_ops->init_structures) in arm_smmu_init_structures()
3709 return smmu->impl_ops->init_structures(smmu); in arm_smmu_init_structures()
3719 writel_relaxed(val, smmu->base + reg_off); in arm_smmu_write_reg_sync()
3720 return readl_relaxed_poll_timeout(smmu->base + ack_off, reg, reg == val, in arm_smmu_write_reg_sync()
3728 u32 reg, __iomem *gbpa = smmu->base + ARM_SMMU_GBPA; in arm_smmu_update_gbpa()
3742 dev_err(smmu->dev, "GBPA not responding to update\n"); in arm_smmu_update_gbpa()
3758 phys_addr_t *cfg = arm_smmu_msi_cfg[desc->msi_index]; in arm_smmu_write_msi_msg()
3760 doorbell = (((u64)msg->address_hi) << 32) | msg->address_lo; in arm_smmu_write_msi_msg()
3763 writeq_relaxed(doorbell, smmu->base + cfg[0]); in arm_smmu_write_msi_msg()
3764 writel_relaxed(msg->data, smmu->base + cfg[1]); in arm_smmu_write_msi_msg()
3765 writel_relaxed(ARM_SMMU_MEMATTR_DEVICE_nGnRE, smmu->base + cfg[2]); in arm_smmu_write_msi_msg()
3771 struct device *dev = smmu->dev; in arm_smmu_setup_msis()
3774 writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); in arm_smmu_setup_msis()
3775 writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); in arm_smmu_setup_msis()
3777 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_msis()
3778 writeq_relaxed(0, smmu->base + ARM_SMMU_PRIQ_IRQ_CFG0); in arm_smmu_setup_msis()
3780 nvec--; in arm_smmu_setup_msis()
3782 if (!(smmu->features & ARM_SMMU_FEAT_MSI)) in arm_smmu_setup_msis()
3785 if (!dev->msi.domain) { in arm_smmu_setup_msis()
3786 dev_info(smmu->dev, "msi_domain absent - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3793 dev_warn(dev, "failed to allocate MSIs - falling back to wired irqs\n"); in arm_smmu_setup_msis()
3797 smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); in arm_smmu_setup_msis()
3798 smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); in arm_smmu_setup_msis()
3799 smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); in arm_smmu_setup_msis()
3812 irq = smmu->evtq.q.irq; in arm_smmu_setup_unique_irqs()
3814 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3817 "arm-smmu-v3-evtq", smmu); in arm_smmu_setup_unique_irqs()
3819 dev_warn(smmu->dev, "failed to enable evtq irq\n"); in arm_smmu_setup_unique_irqs()
3821 dev_warn(smmu->dev, "no evtq irq - events will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3824 irq = smmu->gerr_irq; in arm_smmu_setup_unique_irqs()
3826 ret = devm_request_irq(smmu->dev, irq, arm_smmu_gerror_handler, in arm_smmu_setup_unique_irqs()
3827 0, "arm-smmu-v3-gerror", smmu); in arm_smmu_setup_unique_irqs()
3829 dev_warn(smmu->dev, "failed to enable gerror irq\n"); in arm_smmu_setup_unique_irqs()
3831 dev_warn(smmu->dev, "no gerr irq - errors will not be reported!\n"); in arm_smmu_setup_unique_irqs()
3834 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_setup_unique_irqs()
3835 irq = smmu->priq.q.irq; in arm_smmu_setup_unique_irqs()
3837 ret = devm_request_threaded_irq(smmu->dev, irq, NULL, in arm_smmu_setup_unique_irqs()
3840 "arm-smmu-v3-priq", in arm_smmu_setup_unique_irqs()
3843 dev_warn(smmu->dev, in arm_smmu_setup_unique_irqs()
3846 dev_warn(smmu->dev, "no priq irq - PRI will be broken\n"); in arm_smmu_setup_unique_irqs()
3860 dev_err(smmu->dev, "failed to disable irqs\n"); in arm_smmu_setup_irqs()
3864 irq = smmu->combined_irq; in arm_smmu_setup_irqs()
3870 ret = devm_request_threaded_irq(smmu->dev, irq, in arm_smmu_setup_irqs()
3874 "arm-smmu-v3-combined-irq", smmu); in arm_smmu_setup_irqs()
3876 dev_warn(smmu->dev, "failed to enable combined irq\n"); in arm_smmu_setup_irqs()
3880 if (smmu->features & ARM_SMMU_FEAT_PRI) in arm_smmu_setup_irqs()
3887 dev_warn(smmu->dev, "failed to enable irqs\n"); in arm_smmu_setup_irqs()
3898 dev_err(smmu->dev, "failed to clear cr0\n"); in arm_smmu_device_disable()
3905 struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; in arm_smmu_write_strtab()
3909 if (smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB) { in arm_smmu_write_strtab()
3913 ilog2(cfg->l2.num_l1_ents) + STRTAB_SPLIT) | in arm_smmu_write_strtab()
3915 dma = cfg->l2.l1_dma; in arm_smmu_write_strtab()
3919 FIELD_PREP(STRTAB_BASE_CFG_LOG2SIZE, smmu->sid_bits); in arm_smmu_write_strtab()
3920 dma = cfg->linear.ste_dma; in arm_smmu_write_strtab()
3923 smmu->base + ARM_SMMU_STRTAB_BASE); in arm_smmu_write_strtab()
3924 writel_relaxed(reg, smmu->base + ARM_SMMU_STRTAB_BASE_CFG); in arm_smmu_write_strtab()
3934 reg = readl_relaxed(smmu->base + ARM_SMMU_CR0); in arm_smmu_device_reset()
3936 dev_warn(smmu->dev, "SMMU currently enabled! Resetting...\n"); in arm_smmu_device_reset()
3951 writel_relaxed(reg, smmu->base + ARM_SMMU_CR1); in arm_smmu_device_reset()
3956 if (smmu->features & ARM_SMMU_FEAT_E2H) in arm_smmu_device_reset()
3959 writel_relaxed(reg, smmu->base + ARM_SMMU_CR2); in arm_smmu_device_reset()
3965 writeq_relaxed(smmu->cmdq.q.q_base, smmu->base + ARM_SMMU_CMDQ_BASE); in arm_smmu_device_reset()
3966 writel_relaxed(smmu->cmdq.q.llq.prod, smmu->base + ARM_SMMU_CMDQ_PROD); in arm_smmu_device_reset()
3967 writel_relaxed(smmu->cmdq.q.llq.cons, smmu->base + ARM_SMMU_CMDQ_CONS); in arm_smmu_device_reset()
3973 dev_err(smmu->dev, "failed to enable command queue\n"); in arm_smmu_device_reset()
3982 if (smmu->features & ARM_SMMU_FEAT_HYP) { in arm_smmu_device_reset()
3991 writeq_relaxed(smmu->evtq.q.q_base, smmu->base + ARM_SMMU_EVTQ_BASE); in arm_smmu_device_reset()
3992 writel_relaxed(smmu->evtq.q.llq.prod, smmu->page1 + ARM_SMMU_EVTQ_PROD); in arm_smmu_device_reset()
3993 writel_relaxed(smmu->evtq.q.llq.cons, smmu->page1 + ARM_SMMU_EVTQ_CONS); in arm_smmu_device_reset()
3999 dev_err(smmu->dev, "failed to enable event queue\n"); in arm_smmu_device_reset()
4004 if (smmu->features & ARM_SMMU_FEAT_PRI) { in arm_smmu_device_reset()
4005 writeq_relaxed(smmu->priq.q.q_base, in arm_smmu_device_reset()
4006 smmu->base + ARM_SMMU_PRIQ_BASE); in arm_smmu_device_reset()
4007 writel_relaxed(smmu->priq.q.llq.prod, in arm_smmu_device_reset()
4008 smmu->page1 + ARM_SMMU_PRIQ_PROD); in arm_smmu_device_reset()
4009 writel_relaxed(smmu->priq.q.llq.cons, in arm_smmu_device_reset()
4010 smmu->page1 + ARM_SMMU_PRIQ_CONS); in arm_smmu_device_reset()
4016 dev_err(smmu->dev, "failed to enable PRI queue\n"); in arm_smmu_device_reset()
4021 if (smmu->features & ARM_SMMU_FEAT_ATS) { in arm_smmu_device_reset()
4026 dev_err(smmu->dev, "failed to enable ATS check\n"); in arm_smmu_device_reset()
4033 dev_err(smmu->dev, "failed to setup irqs\n"); in arm_smmu_device_reset()
4045 dev_err(smmu->dev, "failed to enable SMMU interface\n"); in arm_smmu_device_reset()
4049 if (smmu->impl_ops && smmu->impl_ops->device_reset) { in arm_smmu_device_reset()
4050 ret = smmu->impl_ops->device_reset(smmu); in arm_smmu_device_reset()
4052 dev_err(smmu->dev, "failed to reset impl\n"); in arm_smmu_device_reset()
4069 reg = readl_relaxed(smmu->base + ARM_SMMU_IIDR); in arm_smmu_device_iidr_probe()
4081 smmu->features &= ~ARM_SMMU_FEAT_SEV; in arm_smmu_device_iidr_probe()
4084 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
4088 smmu->features &= ~ARM_SMMU_FEAT_BTM; in arm_smmu_device_iidr_probe()
4089 smmu->options |= ARM_SMMU_OPT_CMDQ_FORCE_SYNC; in arm_smmu_device_iidr_probe()
4091 smmu->features &= ~ARM_SMMU_FEAT_NESTING; in arm_smmu_device_iidr_probe()
4100 u32 fw_features = smmu->features & (ARM_SMMU_FEAT_HA | ARM_SMMU_FEAT_HD); in arm_smmu_get_httu()
4111 if (smmu->dev->of_node) in arm_smmu_get_httu()
4112 smmu->features |= hw_features; in arm_smmu_get_httu()
4115 dev_warn(smmu->dev, in arm_smmu_get_httu()
4123 bool coherent = smmu->features & ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_hw_probe()
4126 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR0); in arm_smmu_device_hw_probe()
4128 /* 2-level structures */ in arm_smmu_device_hw_probe()
4130 smmu->features |= ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
4133 smmu->features |= ARM_SMMU_FEAT_2_LVL_CDTAB; in arm_smmu_device_hw_probe()
4142 smmu->features |= ARM_SMMU_FEAT_TT_LE | ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
4146 smmu->features |= ARM_SMMU_FEAT_TT_BE; in arm_smmu_device_hw_probe()
4150 smmu->features |= ARM_SMMU_FEAT_TT_LE; in arm_smmu_device_hw_probe()
4154 dev_err(smmu->dev, "unknown/unsupported TT endianness!\n"); in arm_smmu_device_hw_probe()
4155 return -ENXIO; in arm_smmu_device_hw_probe()
4160 smmu->features |= ARM_SMMU_FEAT_PRI; in arm_smmu_device_hw_probe()
4163 smmu->features |= ARM_SMMU_FEAT_ATS; in arm_smmu_device_hw_probe()
4166 smmu->features |= ARM_SMMU_FEAT_SEV; in arm_smmu_device_hw_probe()
4169 smmu->features |= ARM_SMMU_FEAT_MSI; in arm_smmu_device_hw_probe()
4171 smmu->options |= ARM_SMMU_OPT_MSIPOLL; in arm_smmu_device_hw_probe()
4175 smmu->features |= ARM_SMMU_FEAT_HYP; in arm_smmu_device_hw_probe()
4177 smmu->features |= ARM_SMMU_FEAT_E2H; in arm_smmu_device_hw_probe()
4187 dev_warn(smmu->dev, "IDR0.COHACC overridden by FW configuration (%s)\n", in arm_smmu_device_hw_probe()
4192 smmu->features |= ARM_SMMU_FEAT_STALL_FORCE; in arm_smmu_device_hw_probe()
4195 smmu->features |= ARM_SMMU_FEAT_STALLS; in arm_smmu_device_hw_probe()
4199 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_hw_probe()
4202 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_hw_probe()
4205 dev_err(smmu->dev, "no translation support!\n"); in arm_smmu_device_hw_probe()
4206 return -ENXIO; in arm_smmu_device_hw_probe()
4212 smmu->ias = 40; in arm_smmu_device_hw_probe()
4217 dev_err(smmu->dev, "AArch64 table format not supported!\n"); in arm_smmu_device_hw_probe()
4218 return -ENXIO; in arm_smmu_device_hw_probe()
4222 smmu->asid_bits = reg & IDR0_ASID16 ? 16 : 8; in arm_smmu_device_hw_probe()
4223 smmu->vmid_bits = reg & IDR0_VMID16 ? 16 : 8; in arm_smmu_device_hw_probe()
4226 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR1); in arm_smmu_device_hw_probe()
4228 dev_err(smmu->dev, "embedded implementation not supported\n"); in arm_smmu_device_hw_probe()
4229 return -ENXIO; in arm_smmu_device_hw_probe()
4233 smmu->features |= ARM_SMMU_FEAT_ATTR_TYPES_OVR; in arm_smmu_device_hw_probe()
4236 smmu->cmdq.q.llq.max_n_shift = min_t(u32, CMDQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4238 if (smmu->cmdq.q.llq.max_n_shift <= ilog2(CMDQ_BATCH_ENTRIES)) { in arm_smmu_device_hw_probe()
4243 * restrictions on the base pointer for a unit-length queue. in arm_smmu_device_hw_probe()
4245 dev_err(smmu->dev, "command queue size <= %d entries not supported\n", in arm_smmu_device_hw_probe()
4247 return -ENXIO; in arm_smmu_device_hw_probe()
4250 smmu->evtq.q.llq.max_n_shift = min_t(u32, EVTQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4252 smmu->priq.q.llq.max_n_shift = min_t(u32, PRIQ_MAX_SZ_SHIFT, in arm_smmu_device_hw_probe()
4256 smmu->ssid_bits = FIELD_GET(IDR1_SSIDSIZE, reg); in arm_smmu_device_hw_probe()
4257 smmu->sid_bits = FIELD_GET(IDR1_SIDSIZE, reg); in arm_smmu_device_hw_probe()
4258 smmu->iommu.max_pasids = 1UL << smmu->ssid_bits; in arm_smmu_device_hw_probe()
4264 if (smmu->sid_bits <= STRTAB_SPLIT) in arm_smmu_device_hw_probe()
4265 smmu->features &= ~ARM_SMMU_FEAT_2_LVL_STRTAB; in arm_smmu_device_hw_probe()
4268 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR3); in arm_smmu_device_hw_probe()
4270 smmu->features |= ARM_SMMU_FEAT_RANGE_INV; in arm_smmu_device_hw_probe()
4273 reg = readl_relaxed(smmu->base + ARM_SMMU_IDR5); in arm_smmu_device_hw_probe()
4276 smmu->evtq.max_stalls = FIELD_GET(IDR5_STALL_MAX, reg); in arm_smmu_device_hw_probe()
4280 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_hw_probe()
4282 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_hw_probe()
4284 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_hw_probe()
4288 smmu->features |= ARM_SMMU_FEAT_VAX; in arm_smmu_device_hw_probe()
4293 smmu->oas = 32; in arm_smmu_device_hw_probe()
4296 smmu->oas = 36; in arm_smmu_device_hw_probe()
4299 smmu->oas = 40; in arm_smmu_device_hw_probe()
4302 smmu->oas = 42; in arm_smmu_device_hw_probe()
4305 smmu->oas = 44; in arm_smmu_device_hw_probe()
4308 smmu->oas = 52; in arm_smmu_device_hw_probe()
4309 smmu->pgsize_bitmap |= 1ULL << 42; /* 4TB */ in arm_smmu_device_hw_probe()
4312 dev_info(smmu->dev, in arm_smmu_device_hw_probe()
4313 "unknown output address size. Truncating to 48-bit\n"); in arm_smmu_device_hw_probe()
4316 smmu->oas = 48; in arm_smmu_device_hw_probe()
4319 if (arm_smmu_ops.pgsize_bitmap == -1UL) in arm_smmu_device_hw_probe()
4320 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
4322 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_hw_probe()
4325 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(smmu->oas))) in arm_smmu_device_hw_probe()
4326 dev_warn(smmu->dev, in arm_smmu_device_hw_probe()
4329 smmu->ias = max(smmu->ias, smmu->oas); in arm_smmu_device_hw_probe()
4331 if ((smmu->features & ARM_SMMU_FEAT_TRANS_S1) && in arm_smmu_device_hw_probe()
4332 (smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_device_hw_probe()
4333 smmu->features |= ARM_SMMU_FEAT_NESTING; in arm_smmu_device_hw_probe()
4338 smmu->features |= ARM_SMMU_FEAT_SVA; in arm_smmu_device_hw_probe()
4340 dev_info(smmu->dev, "ias %lu-bit, oas %lu-bit (features 0x%08x)\n", in arm_smmu_device_hw_probe()
4341 smmu->ias, smmu->oas, smmu->features); in arm_smmu_device_hw_probe()
4350 const char *uid = kasprintf(GFP_KERNEL, "%u", node->identifier); in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4354 adev = acpi_dev_get_first_match_dev("NVDA200C", uid, -1); in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4357 smmu->impl_dev = &adev->dev; in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4358 smmu->options |= ARM_SMMU_OPT_TEGRA241_CMDQV; in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4359 dev_info(smmu->dev, "found companion CMDQV device: %s\n", in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4360 dev_name(smmu->impl_dev)); in acpi_smmu_dsdt_probe_tegra241_cmdqv()
4375 (struct acpi_iort_smmu_v3 *)node->node_data; in acpi_smmu_iort_probe_model()
4377 switch (iort_smmu->model) { in acpi_smmu_iort_probe_model()
4379 smmu->options |= ARM_SMMU_OPT_PAGE0_REGS_ONLY; in acpi_smmu_iort_probe_model()
4382 smmu->options |= ARM_SMMU_OPT_SKIP_PREFETCH; in acpi_smmu_iort_probe_model()
4393 dev_notice(smmu->dev, "option mask 0x%x\n", smmu->options); in acpi_smmu_iort_probe_model()
4401 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
4407 iort_smmu = (struct acpi_iort_smmu_v3 *)node->node_data; in arm_smmu_device_acpi_probe()
4409 if (iort_smmu->flags & ACPI_IORT_SMMU_V3_COHACC_OVERRIDE) in arm_smmu_device_acpi_probe()
4410 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_acpi_probe()
4412 switch (FIELD_GET(ACPI_IORT_SMMU_V3_HTTU_OVERRIDE, iort_smmu->flags)) { in arm_smmu_device_acpi_probe()
4414 smmu->features |= ARM_SMMU_FEAT_HD; in arm_smmu_device_acpi_probe()
4417 smmu->features |= ARM_SMMU_FEAT_HA; in arm_smmu_device_acpi_probe()
4426 return -ENODEV; in arm_smmu_device_acpi_probe()
4433 struct device *dev = &pdev->dev; in arm_smmu_device_dt_probe()
4435 int ret = -EINVAL; in arm_smmu_device_dt_probe()
4437 if (of_property_read_u32(dev->of_node, "#iommu-cells", &cells)) in arm_smmu_device_dt_probe()
4438 dev_err(dev, "missing #iommu-cells property\n"); in arm_smmu_device_dt_probe()
4440 dev_err(dev, "invalid #iommu-cells value (%d)\n", cells); in arm_smmu_device_dt_probe()
4446 if (of_dma_is_coherent(dev->of_node)) in arm_smmu_device_dt_probe()
4447 smmu->features |= ARM_SMMU_FEAT_COHERENCY; in arm_smmu_device_dt_probe()
4454 if (smmu->options & ARM_SMMU_OPT_PAGE0_REGS_ONLY) in arm_smmu_resource_size()
4474 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
4481 for (i = 0; i < rmr->num_sids; i++) { in arm_smmu_rmr_install_bypass_ste()
4482 ret = arm_smmu_init_sid_strtab(smmu, rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
4484 dev_err(smmu->dev, "RMR SID(0x%x) bypass failed\n", in arm_smmu_rmr_install_bypass_ste()
4485 rmr->sids[i]); in arm_smmu_rmr_install_bypass_ste()
4494 arm_smmu_get_step_for_sid(smmu, rmr->sids[i])); in arm_smmu_rmr_install_bypass_ste()
4498 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_ste()
4505 if (smmu->impl_ops && smmu->impl_ops->device_remove) in arm_smmu_impl_remove()
4506 smmu->impl_ops->device_remove(smmu); in arm_smmu_impl_remove()
4516 struct arm_smmu_device *new_smmu = ERR_PTR(-ENODEV); in arm_smmu_impl_probe()
4519 if (smmu->impl_dev && (smmu->options & ARM_SMMU_OPT_TEGRA241_CMDQV)) in arm_smmu_impl_probe()
4522 if (new_smmu == ERR_PTR(-ENODEV)) in arm_smmu_impl_probe()
4527 ret = devm_add_action_or_reset(new_smmu->dev, arm_smmu_impl_remove, in arm_smmu_impl_probe()
4540 struct device *dev = &pdev->dev; in arm_smmu_device_probe()
4544 return -ENOMEM; in arm_smmu_device_probe()
4545 smmu->dev = dev; in arm_smmu_device_probe()
4547 if (dev->of_node) { in arm_smmu_device_probe()
4562 return -EINVAL; in arm_smmu_device_probe()
4565 return -EINVAL; in arm_smmu_device_probe()
4567 ioaddr = res->start; in arm_smmu_device_probe()
4573 smmu->base = arm_smmu_ioremap(dev, ioaddr, ARM_SMMU_REG_SZ); in arm_smmu_device_probe()
4574 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
4575 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
4578 smmu->page1 = arm_smmu_ioremap(dev, ioaddr + SZ_64K, in arm_smmu_device_probe()
4580 if (IS_ERR(smmu->page1)) in arm_smmu_device_probe()
4581 return PTR_ERR(smmu->page1); in arm_smmu_device_probe()
4583 smmu->page1 = smmu->base; in arm_smmu_device_probe()
4590 smmu->combined_irq = irq; in arm_smmu_device_probe()
4594 smmu->evtq.q.irq = irq; in arm_smmu_device_probe()
4598 smmu->priq.q.irq = irq; in arm_smmu_device_probe()
4602 smmu->gerr_irq = irq; in arm_smmu_device_probe()
4609 /* Initialise in-memory data structures */ in arm_smmu_device_probe()
4626 ret = iommu_device_sysfs_add(&smmu->iommu, dev, NULL, in arm_smmu_device_probe()
4631 ret = iommu_device_register(&smmu->iommu, &arm_smmu_ops, dev); in arm_smmu_device_probe()
4634 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
4645 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
4646 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
4648 iopf_queue_free(smmu->evtq.iopf); in arm_smmu_device_remove()
4649 ida_destroy(&smmu->vmid_map); in arm_smmu_device_remove()
4660 { .compatible = "arm,smmu-v3", },
4673 .name = "arm-smmu-v3",
4686 MODULE_ALIAS("platform:arm-smmu-v3");