Lines Matching +full:control +full:- +full:parent
2 * Copyright (c) 2010 - 2017 Intel Corporation. All rights reserved.
15 * - Redistributions of source code must retain the above
19 * - Redistributions in binary form must reproduce the above
50 * from qib_pcie_params, which every chip-specific
81 qib_early_err(&pdev->dev, "pci enable failed: error %d\n", in qib_pcie_init()
82 -ret); in qib_pcie_init()
88 qib_devinfo(pdev, "pci_request_regions fails: err %d\n", -ret); in qib_pcie_init()
92 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); in qib_pcie_init()
99 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); in qib_pcie_init()
118 * fields required to re-initialize after a chip reset, or for
127 dd->pcidev = pdev; in qib_pcie_ddinit()
133 dd->kregbase = ioremap(addr, len); in qib_pcie_ddinit()
134 if (!dd->kregbase) in qib_pcie_ddinit()
135 return -ENOMEM; in qib_pcie_ddinit()
137 dd->kregend = (u64 __iomem *)((void __iomem *) dd->kregbase + len); in qib_pcie_ddinit()
138 dd->physaddr = addr; /* used for io_remap, etc. */ in qib_pcie_ddinit()
144 dd->pcibar0 = addr; in qib_pcie_ddinit()
145 dd->pcibar1 = addr >> 32; in qib_pcie_ddinit()
146 dd->deviceid = ent->device; /* save for later use */ in qib_pcie_ddinit()
147 dd->vendorid = ent->vendor; in qib_pcie_ddinit()
153 * Do PCIe cleanup, after chip-specific cleanup, etc. Just prior
159 u64 __iomem *base = (void __iomem *) dd->kregbase; in qib_pcie_ddcleanup()
161 dd->kregbase = NULL; in qib_pcie_ddcleanup()
163 if (dd->piobase) in qib_pcie_ddcleanup()
164 iounmap(dd->piobase); in qib_pcie_ddcleanup()
165 if (dd->userbase) in qib_pcie_ddcleanup()
166 iounmap(dd->userbase); in qib_pcie_ddcleanup()
167 if (dd->piovl15base) in qib_pcie_ddcleanup()
168 iounmap(dd->piovl15base); in qib_pcie_ddcleanup()
170 pci_disable_device(dd->pcidev); in qib_pcie_ddcleanup()
171 pci_release_regions(dd->pcidev); in qib_pcie_ddcleanup()
173 pci_set_drvdata(dd->pcidev, NULL); in qib_pcie_ddcleanup()
183 struct pci_dev *pdev = dd->pcidev; in qib_cache_msi_info()
184 u16 control; in qib_cache_msi_info() local
186 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_LO, &dd->msi_lo); in qib_cache_msi_info()
187 pci_read_config_dword(pdev, pos + PCI_MSI_ADDRESS_HI, &dd->msi_hi); in qib_cache_msi_info()
188 pci_read_config_word(pdev, pos + PCI_MSI_FLAGS, &control); in qib_cache_msi_info()
192 pos + ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), in qib_cache_msi_info()
193 &dd->msi_data); in qib_cache_msi_info()
203 if (!pci_is_pcie(dd->pcidev)) { in qib_pcie_params()
206 dd->lbus_width = 1; in qib_pcie_params()
207 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ in qib_pcie_params()
208 nvec = -1; in qib_pcie_params()
212 if (dd->flags & QIB_HAS_INTX) in qib_pcie_params()
215 nvec = pci_alloc_irq_vectors(dd->pcidev, 1, maxvec, flags); in qib_pcie_params()
225 *nent = !dd->pcidev->msix_enabled ? 0 : nvec; in qib_pcie_params()
227 if (dd->pcidev->msi_enabled) in qib_pcie_params()
228 qib_cache_msi_info(dd, dd->pcidev->msi_cap); in qib_pcie_params()
230 pcie_capability_read_word(dd->pcidev, PCI_EXP_LNKSTA, &linkstat); in qib_pcie_params()
232 * speed is bits 0-3, linkwidth is bits 4-8 in qib_pcie_params()
238 dd->lbus_width = linkstat; in qib_pcie_params()
242 dd->lbus_speed = 2500; /* Gen1, 2.5GHz */ in qib_pcie_params()
245 dd->lbus_speed = 5000; /* Gen1, 5GHz */ in qib_pcie_params()
248 dd->lbus_speed = 2500; in qib_pcie_params()
267 snprintf(dd->lbus_info, sizeof(dd->lbus_info), in qib_pcie_params()
268 "PCIe,%uMHz,x%u\n", dd->lbus_speed, dd->lbus_width); in qib_pcie_params()
273 * qib_free_irq - Cleanup INTx and MSI interrupts
282 pci_free_irq(dd->pcidev, 0, dd); in qib_free_irq()
283 pci_free_irq_vectors(dd->pcidev); in qib_free_irq()
297 u16 control; in qib_reinit_intr() local
301 if (!dd->msi_lo) in qib_reinit_intr()
304 pos = dd->pcidev->msi_cap; in qib_reinit_intr()
312 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_LO, in qib_reinit_intr()
313 dd->msi_lo); in qib_reinit_intr()
314 pci_write_config_dword(dd->pcidev, pos + PCI_MSI_ADDRESS_HI, in qib_reinit_intr()
315 dd->msi_hi); in qib_reinit_intr()
316 pci_read_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, &control); in qib_reinit_intr()
317 if (!(control & PCI_MSI_FLAGS_ENABLE)) { in qib_reinit_intr()
318 control |= PCI_MSI_FLAGS_ENABLE; in qib_reinit_intr()
319 pci_write_config_word(dd->pcidev, pos + PCI_MSI_FLAGS, in qib_reinit_intr()
320 control); in qib_reinit_intr()
323 pci_write_config_word(dd->pcidev, pos + in qib_reinit_intr()
324 ((control & PCI_MSI_FLAGS_64BIT) ? 12 : 8), in qib_reinit_intr()
325 dd->msi_data); in qib_reinit_intr()
330 if (!ret && (dd->flags & QIB_HAS_INTX)) in qib_reinit_intr()
334 pci_set_master(dd->pcidev); in qib_reinit_intr()
341 * to move all the pcie code out of the chip-specific driver code.
345 pci_read_config_word(dd->pcidev, PCI_COMMAND, cmd); in qib_pcie_getcmd()
346 pci_read_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); in qib_pcie_getcmd()
347 pci_read_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); in qib_pcie_getcmd()
354 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_0, in qib_pcie_reenable()
355 dd->pcibar0); in qib_pcie_reenable()
358 r = pci_write_config_dword(dd->pcidev, PCI_BASE_ADDRESS_1, in qib_pcie_reenable()
359 dd->pcibar1); in qib_pcie_reenable()
362 /* now re-enable memory access, and restore cosmetic settings */ in qib_pcie_reenable()
363 pci_write_config_word(dd->pcidev, PCI_COMMAND, cmd); in qib_pcie_reenable()
364 pci_write_config_byte(dd->pcidev, PCI_INTERRUPT_LINE, iline); in qib_pcie_reenable()
365 pci_write_config_byte(dd->pcidev, PCI_CACHE_LINE_SIZE, cline); in qib_pcie_reenable()
366 r = pci_enable_device(dd->pcidev); in qib_pcie_reenable()
385 struct pci_dev *parent; in qib_tune_pcie_coalesce() local
392 /* Find out supported and configured values for parent (root) */ in qib_tune_pcie_coalesce()
393 parent = dd->pcidev->bus->self; in qib_tune_pcie_coalesce()
394 if (parent->bus->parent) { in qib_tune_pcie_coalesce()
395 qib_devinfo(dd->pcidev, "Parent not root\n"); in qib_tune_pcie_coalesce()
398 if (!pci_is_pcie(parent)) in qib_tune_pcie_coalesce()
400 if (parent->vendor != 0x8086) in qib_tune_pcie_coalesce()
404 * - bit 12: Max_rdcmp_Imt_EN: need to set to 1 in qib_tune_pcie_coalesce()
405 * - bit 11: COALESCE_FORCE: need to set to 0 in qib_tune_pcie_coalesce()
406 * - bit 10: COALESCE_EN: need to set to 1 in qib_tune_pcie_coalesce()
410 * also: - bit 25:24: COALESCE_MODE, need to set to 0 in qib_tune_pcie_coalesce()
412 devid = parent->device; in qib_tune_pcie_coalesce()
415 if (parent->revision <= 0xb2) in qib_tune_pcie_coalesce()
436 pci_read_config_dword(parent, 0x48, &val); in qib_tune_pcie_coalesce()
439 pci_write_config_dword(parent, 0x48, val); in qib_tune_pcie_coalesce()
443 * BIOS may not set PCIe bus-utilization parameters for best performance.
452 struct pci_dev *parent; in qib_tune_pcie_caps() local
456 /* Find out supported and configured values for parent (root) */ in qib_tune_pcie_caps()
457 parent = dd->pcidev->bus->self; in qib_tune_pcie_caps()
458 if (!pci_is_root_bus(parent->bus)) { in qib_tune_pcie_caps()
459 qib_devinfo(dd->pcidev, "Parent not root\n"); in qib_tune_pcie_caps()
463 if (!pci_is_pcie(parent) || !pci_is_pcie(dd->pcidev)) in qib_tune_pcie_caps()
466 rc_mpss = parent->pcie_mpss; in qib_tune_pcie_caps()
467 rc_mps = ffs(pcie_get_mps(parent)) - 8; in qib_tune_pcie_caps()
469 ep_mpss = dd->pcidev->pcie_mpss; in qib_tune_pcie_caps()
470 ep_mps = ffs(pcie_get_mps(dd->pcidev)) - 8; in qib_tune_pcie_caps()
482 pcie_set_mps(parent, 128 << rc_mps); in qib_tune_pcie_caps()
487 pcie_set_mps(dd->pcidev, 128 << ep_mps); in qib_tune_pcie_caps()
493 * which is code '5' (log2(4096) - 7) in qib_tune_pcie_caps()
500 rc_mrrs = pcie_get_readrq(parent); in qib_tune_pcie_caps()
501 ep_mrrs = pcie_get_readrq(dd->pcidev); in qib_tune_pcie_caps()
505 pcie_set_readrq(parent, rc_mrrs); in qib_tune_pcie_caps()
509 pcie_set_readrq(dd->pcidev, ep_mrrs); in qib_tune_pcie_caps()
539 dd->flags &= ~QIB_PRESENT; in qib_pci_error_detected()
561 if (dd && dd->pport) { in qib_pci_mmio_enabled()
562 words = dd->f_portcntr(dd->pport, QIBPORTCNTR_WORDRCV); in qib_pci_mmio_enabled()
587 * unlike sysfs-requested reset. Better than in qib_pci_resume()
590 qib_init(dd, 1); /* same as re-init after reset */ in qib_pci_resume()