Lines Matching refs:cspec
880 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg()
882 return readq(&dd->cspec->cregbase[regno]); in read_7322_creg()
889 if (!dd->cspec->cregbase || !(dd->flags & QIB_PRESENT)) in read_7322_creg32()
891 return readl(&dd->cspec->cregbase[regno]); in read_7322_creg32()
1499 if ((op & QIB_SDMA_SENDCTRL_OP_DRAIN) && ppd->dd->cspec->r1) in qib_7322_sdma_sendctrl()
1644 errs &= dd->cspec->errormask; in handle_7322_errors()
1645 msg = dd->cspec->emsgbuf; in handle_7322_errors()
1650 qib_7322_handle_hwerrors(dd, msg, sizeof(dd->cspec->emsgbuf)); in handle_7322_errors()
1672 err_decode(msg, sizeof(dd->cspec->emsgbuf), errs & ~mask, in handle_7322_errors()
1719 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_error_tasklet()
1782 if (!ppd->dd->cspec->r1) in handle_serdes_issues()
1803 if (!ppd->dd->cspec->r1 && in handle_serdes_issues()
1818 ppd->dd->cspec->r1 ? in handle_serdes_issues()
1996 qib_write_kreg(dd, kr_intmask, dd->cspec->int_enable_mask); in qib_7322_set_intr_state()
1999 if (dd->cspec->num_msix_entries) { in qib_7322_set_intr_state()
2052 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_7322_clear_freeze()
2096 hwerrs &= dd->cspec->hwerrmask; in qib_7322_handle_hwerrors()
2111 dd->cspec->stay_in_freeze) { in qib_7322_handle_hwerrors()
2131 dd->cspec->hwerrmask &= ~HWE_MASK(PowerOnBISTFailed); in qib_7322_handle_hwerrors()
2132 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_handle_hwerrors()
2203 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_init_hwerrors()
2209 dd->cspec->errormask = qib_read_kreg64(dd, kr_errmask); in qib_7322_init_hwerrors()
2226 dd->cspec->errormask |= QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2228 dd->cspec->errormask &= ~QIB_E_SPIOARMLAUNCH; in qib_set_7322_armlaunch()
2229 qib_write_kreg(dd, kr_errmask, dd->cspec->errormask); in qib_set_7322_armlaunch()
2479 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2482 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_bringup_serdes()
2510 if (ppd->dd->cspec->r1) in qib_7322_mini_quiet_serdes()
2620 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2621 extctl = dd->cspec->extctrl & (ppd->port == 1 ? in qib_setup_7322_setextled()
2635 dd->cspec->extctrl = extctl; in qib_setup_7322_setextled()
2636 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_setup_7322_setextled()
2637 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_setextled()
2661 dd->cspec->dca_ctrl = 0; in qib_7322_notify_dca()
2663 dd->cspec->dca_ctrl); in qib_7322_notify_dca()
2673 struct qib_chip_specific *cspec = dd->cspec; in qib_update_rhdrq_dca() local
2677 if (cspec->rhdr_cpu[rcd->ctxt] != cpu) { in qib_update_rhdrq_dca()
2680 cspec->rhdr_cpu[rcd->ctxt] = cpu; in qib_update_rhdrq_dca()
2682 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] &= rmp->mask; in qib_update_rhdrq_dca()
2683 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx] |= in qib_update_rhdrq_dca()
2687 (long long) cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2689 cspec->dca_rcvhdr_ctrl[rmp->shadow_inx]); in qib_update_rhdrq_dca()
2690 cspec->dca_ctrl |= SYM_MASK(DCACtrlA, RcvHdrqDCAEnable); in qib_update_rhdrq_dca()
2691 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_rhdrq_dca()
2698 struct qib_chip_specific *cspec = dd->cspec; in qib_update_sdma_dca() local
2703 if (cspec->sdma_cpu[pidx] != cpu) { in qib_update_sdma_dca()
2704 cspec->sdma_cpu[pidx] = cpu; in qib_update_sdma_dca()
2705 cspec->dca_rcvhdr_ctrl[4] &= ~(ppd->hw_pidx ? in qib_update_sdma_dca()
2708 cspec->dca_rcvhdr_ctrl[4] |= in qib_update_sdma_dca()
2715 (long long) cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2717 cspec->dca_rcvhdr_ctrl[4]); in qib_update_sdma_dca()
2718 cspec->dca_ctrl |= ppd->hw_pidx ? in qib_update_sdma_dca()
2721 qib_write_kreg(dd, KREG_IDX(DCACtrlA), cspec->dca_ctrl); in qib_update_sdma_dca()
2727 struct qib_chip_specific *cspec = dd->cspec; in qib_setup_dca() local
2730 for (i = 0; i < ARRAY_SIZE(cspec->rhdr_cpu); i++) in qib_setup_dca()
2731 cspec->rhdr_cpu[i] = -1; in qib_setup_dca()
2732 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2733 cspec->sdma_cpu[i] = -1; in qib_setup_dca()
2734 cspec->dca_rcvhdr_ctrl[0] = in qib_setup_dca()
2739 cspec->dca_rcvhdr_ctrl[1] = in qib_setup_dca()
2744 cspec->dca_rcvhdr_ctrl[2] = in qib_setup_dca()
2749 cspec->dca_rcvhdr_ctrl[3] = in qib_setup_dca()
2754 cspec->dca_rcvhdr_ctrl[4] = in qib_setup_dca()
2757 for (i = 0; i < ARRAY_SIZE(cspec->sdma_cpu); i++) in qib_setup_dca()
2759 cspec->dca_rcvhdr_ctrl[i]); in qib_setup_dca()
2760 for (i = 0; i < cspec->num_msix_entries; i++) in qib_setup_dca()
2808 dd->cspec->main_int_mask = ~0ULL; in qib_7322_free_irq()
2810 for (i = 0; i < dd->cspec->num_msix_entries; i++) { in qib_7322_free_irq()
2812 if (dd->cspec->msix_entries[i].arg) { in qib_7322_free_irq()
2818 free_cpumask_var(dd->cspec->msix_entries[i].mask); in qib_7322_free_irq()
2820 dd->cspec->msix_entries[i].arg); in qib_7322_free_irq()
2825 if (!dd->cspec->num_msix_entries) in qib_7322_free_irq()
2828 dd->cspec->num_msix_entries = 0; in qib_7322_free_irq()
2846 dd->cspec->dca_ctrl = 0; in qib_setup_7322_cleanup()
2847 qib_write_kreg(dd, KREG_IDX(DCACtrlA), dd->cspec->dca_ctrl); in qib_setup_7322_cleanup()
2852 kfree(dd->cspec->cntrs); in qib_setup_7322_cleanup()
2853 bitmap_free(dd->cspec->sendchkenable); in qib_setup_7322_cleanup()
2854 bitmap_free(dd->cspec->sendgrhchk); in qib_setup_7322_cleanup()
2855 bitmap_free(dd->cspec->sendibchk); in qib_setup_7322_cleanup()
2856 kfree(dd->cspec->msix_entries); in qib_setup_7322_cleanup()
2864 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2865 dd->cspec->gpio_mask &= ~mask; in qib_setup_7322_cleanup()
2866 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_setup_7322_cleanup()
2867 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_setup_7322_cleanup()
2924 qib_write_kreg(dd, kr_intmask, (dd->cspec->int_enable_mask & ~kills)); in unknown_7322_ibits()
2965 if (gpiostatus & dd->cspec->gpio_mask & mask) { in unknown_7322_gpio_intr()
2987 dd->cspec->gpio_mask &= ~gpio_irq; in unknown_7322_gpio_intr()
2988 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in unknown_7322_gpio_intr()
3019 u32 timeout = dd->cspec->rcvavail_timeout[rcd->ctxt]; in adjust_rcv_timeout()
3032 dd->cspec->rcvavail_timeout[rcd->ctxt] = timeout; in adjust_rcv_timeout()
3075 istat &= dd->cspec->main_int_mask; in qib_7322intr()
3306 if (!dd->cspec->msix_entries[msixnum].dca) in reset_dca_notifier()
3312 dd->cspec->msix_entries[msixnum].notifier = NULL; in reset_dca_notifier()
3317 struct qib_msix_entry *m = &dd->cspec->msix_entries[msixnum]; in setup_dca_notifier()
3385 if (!dd->cspec->num_msix_entries) { in qib_setup_7322_interrupt()
3397 dd->cspec->main_int_mask = ~0ULL; in qib_setup_7322_interrupt()
3418 for (i = 0; msixnum < dd->cspec->num_msix_entries; i++) { in qib_setup_7322_interrupt()
3477 dd->cspec->msix_entries[msixnum].arg = arg; in qib_setup_7322_interrupt()
3479 dd->cspec->msix_entries[msixnum].dca = dca; in qib_setup_7322_interrupt()
3480 dd->cspec->msix_entries[msixnum].rcv = in qib_setup_7322_interrupt()
3494 &dd->cspec->msix_entries[msixnum].mask, in qib_setup_7322_interrupt()
3498 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3505 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3509 dd->cspec->msix_entries[msixnum].mask); in qib_setup_7322_interrupt()
3516 dd->cspec->main_int_mask = mask; in qib_setup_7322_interrupt()
3616 msix_entries = dd->cspec->num_msix_entries; in qib_do_7322_reset()
3625 msix_vecsave = kmalloc_array(2 * dd->cspec->num_msix_entries, in qib_do_7322_reset()
3718 dd->cspec->num_msix_entries = msix_entries; in qib_do_7322_reset()
3853 if (rcd->dd->cspec->r1) in qib_7322_get_base_info()
3879 dd->cspec->numctxts = nchipctxts; in qib_7322_config_ctxts()
3912 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3927 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in qib_7322_config_ctxts()
3930 dd->cspec->rcvegrcnt = qib_read_kreg32(dd, kr_rcvegrcnt); in qib_7322_config_ctxts()
3932 dd->rcvhdrcnt = max(dd->cspec->rcvegrcnt, qib_rcvhdrcnt); in qib_7322_config_ctxts()
3934 dd->rcvhdrcnt = 2 * max(dd->cspec->rcvegrcnt, in qib_7322_config_ctxts()
4278 if (ppd->dd->cspec->r1) { in qib_7322_set_ib_cfg()
4464 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4566 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in rcvctrl_7322_mod()
4978 dd->cspec->ncntrs = i; in init_7322_cntrnames()
4981 dd->cspec->cntrnamelen = sizeof(cntr7322names) - 1; in init_7322_cntrnames()
4983 dd->cspec->cntrnamelen = 1 + s - cntr7322names; in init_7322_cntrnames()
4984 dd->cspec->cntrs = kmalloc_array(dd->cspec->ncntrs, sizeof(u64), in init_7322_cntrnames()
4989 dd->cspec->nportcntrs = i - 1; in init_7322_cntrnames()
4990 dd->cspec->portcntrnamelen = sizeof(portcntr7322names) - 1; in init_7322_cntrnames()
4993 kmalloc_array(dd->cspec->nportcntrs, sizeof(u64), in init_7322_cntrnames()
5004 ret = dd->cspec->cntrnamelen; in qib_read_7322cntrs()
5010 u64 *cntr = dd->cspec->cntrs; in qib_read_7322cntrs()
5013 ret = dd->cspec->ncntrs * sizeof(u64); in qib_read_7322cntrs()
5020 for (i = 0; i < dd->cspec->ncntrs; i++) in qib_read_7322cntrs()
5039 ret = dd->cspec->portcntrnamelen; in qib_read_7322portcntrs()
5049 ret = dd->cspec->nportcntrs * sizeof(u64); in qib_read_7322portcntrs()
5056 for (i = 0; i < dd->cspec->nportcntrs; i++) { in qib_read_7322portcntrs()
5125 ppd->dd->cspec->r1 ? in qib_get_7322_faststats()
5139 if (!dd->cspec->num_msix_entries) in qib_7322_intr_fallback()
5170 dd->cspec->hwerrmask & ~HWE_MASK(statusValidNoEop)); in qib_7322_mini_pcs_reset()
5182 qib_write_kreg(dd, kr_hwerrmask, dd->cspec->hwerrmask); in qib_7322_mini_pcs_reset()
5628 if (ppd->dd->cspec->r1 && ppd->cpspec->ipg_tries <= 10) in qib_7322_ib_updown()
5680 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5681 dd->cspec->extctrl &= ~((u64)mask << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5682 dd->cspec->extctrl |= ((u64) dir << SYM_LSB(EXTCtrl, GPIOOe)); in gpio_7322_mod()
5683 new_out = (dd->cspec->gpio_out & ~mask) | out; in gpio_7322_mod()
5685 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in gpio_7322_mod()
5687 dd->cspec->gpio_out = new_out; in gpio_7322_mod()
5688 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in gpio_7322_mod()
5779 dd->cspec->cregbase = (u64 __iomem *)(cregbase + in qib_7322_set_baseaddrs()
5955 if (!ret && !ppd->dd->cspec->r1) { in qsfp_7322_event()
6003 spin_lock_irqsave(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6004 dd->cspec->extctrl |= (mod_prs_bit << SYM_LSB(EXTCtrl, GPIOInvert)); in qib_init_7322_qsfp()
6005 dd->cspec->gpio_mask |= mod_prs_bit; in qib_init_7322_qsfp()
6006 qib_write_kreg(dd, kr_extctrl, dd->cspec->extctrl); in qib_init_7322_qsfp()
6007 qib_write_kreg(dd, kr_gpio_mask, dd->cspec->gpio_mask); in qib_init_7322_qsfp()
6008 spin_unlock_irqrestore(&dd->cspec->gpio_lock, flags); in qib_init_7322_qsfp()
6247 if (ppd->dd->cspec->r1) in write_7322_init_portregs()
6278 spin_lock_irqsave(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6280 spin_unlock_irqrestore(&dd->cspec->rcvmod_lock, flags); in write_7322_initregs()
6316 dd->cspec->rcvavail_timeout[i] = rcv_int_timeout; in write_7322_initregs()
6356 dd->cspec = (struct qib_chip_specific *)(ppd + 2); in qib_init_7322_variables()
6358 ppd[0].cpspec = (struct qib_chippport_specific *)(dd->cspec + 1); in qib_init_7322_variables()
6363 spin_lock_init(&dd->cspec->rcvmod_lock); in qib_init_7322_variables()
6364 spin_lock_init(&dd->cspec->gpio_lock); in qib_init_7322_variables()
6379 dd->cspec->r1 = dd->minrev == 1; in qib_init_7322_variables()
6387 dd->cspec->sendchkenable = bitmap_zalloc(sbufcnt, GFP_KERNEL); in qib_init_7322_variables()
6388 dd->cspec->sendgrhchk = bitmap_zalloc(sbufcnt, GFP_KERNEL); in qib_init_7322_variables()
6389 dd->cspec->sendibchk = bitmap_zalloc(sbufcnt, GFP_KERNEL); in qib_init_7322_variables()
6390 if (!dd->cspec->sendchkenable || !dd->cspec->sendgrhchk || in qib_init_7322_variables()
6391 !dd->cspec->sendibchk) { in qib_init_7322_variables()
6423 dd->cspec->int_enable_mask = QIB_I_BITSEXTANT; in qib_init_7322_variables()
6425 dd->cspec->hwerrmask = ~0ULL; in qib_init_7322_variables()
6428 dd->cspec->hwerrmask &= in qib_init_7322_variables()
6446 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6450 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6461 dd->cspec->hwerrmask &= ~(SYM_MASK(HwErrMask, in qib_init_7322_variables()
6465 dd->cspec->int_enable_mask &= ~( in qib_init_7322_variables()
6526 if (ppd->dd->cspec->r1) in qib_init_7322_variables()
6635 dd->cspec->sdmabufcnt = dd->piobcnt4k; in qib_init_7322_variables()
6638 dd->cspec->sdmabufcnt = 0; in qib_init_7322_variables()
6641 dd->cspec->lastbuf_for_pio = dd->piobcnt2k + dd->piobcnt4k - in qib_init_7322_variables()
6642 dd->cspec->sdmabufcnt; in qib_init_7322_variables()
6643 dd->lastctxt_piobuf = dd->cspec->lastbuf_for_pio - sbufs; in qib_init_7322_variables()
6644 dd->cspec->lastbuf_for_pio--; /* range is <= , not < */ in qib_init_7322_variables()
6645 dd->last_pio = dd->cspec->lastbuf_for_pio; in qib_init_7322_variables()
6657 dd->cspec->updthresh_dflt = updthresh; in qib_init_7322_variables()
6658 dd->cspec->updthresh = updthresh; in qib_init_7322_variables()
6689 last = dd->cspec->lastbuf_for_pio; in qib_7322_getsendbuf()
6856 n = dd->cspec->sdmabufcnt / dd->num_pports; /* no remainder */ in init_sdma_7322_regs()
6858 n = dd->cspec->sdmabufcnt; /* failsafe for init */ in init_sdma_7322_regs()
6861 dd->cspec->sdmabufcnt); in init_sdma_7322_regs()
6986 rcd->rcvegrcnt = rcd->dd->cspec->rcvegrcnt; in qib_7322_init_ctxt()
7047 clear_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7059 set_bit(i, dd->cspec->sendchkenable); in qib_7322_txchk_change()
7065 set_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7066 clear_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7071 dd->cspec->updthresh != dd->cspec->updthresh_dflt in qib_7322_txchk_change()
7075 < dd->cspec->updthresh_dflt) in qib_7322_txchk_change()
7080 dd->cspec->updthresh = dd->cspec->updthresh_dflt; in qib_7322_txchk_change()
7082 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7093 clear_bit(i, dd->cspec->sendibchk); in qib_7322_txchk_change()
7094 set_bit(i, dd->cspec->sendgrhchk); in qib_7322_txchk_change()
7098 / rcd->subctxt_cnt) - 1) < dd->cspec->updthresh) { in qib_7322_txchk_change()
7099 dd->cspec->updthresh = (rcd->piocnt / in qib_7322_txchk_change()
7102 dd->sendctrl |= (dd->cspec->updthresh & in qib_7322_txchk_change()
7117 dd->cspec->sendchkenable[i]); in qib_7322_txchk_change()
7121 dd->cspec->sendgrhchk[i]); in qib_7322_txchk_change()
7123 dd->cspec->sendibchk[i]); in qib_7322_txchk_change()
7260 dd->cspec->msix_entries = kcalloc(tabsize, in qib_init_iba7322_funcs()
7263 if (!dd->cspec->msix_entries) in qib_init_iba7322_funcs()
7270 dd->cspec->num_msix_entries = tabsize; in qib_init_iba7322_funcs()
7811 if (ppd->dd->cspec->r1) in serdes_7322_init()
7886 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_old()
7896 ppd->dd->cspec->r1 ? in serdes_7322_init_old()
7906 if (!ppd->dd->cspec->r1) { in serdes_7322_init_old()
7966 if (!ppd->dd->cspec->r1) { in serdes_7322_init_new()
8066 le_val = (ppd->dd->cspec->r1 || IS_QME(ppd->dd)) ? 0xb6c0 : 0x6bac; in serdes_7322_init_new()
8087 ppd->dd->cspec->r1 ? in serdes_7322_init_new()
8202 if (!ppd->dd->cspec->r1) in force_h1()
8403 if (!ppd->dd->cspec->r1) in setup_7322_link_recovery()
8406 dd->cspec->recovery_ports_initted++; in setup_7322_link_recovery()
8409 if (!both && dd->cspec->recovery_ports_initted == 1) { in setup_7322_link_recovery()
8437 if (dd->cspec->recovery_ports_initted != 1) in check_7322_rxe_status()
8450 ppd->dd->cspec->stay_in_freeze = 1; in check_7322_rxe_status()