44 	MTHCA_NUM_ASYNC_EQE = 0x80,
45 	MTHCA_NUM_CMD_EQE   = 0x80,
46 	MTHCA_NUM_SPARE_EQE = 0x80,
47 	MTHCA_EQ_ENTRY_SIZE = 0x20
68 #define MTHCA_EQ_STATUS_OK          ( 0 << 28)
71 #define MTHCA_EQ_OWNER_SW           ( 0 << 24)
81 	MTHCA_EVENT_TYPE_COMP       	    = 0x00,
82 	MTHCA_EVENT_TYPE_PATH_MIG   	    = 0x01,
83 	MTHCA_EVENT_TYPE_COMM_EST   	    = 0x02,
84 	MTHCA_EVENT_TYPE_SQ_DRAINED 	    = 0x03,
85 	MTHCA_EVENT_TYPE_SRQ_QP_LAST_WQE    = 0x13,
86 	MTHCA_EVENT_TYPE_SRQ_LIMIT	    = 0x14,
87 	MTHCA_EVENT_TYPE_CQ_ERROR   	    = 0x04,
88 	MTHCA_EVENT_TYPE_WQ_CATAS_ERROR     = 0x05,
89 	MTHCA_EVENT_TYPE_EEC_CATAS_ERROR    = 0x06,
90 	MTHCA_EVENT_TYPE_PATH_MIG_FAILED    = 0x07,
91 	MTHCA_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10,
92 	MTHCA_EVENT_TYPE_WQ_ACCESS_ERROR    = 0x11,
93 	MTHCA_EVENT_TYPE_SRQ_CATAS_ERROR    = 0x12,
94 	MTHCA_EVENT_TYPE_LOCAL_CATAS_ERROR  = 0x08,
95 	MTHCA_EVENT_TYPE_PORT_CHANGE        = 0x09,
96 	MTHCA_EVENT_TYPE_EQ_OVERFLOW        = 0x0f,
97 	MTHCA_EVENT_TYPE_ECC_DETECT         = 0x0e,
98 	MTHCA_EVENT_TYPE_CMD                = 0x0a
163 #define  MTHCA_EQ_ENTRY_OWNER_SW      (0 << 7)
209 	mthca_write64(MTHCA_EQ_DB_REQ_NOT | eqn, 0,  in tavor_eq_req_not()
264 	int eqes_found = 0;  in mthca_eq_int()
265 	int set_ci = 0;  in mthca_eq_int()
276 			disarm_cqn = be32_to_cpu(eqe->event.comp.cqn) & 0xffffff;  in mthca_eq_int()
282 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
287 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
292 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
297 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
302 			mthca_srq_event(dev, be32_to_cpu(eqe->event.srq.srqn) & 0xffffff,  in mthca_eq_int()
307 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
312 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
317 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
322 			mthca_qp_event(dev, be32_to_cpu(eqe->event.qp.qpn) & 0xffffff,  in mthca_eq_int()
336 				    eqe->subtype == 0x4);  in mthca_eq_int()
343 				   be32_to_cpu(eqe->event.cq_err.cqn) & 0xffffff);  in mthca_eq_int()
380 			set_ci = 0;  in mthca_eq_int()
407 	for (i = 0; i < MTHCA_NUM_EQ; ++i)  in mthca_tavor_interrupt()
434 	int work = 0;  in mthca_arbel_interrupt()
440 	for (i = 0; i < MTHCA_NUM_EQ; ++i)  in mthca_arbel_interrupt()
487 	for (i = 0; i < npages; ++i)  in mthca_create_eq()
499 	for (i = 0; i < npages; ++i) {  in mthca_create_eq()
511 	for (i = 0; i < eq->nent; ++i)  in mthca_create_eq()
520 				  0, npages * PAGE_SIZE,  in mthca_create_eq()
527 	memset(eq_context, 0, sizeof *eq_context);  in mthca_create_eq()
555 	eq->cons_index = 0;  in mthca_create_eq()
571 	for (i = 0; i < npages; ++i)  in mthca_create_eq()
607 	if (0) {  in mthca_free_eq()
609 		for (i = 0; i < sizeof (struct mthca_eq_context) / 4; ++i) {  in mthca_free_eq()
610 			if (i % 4 == 0)  in mthca_free_eq()
613 			if ((i + 1) % 4 == 0)  in mthca_free_eq()
619 	for (i = 0; i < npages; ++i)  in mthca_free_eq()
634 	for (i = 0; i < MTHCA_NUM_EQ; ++i)  in mthca_free_irqs()
638 			dev->eq_table.eq[i].have_irq = 0;  in mthca_free_irqs()
646 	phys_addr_t base = pci_resource_start(dev->pdev, 0);  in mthca_map_reg()
652 	return 0;  in mthca_map_reg()
665 		if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &  in mthca_map_eq_regs()
674 		 * Add 4 because we limit ourselves to EQs 0 ... 31,  in mthca_map_eq_regs()
677 		if (mthca_map_reg(dev, ((pci_resource_len(dev->pdev, 0) - 1) &  in mthca_map_eq_regs()
685 		if (mthca_map_reg(dev, (pci_resource_len(dev->pdev, 0) - 1) &  in mthca_map_eq_regs()
712 	return 0;  in mthca_map_eq_regs()
743 		dma_map_page(&dev->pdev->dev, dev->eq_table.icm_page, 0,  in mthca_map_eq_icm()
786 		dev->eq_table.clr_mask = 0;  in mthca_init_eq_table()
791 			(dev->eq_table.inta_pin < 32 ? 4 : 0);  in mthca_init_eq_table()
794 	dev->eq_table.arm_mask = 0;  in mthca_init_eq_table()
823 		for (i = 0; i < MTHCA_NUM_EQ; ++i) {  in mthca_init_eq_table()
832 					  0, dev->eq_table.eq[i].irq_name,  in mthca_init_eq_table()
839 		snprintf(dev->eq_table.eq[0].irq_name, IB_DEVICE_NAME_MAX,  in mthca_init_eq_table()
845 				  IRQF_SHARED, dev->eq_table.eq[0].irq_name, dev);  in mthca_init_eq_table()
852 			   0, dev->eq_table.eq[MTHCA_EQ_ASYNC].eqn);  in mthca_init_eq_table()
858 			   0, dev->eq_table.eq[MTHCA_EQ_CMD].eqn);  in mthca_init_eq_table()
863 	for (i = 0; i < MTHCA_NUM_EQ; ++i)  in mthca_init_eq_table()
869 	return 0;  in mthca_init_eq_table()
900 	for (i = 0; i < MTHCA_NUM_EQ; ++i)  in mthca_cleanup_eq_table()