Lines Matching +full:4 +full:wire
257 return calc_sig(wqe, (*((u8 *)wqe + 8) & 0x3f) << 4); in wq_sig()
286 *wqe_sz + (offset >> 4), in set_data_inl_seg()
363 struct ib_sig_domain *wire = &sig_attrs->wire; in mlx5_set_bsf() local
386 /* Wire domain */ in mlx5_set_bsf()
387 switch (sig_attrs->wire.sig_type) { in mlx5_set_bsf()
391 if (mem->sig.dif.pi_interval == wire->sig.dif.pi_interval && in mlx5_set_bsf()
392 mem->sig_type == wire->sig_type) { in mlx5_set_bsf()
394 basic->bsf_size_sbs |= 1 << 4; in mlx5_set_bsf()
395 if (mem->sig.dif.bg_type == wire->sig.dif.bg_type) in mlx5_set_bsf()
396 basic->wire.copy_byte_mask |= MLX5_CPY_GRD_MASK; in mlx5_set_bsf()
397 if (mem->sig.dif.app_tag == wire->sig.dif.app_tag) in mlx5_set_bsf()
398 basic->wire.copy_byte_mask |= MLX5_CPY_APP_MASK; in mlx5_set_bsf()
399 if (mem->sig.dif.ref_tag == wire->sig.dif.ref_tag) in mlx5_set_bsf()
400 basic->wire.copy_byte_mask |= MLX5_CPY_REF_MASK; in mlx5_set_bsf()
402 basic->wire.bs_selector = in mlx5_set_bsf()
403 bs_selector(wire->sig.dif.pi_interval); in mlx5_set_bsf()
406 mlx5_fill_inl_bsf(wire, &bsf->w_inl); in mlx5_set_bsf()
683 *size = ALIGN(*size, MLX5_SEND_WQE_BB >> 4); in set_reg_wr()
711 for (i = 0, j = 0; i < size_16 * 4; i += 4, j += 4) { in dump_wqe()
920 &sig_attrs->wire, mr->sig->psv_wire.psv_idx, in handle_reg_mr_integrity()